Abstract: A method of operating a terminal device (101) includes configuring a data connection (189) on a wireless link (114) between the terminal device (101) and a network (100) based on a first control signal (4001-4003) native to a first layer (255) of a transmission protocol stack (250) associated with the wireless link (114). The method also includes participating in a data communication via the data connection (189). The method also includes receiving a second control signal (205) native to a second layer (251) of the transmission protocol stack (250), the second layer (251) being arranged lower in hierarchy of the transmission protocol stack (250) than the first layer (255). The method also includes in response to receiving the second control signal (205): activating a discontinuous reception (390) for the data communication.

Abstract: Aspects described herein relate to determining a multicast broadcast (MB) bandwidth size for receiving an MB service, the MB bandwidth being different than each bandwidth size in the set of multiple configurable bandwidth sizes for receiving unicast services.

Abstract: Some of the present implementations provide a method for assembling a target SIB for a target service. The method receives, from a first cell on a first frequency carrier, a plurality of SIB segments of the target SIB, each of the plurality of SIB segments associated with a corresponding value tag. The method stores a first SIB segment in the plurality of SIB segments in a memory of the UE. For each subsequent SIB segment in the plurality of SIB segments, the method determines whether a corresponding value tag of the subsequent SIB segment is the same as the corresponding value tag of the first SIB segment and if they are the same, stores the subsequent SIB segment in the memory of the UE. The method then assembles the target SIB using the stored plurality of SIB segments.

Abstract: An instruction set architecture including instructions for a processor and instructions for a coprocessor may include synchronizing instructions that may be used to begin and end instruction sequences that include coprocessor instructions (coprocessor sequences). If a terminating synchronizing instruction is followed by an initial synchronizing instruction and the pair are detected in the coprocessor concurrently, the coprocessor may suppress execution of the pair of instructions.

Abstract: Systems, apparatuses, and methods for efficient parallel execution of multiple work units in a processor by reducing a number of memory accesses are disclosed. A computing system includes a processor core with a parallel data architecture. The processor core executes a software application with matrix operations. The processor core supports the broadcast of shared data to multiple compute units of the processor core. A compiler or other code assigns thread groups to compute units based on detecting shared data among the compute units. Rather than send multiple read accesses to a memory subsystem for the shared data, the processor core generates a single access request. The single access request includes information to identify the multiple compute units for receiving the shared data when broadcasted by the processor core.

Abstract: Techniques for transmitting and receiving wireless communications over an unlicensed radio frequency spectrum band are disclosed, including techniques for transmitting and receiving service information blocks over the unlicensed radio frequency spectrum band, techniques for gaining access to the unlicensed radio frequency spectrum band by performing extended clear channel assessments (eCCAs), techniques for transmitting and receiving synchronization signals and reference signals over the unlicensed radio frequency spectrum band, techniques for communicating locations of reference signals, and techniques for communicating availability of certain resources to be combined across multiple different transmissions.

Abstract: In one embodiment, a microprocessor, comprising: a branch prediction table comprising plural entries, wherein at least a portion of the plural entries corresponds to an indirect branch type; and an indirect valid table; wherein based on an indirect branch instruction fetch, an entry corresponding to an indirect branch instruction in the branch prediction table is configured as invalid based on clearing a corresponding entry in the indirect valid table.

Abstract: A system and method determines a unique performance benchmark for specific computer object code for a particular microprocessor. By generating multiple unique benchmarks for a single, same code module on multiple different processors, the method determines which processor is optimal for the code module. By generating for a single designated processor a performance benchmark for each code modules of multiple modules, where the multiple modules have a same/similar functionality but variations in detailed code or algorithms, the system and method identifies code variation(s) which is/are optimal for the single designated processor. The system and method may entail first extracting selected features of object code (as actually executed) into a code profile, and then generating the performance benchmark based on the code profile and in machine-level timing data for the selected microprocessor. In this way, code security is achieved by fire-walling the object code from the second stage of the method.

Abstract: Techniques for receiving repeatedly transmitted broadcast information appropriately are disclosed. One aspect of the present invention relates to a base station including a communication control unit configured to control radio communication with user equipment and a broadcast information transmission unit configured to transmit broadcast information, wherein the broadcast information transmission unit includes scheduling information for second system information in first system information and broadcasts the second system information in accordance with the scheduling information.

Abstract: An arithmetic processing unit includes an instruction decoder which decodes a fetch instruction to issue an execution instruction; a reservation station which temporarily stores the execution instruction; and an arithmetic unit which executes the execution instruction, and the fetch instruction includes a multi-flow instruction which is divided into divided instructions and a single instruction. The instruction decoder includes: a pre-decoder including N number of slots each of which divides the multi-flow instruction into divided instructions; a main decoder including N number of slots each of which decodes the instructions to issue an execution instruction; and a pre-decoder buffer including N?K number of slots each of which temporarily stores instructions in the pre-decoder. The instruction decoder repeats transferring the divided instructions and the single instructions from the slots of the pre-decoder and the slots of the pre-decoder buffer to the main decoder as much as possible in order.

Abstract: Embodiments detailed herein relate to matrix operations. In particular, support for matrix (tile) addition, subtraction, and multiplication is described. For example, circuitry to support instructions for element-by-element matrix (tile) addition, subtraction, and multiplication are detailed. In some embodiments, for matrix (tile) addition, decode circuitry is to decode an instruction having fields for an opcode, a first source matrix operand identifier, a second source matrix operand identifier, and a destination matrix operand identifier; and execution circuitry is to execute the decoded instruction to, for each data element position of the identified first source matrix operand: add a first data value at that data element position to a second data value at a corresponding data element position of the identified second source matrix operand, and store a result of the addition into a corresponding data element position of the identified destination matrix operand.

Abstract: A processing device includes an instruction decode circuit including decoders that decode instructions respectively assigned an instruction number that is determined for every one of the decoders, an instruction execution circuit that executes the instructions decoded by the instruction decode circuit, an instruction complete holding circuit including hold blocks provided in correspondence with each of the decoders and respectively including hold regions assigned the instruction number, and used for an instruction complete process, and an instruction complete controller that stores instruction information that is generated by decoding the instructions by the decoders, in one of the hold regions of the hold block corresponding to the decoder that decodes the instruction, based on the instruction number, and obtain, in order, the instruction information corresponding to the instructions executed by the instruction execution circuit from the instruction complete holding circuit, to perform the instruction comple

Abstract: A mobile telecommunications system entity for a mobile telecommunications system has at least one entity, which serves at least one user equipment. The mobile telecommunications system entity has circuitry which is configured to transmit scheduling information for on-demand system information, which can be requested by the at least one user equipment.

Abstract: Accelerated synchronization operations using fine grain dependency check are disclosed. A graphics multiprocessor includes a plurality of execution units and synchronization circuitry that is configured to determine availability of at least one execution unit. The synchronization circuitry to perform a fine grain dependency check of availability of dependent data or operands in shared local memory or cache when at least one execution unit is available.

Abstract: Some example memory systems include a load and store unit (LSU) operable to load a memory reference. The LSU may include an alignment register, a current memory reference register, and a vector register. The memory system may include a memory coupled to the LSU. The memory may be operable to store a memory reference. The memory reference may be aligned or unaligned in the memory, and the LSU may be operable to efficiently load both unaligned and aligned memory references. Some example memory systems include a load and store unit (LSU) operable to store to the memory at a memory address. The LSU may be operable to efficiently store to both unaligned and aligned memory addresses. The LSU may perform loads and stores in forward and reverse stride.

Abstract: Implementations disclosed herein provide a method of receiving a command from a host, the command providing a starting logical block address (LBA) and a length of the command, generating a multiplicity bit mask (MBM) for the command in response to receiving a command from a host, and storing the MBM to an MBM table in a row corresponding to a stream that the command is part of.

Abstract: Examples of the present disclosure provide apparatuses and methods for direct data transfer. An example method comprises transferring data between a first device and a second device, wherein the first device is a bit vector operation device, and transforming the data using a data transform engine (DTE) by rearranging the data to enable the data to be stored on the first device when transferring the data between the second device and first memory device.

Abstract: Provided are a method for a terminal for requesting a system information block (SIB), and an apparatus for supporting the method in a wireless communication system. The method may comprise the steps of: receiving, from a radio access network (RAN), an SIB list comprising one or more SIBs supported by a cell; receiving, from the RAN, SIB broadcast information indicating whether the SIB supported by the cell is broadcast in a broadcast control channel (BCCH) section; detecting an omitted SIB on the basis of the SIB list and SIB broadcast information; and requesting the omitted SIB from the RAN.

Abstract: At least some instructions executed in a pipeline are each associated with corresponding trace information that characterizes execution of that instruction in the pipeline. A predetermined type of store instructions flow through a subset of contiguous stages of the pipeline. A signal is received to store a portion of the trace information. A stage before the subset of contiguous stages is stalled. A store instruction of the predetermined type is inserted into a stage at the beginning of the subset of contiguous stages to enable the store instruction to reach the memory access stage at which an operand of the store instruction including the portion of the trace information is sent out of the pipeline. The store instruction is filtered from a stage of the subset of contiguous stages that occurs earlier in the pipeline than a stage in which trace information is generated.

Abstract: Various communication systems may benefit from efficient communication of system information. For example, certain wireless communication systems may benefit from system information block enhancement for low complexity user equipment and/or user equipment in coverage enhancement mode. A method can include decoding a transport block size (TBS) index in a compact downlink control information. The method can also include monitoring for SIB based on the decoded TBS index. The method may optionally include monitoring for the SIB based on a predefined transmission pattern of physical downlink control channel for machine type communication. The method may also optionally include decoding of M-SI messages from a subframe according to a pattern indicated by an information element in M-SIB1.

Abstract: A technique includes determining whether one or more instructions in an instruction group require cracking. Whether the instructions that require cracking are associated with a decode-time instruction optimization (DTIO) sequence is also determined. In response to a first instruction, included in the one or more instructions, requiring cracking and the first instruction not being part of a DTIO sequence, the first instruction is cracked into internal operations (IOPs). In response to a second instruction, included in the one or more instructions, requiring cracking and the second instruction being part of a DTIO sequence, an IOP sequence (that includes at least one IOP that is associated with at least a cracked version of the second instruction and at least a third instruction that is included in the one or more instructions and at least one other IOP that is associated with the cracked version of the second instruction) is generated.

Abstract: A technique includes determining whether one or more instructions in an instruction group require cracking. Whether the instructions that require cracking are associated with a decode-time instruction optimization (DTIO) sequence is also determined. In response to a first instruction, included in the one or more instructions, requiring cracking and the first instruction not being part of a DTIO sequence, the first instruction is cracked into internal operations (IOPs). In response to a second instruction, included in the one or more instructions, requiring cracking and the second instruction being part of a DTIO sequence, an IOP sequence (that includes at least one IOP that is associated with at least a cracked version of the second instruction and at least a third instruction that is included in the one or more instructions and at least one other IOP that is associated with the cracked version of the second instruction) is generated.

Abstract: A parallel processing method, system, and/or computer program product for performing data parallel wide accesses on an unstructured text is provided. The parallel processing includes creating a pointer that points to a beginning of the unstructured text and loading into a vector register a string segment of the unstructured text based on the pointer. Then, access permissions of a first byte of the string segment are automatically tested. In turn, a determination is made as to whether the string segment includes an end indication, and a remaining portion of the unstructured text is validated by accessing and loading a last character identified by the end indication into the vector register when the string segment is determined to include the end indication.

Abstract: An apparatus and method for performing addition of signed packed data values using rotation and halving.

Abstract: A hardware/software co-design for an optimized dynamic out-of-order Very Long Instruction Word (VLIW) pipeline.

Abstract: An embodiment of the invention includes receiving packet header vectors where a header vector includes a number of packet header words. Match operations are performed on the packet header words. At least one packet header word is modified based on the match operations. At least one processor is used for each packet header word to perform the packet match operations and modify at least one packet header word. Instructions are received from an instruction word where a VLIW instruction word includes all of the instruction words. Each processor performs an operation in response to the instruction word.

Abstract: According to one general aspect, a load unit may include a load circuit configured to load at least one piece of data from a memory. The load unit may include an alignment circuit configured to align the data to generate an aligned data. The load unit may also include a mathematical operation execution circuit configured to generate a resultant of a predetermined mathematical operation with the at least one piece of data as an operand. Wherein the load unit is configured to, if an active instruction is associated with the predetermined mathematical operation, bypass the alignment circuit and input the piece of data directly to the mathematical operation execution circuit.

Abstract: A technique for processing instructions includes examining instructions in an instruction stream of a processor to determine properties of the instructions. The properties indicate whether the instructions may belong in an instruction sequence subject to decode-time instruction optimization (DTIO). Whether the properties of multiple ones of the instructions are compatible for inclusion within an instruction sequence of a same group is determined. The instructions with compatible ones of the properties are grouped into a first instruction group. The instructions of the first instruction group are decoded subsequent to formation of the first instruction group. Whether the first instruction group actually includes a DTIO sequence is verified based on the decoding. Based on the verifying, DTIO is performed on the instructions of the first instruction group or is not performed on the instructions of the first instruction group.

Abstract: A system for, and method of, reducing power consumed obtaining system information from a cell, the system information contained in at least a master information block, a scheduling information block and a system information block. In one embodiment, the system includes: (1) a broadcast control channel (BCCH) frame cache configured to buffer received BCCH frames bearing portions of the system information and (2) a system information verifier associated with the BCCH frame cache and configured to determine version consistency in the master information block and the scheduling information block by employing the check numbers associated therewith.

Abstract: A UAV has two rotors. First and second sensors sense a first and second type of input respectively. The second type of input is different than the first type, the first sensor providing a first sensor output and the second sensor providing a second sensor output. The first sensor output is input to a first computer and the second sensor output is input to a second computer. The first and second computer communicate in parallel to process the first and second sensor outputs to create a control signal having a predetermined number of variables therein, each variable having an exclusive position within the signal. The first computer outputs a first variable and the second computer outputs a second variable, each output being assigned an exclusive position within the control signal. At least one of the first and second computers outputting the control signal to the rotors.

Abstract: An embodiment of the invention includes receiving packet header vectors where a header vector includes a number of packet header words. Match operations are performed on the packet header words. At least one packet header word is modified based on the match operations. At least one processor is used for each packet header word to perform the packet match operations and modify at least one packet header word. Instructions are received from an instruction word where a VLIW instruction word includes all of the instruction words. Each processor performs an operation in response to the instruction word.

Abstract: Method and a system for managing distributing computing suitable for implementation in an automation system are provided, wherein in a first step, a set of program instructions is partitioned into a plurality of unit blocks, where each unit block comprises at least one program instruction and, in a second set, at least one complementary block corresponding to at least one unit block are identified from the remainder of the plurality of unit blocks, where the complementary blocks are identified based on a comparison between read-write access of global variables in the unit block and corresponding complementary blocks and, in another step, the plurality of unit blocks are executed on a set of multiple processors within the automation system such that at least one complementary block is executed in parallel with a corresponding unit block.

Abstract: A computer processor is disclosed. The computer processor may comprise a vector unit comprising a vector register file comprising at least one register to hold a varying number of elements. The computer processor may further comprise processing logic configured to operate on the varying number of elements in the vector register file using one or more instructions that separate a vector or combine two vectors. The computer processor may be implemented as a monolithic integrated circuit.

Abstract: There is a need to provide a microcomputer capable of eliminating an external terminal for endian selection. Flash memory includes a user boot area for storing a program executed in user boot mode and corresponding endian information and a user area for storing a program executed in user mode and corresponding endian information. A data transfer circuit reads endian information stored in the user boot area or the user area in accordance with operation mode and supplies the endian information to a CPU before reset release of the CPU. Accordingly, an external terminal for endian selection can be eliminated.

Abstract: A microprocessor includes a plurality of processing cores and an uncore random access memory (RAM) readable and writable by each of the plurality of processing cores. Each core of the plurality of processing cores comprises microcode run by the core that implements architectural instructions of an instruction set architecture of the microprocessor. The microcode is configured to both read and write the uncore RAM to accomplish inter-core communication between the plurality of processing cores.

Abstract: A non-volatile memory accelerator and a method for speeding up data access are provided. The non-volatile memory accelerator includes a data pre-fetching unit, a cache unit, and an access interface circuit. The data pre-fetching unit has a plurality of line buffers. One of the line buffers provides read data according to a read command, or the data pre-fetching unit reads at least one cache data as the read data according to the read command. The data pre-fetching unit further stores in at least one of the line buffers a plurality of pre-stored data with continuous addresses according to the read command. The cache unit stores the at least one cache data and the pre-stored data with the continuous addresses. The access interface circuit is configured to be an interface circuit of the non-volatile memory.

Abstract: Methods and apparatus are provided for optimizing a processor core. Common processor subcircuitry is used to perform calculations for various types of instructions, including branch and non-branch instructions. Increasing the commonality of calculations across different instruction types allows branch instructions to jump to byte aligned memory address even if supported instructions are multi-byte or word aligned.

Abstract: Embodiments relate to packed loading and storing of data. An aspect includes a system for packed loading and storing of distributed data. The system includes memory and a processing element configured to communicate with the memory. The processing element is configured to perform a method including fetching and decoding an instruction for execution by the processing element. A plurality of individually addressable data elements is gathered from non-contiguous locations in the memory which are narrower than a nominal width of register file elements in the processing element based on the instruction. The processing element packs and loads the data elements into register file elements of a register file entry based on the instruction, such that at least two of the data elements gathered from the non-contiguous locations in the memory are packed and loaded into a single register file element of the register file entry.

Abstract: Embodiments relate to packed loading and storing of data. An aspect includes a method for packed loading and storing of data distributed in a system that includes memory and a processing element. The method includes fetching and decoding an instruction for execution by the processing element. The processing element gathers a plurality of individually addressable data elements from non-contiguous locations in the memory which are narrower than a nominal width of register file elements in the processing element based on the instruction. The data elements are packed and loaded into register file elements of a register file entry by the processing element based on the instruction, such that at least two of the data elements gathered from the non-contiguous locations in the memory are packed and loaded into a single register file element of the register file entry.

Abstract: Embodiments of systems, apparatuses, and methods for performing in a computer processor vector packed horizontal add or subtract of packed data elements in response to a single vector packed horizontal add or subtract instruction that includes a destination vector register operand, a source vector register operand, and an opcode are describes.

Abstract: Methods, systems, and apparatus, including computer programs encoded on computer storage media, for pre-fetching content. One of the systems includes a pre-fetcher configured to perform operations including determining, for a virtual machine executing on a device and using a first virtual machine physical address associated with the virtual machine, a second virtual machine physical address for data to pre-fetch for the execution of the virtual machine on the device, determining, using the second virtual machine physical address and an address mapping that associates virtual machine physical addresses for the virtual machine with device physical addresses for the device, a device physical address for the data, and requesting the data from a memory using the device physical address.

Abstract: Embodiments relate to accessing data in a memory. A method for accessing data in a memory coupled to a processor is provided. The method receives a memory reference instruction for accessing data of a first size at an address in the memory. The method determines an alignment size of the address in the memory. The method accesses the data of the first size in one or more groups of data by accessing each group of data block concurrently. The groups of data have sizes that are multiples of the alignment size.

Abstract: Methods, systems, and devices are described for transmitting scheduling requests for uplink transmission resources following a handover. A user equipment (UE) may determine that a handover from a first base station to a second base station has occurred, and may implement one or more processes to enhance efficiency in communications following the handover. A UE, for example, may wait for successful acquisition and/or derivation of timing information from a base station before attempting to schedule uplink resources with the base station.

Abstract: The instruction code including an instruction code stored in the area where the encrypted instruction code is stored in a non-rewritable format is authenticated using a specific key which is specific to the core where the instruction code is executed or an authenticated key by a specific key to perform an encryption processing for the input and output data between the core and the outside.

Abstract: The disclosure describes novel methods and apparatuses for controlling a device's TCA circuit when the device exists in a JTAG daisy-chain arrangement with other devices. The methods and apparatuses allow the TCA test pattern set used during device manufacturing to be reused when the device is placed in a JTAG daisy-chain arrangement with other devices, such as in a customers system using the device. Additional embodiments are also provided and described in the disclosure.

Abstract: A data processing apparatus is provided comprising processing circuitry and an instruction decoder responsive to program instructions to control processing circuitry to perform the data processing. The instruction decoder is responsive to an address calculating instruction to perform an address calculating operation for calculating a partial address result from a non-fixed reference address and a partial offset value such that a full address specifying a memory location of an information entity is calculable from said partial address result using at least one supplementary program instruction. The partial offset value has a bit-width greater than or equal to said instruction size and is encoded within at least one partial offset field of said address calculating instruction. A corresponding data processing method, virtual machine and computer program product are also provided.

Abstract: The present application describes a method and apparatus for prefetching instructions based on predicted branch target addresses. Some embodiments of the method include providing a second cache line to a second cache when a target address for a branch instruction in a first cache line of a first cache is included in the second cache line of the first cache and when the second cache line is not resident in the second cache.

Abstract: Systems and methods for resource sharing of pipelined circuitry of an integrated circuit (IC) are provided. For example, in one embodiment, a method for sharing a functional unit of an integrated circuit (IC) includes receiving two or more threads configured to access the functional unit through two or more data entry points associated with corresponding data exit points configured to receive processed thread data. The method further includes arbitrating the processing of the two or more threads by the functional unit to obtain the processed thread data. To arbitrate, the exit points that cannot receive additional data are determined. Threads are only received from data entry points with corresponding data exit points that can receive additional data. The processed output data is provided to a corresponding exit point.

Abstract: A method for sharing information between a publisher and multiple subscribers is provided. The publisher uses a latch-free, single publisher, multiple subscriber shared queue to share information. Logical change records representing changes made to a database are enqueued in the shared queue as messages in a stream of messages, and subscribers read the logical change records. Subscribers may filter logical change records before sending to apply processes for processing. An identifying property of the source instance of a change encapsulated in a logical change record may be included with each message enqueued.

Abstract: Disclosed herein are systems, apparatuses, and methods performing in a computer processor of performing a rotate and XOR in response to a single XOR and rotate instruction, wherein the rotate and XOR instruction includes a first and second source operand, a destination operand, and an immediate value.