Abstract: An apparatus and method to transmit unaligned data over an interface bus while providing the appearance of aligned data transfers to the receiving processor. In a preferred embodiment, an alignment mechanism is provided in the bus interface of the receiving processor to align the data transfers transparent to the receiving processor. The alignment mechanism detects an unaligned transfer in the bus command queue and forms multiple commands of aligned data to send to the processor.

Abstract: Methods and apparatuses are presented for sleep optimization based on system information block SIB scheduling. A method for invoking sleep states within user equipment (UE) is presented. The method includes decoding a broadcast control channel with a cell, determining a System Information Block (SIB) schedule associated with the cell, determining a sleep time interval based upon the SIB schedule, and placing the UE in a sleep state using the sleep time intervals. An apparatus for invoking sleep states within UE is presented. The apparatus includes logic configured to decode a broadcast control channel with a cell, logic configured to determine a SIB schedule associated with the cell, logic configured to determine a sleep time interval based upon the SIB schedule, and logic configured to place the UE in a sleep state using the sleep time intervals.

Abstract: A method of preventing an electronic file containing a computer virus from infecting a computer system using the Symbian™ operating system, the method comprising the steps of scanning files using an anti-virus application, and if an infected file is identified, maintaining the file in an open non-sharing state, whereby other applications running on the computer system may not operate on an infected file.

Abstract: Execution of a single stand-alone instruction manipulates two n bit strings of data to pack data or align the data. Decoding of the single instruction identifies two registers of n bits each and a shift value, preferably as parameters of the instruction. A first and a second subset of data of less than n bits are selected, by logical shifting, from the two registers, respectively, based solely upon the shift value. Then, the subsets are concatenated, preferably by a logical OR, to obtain an output of n bits. The output may be aligned data or packed data, particularly useful for performing a single operation on multiple sets of the data through parallel processing with a SIMD processor.

Abstract: Disclosed is an apparatus and method used in an interface for scheduling the store-forwarding of back-to-back multi-channel packet fragments, comprising a first-in-first-out (FIFO) memory, a read pointer of the FIFO memory, the read pointer to increment by at least one of a unit access per read and a fraction of the unit access per read, and a write pointer of the FIFO memory, the write pointer to increment by at least one of a unit access per write and a fraction of the unit access per write.

Abstract: Methods, apparatus and computer program products for removal of elements from a linked list while other elements of the linked list are allowed to be accessed during the removal operation. In one embodiment, the method, apparatus and computer program product include identifying an add/remove area of a linked list and a static area of the linked list. Elements may only be added or removed from the linked list in the add/remove area or by a garbage collector that performs garbage collection only on elements in the static area of the linked list. The garbage collector identifies an element after the last element in the add/remove area and performs garbage collection beginning with that element and moving through the static area. In an alternative embodiment, a “next element” pointer in a previous list element is set to point to the element being deleted's “next element” pointer. Any global references to the element being deleted must be modified.

Abstract: A branch control apparatus in a microprocessor. The apparatus includes a branch target address cache (BTAC) that caches indications of whether a branch instruction wraps across two cache lines. When an instruction cache fetch address of a first cache line containing the first part of the branch instruction hits in the BTAC, the BTAC outputs a target address of the branch instruction and indicates the wrap condition. The target address is stored in a register. The next sequential fetch address selects a second cache line containing the second part of the branch instruction. After the two cache lines containing the branch instruction are fetched, the target address from the register is provided to the instruction cache in order to fetch a third cache line containing a target instruction of the branch. The three cache lines are stored in order in an instruction buffer for decoding.

Abstract: A programmable processor and method for improving the performance of processors by incorporating an execution unit operable to decode and execute single instructions in an instruction set comprising (a) group instructions that operate on a plurality of data elements in partitioned fields of a register to produce a catenated result, (b) aligned memory operations that move data between memory and register where the memory operand is aligned, and (c) unaligned memory operations where the memory operand is unaligned.

Abstract: A system and method for aligning an instruction stream is described. The system comprises a rotator logic unit for rotating data bytes of the instruction stream. A shifter logic unit is used for shifting the data bytes to the start of a instruction based upon a length of an immediately prior instruction.

Abstract: The present invention provides a data processing apparatus and method for performing aligned access operations. The data processing apparatus comprises a register data store having a plurality of registers operable to store data elements, and a processor operable to perform a data processing operation on one or more data elements accessed in at least one of the registers. Further, access logic is provided which is operable in response to an access instruction to perform an access operation in order to move a number of data elements between specified registers and a portion of a memory, the portion having a start address specified by the access instruction. Further, the access instruction has an alignment specifier associated therewith which is settable either to a first value or one of a plurality of second values.

Abstract: A branch control apparatus in a microprocessor. The apparatus includes a branch target address cache (BTAC) that caches indications of whether a branch instruction wraps across two cache lines. When an instruction cache fetch address of a first cache line containing the first part of the branch instruction hits in the BTAC, the BTAC outputs a target address of the branch instruction and indicates the wrap condition. The target address is stored in a register. The next sequential fetch address selects a second cache line containing the second part of the branch instruction. After the two cache lines containing the branch instruction are fetched, the target address from the register is provided to the instruction cache in order to fetch a third cache line containing a target instruction of the branch. The three cache lines are stored in order in an instruction buffer for decoding.

Abstract: A method for emulating a processor of a first endian type on a processor of a second endian type, wherein each memory access address B of string length L is transformed to the address A?B?L+S, wherein A is the total number of bytes allocated to a program, and S is the start address of the program.

Abstract: A method and associated apparatus is provided for operating an electronic device in accordance with a wired endian format. More specifically, the wired endian format requires multi-byte values be maintained in transmit order. The wired endian format is defined to allow for interfacing with both a big endian format and a little endian format. Thus, a device operating in accordance with the wired endian format is able to interface with both a device operating in accordance with the big endian format (e.g., a Serial Attached SCSI (SAS) device) and a device operating in accordance with the little endian format (e.g., a Serial ATA (SATA) device). Furthermore, since the device operating in accordance with wired endian format implements circuitry compliant with the wired endian format, duplication of circuitry to define separate data paths for interfacing with the big endian and little endian formats, respectively, is avoided.

Abstract: An instruction alignment unit for aligning instructions in a digital processor having a pipelined architecture includes an instruction queue, a current instruction buffer and a next instruction buffer in a pipeline stage n, an aligned instruction buffer in a pipeline stage n+1, instruction fetch logic for loading instructions into the current instruction buffer from an instruction cache or from the next instruction buffer and for loading instructions into the next instruction buffer from the instruction cache or from the instruction queue, and alignment control logic responsive to instruction length information contained in the instructions for controlling transfer of instructions from the current instruction buffer and the next instruction buffer to the aligned instruction buffer.

Abstract: Instructions asserted in a microprocessors instruction pipeline (3) are accompanied by control information, comprising a group of bits, asserted within a control information pipeline (5) that is synchronized to the instruction pipeline. At the execution stage, the control information is interpreted and appropriate action taken. The control information may indicate that the instruction has been reasserted (asserted again following an initial assertion) and may also indicate the number of times that the instruction has been consecutively asserted in the instruction pipeline. Applied to unaligned memory operations, in which a memory atom is asserted twice, the control information indicates which part of the unaligned data is to be fetched each time the atom is executed.

Abstract: Described herein is a technology facilitating the operation of non-native program modules within a native computing platform. This technology provides a mechanism for aligning—as necessary—parameters of data structures so that program modules or operating systems of different paradigms may use them. The data of parameters of data structures is aligned to match the native paradigm. Typically, such data structures are shared by non-native program modules and the native operating system (or other program modules). It is aligned so that data—that would otherwise be non-aligned and performance hindering—is quickly and easily accessible by the native platform. This abstract itself is not intended to limit the scope of this patent. The scope of the present invention is pointed out in the appending claims.

Abstract: A data processing system using a main processor 8 and a coprocessor 10 provides coprocessor load instructions (USALD) for loading a variable number of data values dependent upon alignment into the coprocessor 10 and also specifying data processing operations to be performed upon operands within those loaded data words to generate result data words. The specified coprocessor processing operations may be a sum of absolute differences calculation for a row of pixel byte values. The result of this may be accumulated within an accumulate register 22. A coprocessor memory 18 is provided within the coprocessor 10 to provide local storage of frequently used operand values for the coprocessor 10.

Abstract: In one embodiment, a digital signal processor includes look ahead logic to decrease the number of bubbles inserted in the processing pipeline. The processor receives data containing instructions in a plurality of buffers and decodes the size of a first instruction. The beginning of a second instruction is determined based on the size of the first instruction. The size of the second instruction is decoded and the processor determines whether loading the second instruction will deplete one of the plurality of buffers.

Abstract: There is provided a method for aligning and inserting data elements into a memory based upon an instruction sequence consisting of one or more alignment instructions and a single store instruction. Given a data item that includes a data element to be stored, the method includes the step of aligning the data element in another memory with respect to a predetermined position in the memory, in response to the one or more alignment instructions. A mask is dynamically generated to enable writing of memory bit lines that correspond to the aligned data element. The memory bit lines are written to the memory under a control of the mask. The generating and writing steps are performed in response to the single store instruction.

Abstract: A method and system for fixed-length memory-to-memory processing of fixed-length instructions. Further, the present invention is a method and system for implementing a memory operand width independent of the ALU width. The arithmetic and register data are 32 bits, but the memory operand is variable in size. The size of the memory operand is specified by the instruction. Instructions in accordance with the present invention allow for multiple memory operands in a single fixed-length instruction. The instruction set is small and simple, so the implementation is lower cost than traditional processors. More addressing modes are provided for, thus creating a more efficient code. Semaphores are implemented using a single bit. Shift-and-merge instructions are used to access data across word boundaries.

Abstract: A cache controller is disclosed. The cache controller includes potential replacement list, a plurality of valid bits and a number of counters. The potential replacement list includes a number of entries. Each of the valid bits corresponds to one of the entries. Each of the counters also corresponds to the one of the entries.

Abstract: A method and apparatus for trace data alignment for trace data generated during differing instruction pipeline stages selectively delays write data, memory access address and memory access control data zero, one or two pipeline stages dependent upon the memory access control data. Program counter data delayed by one clock cycle is delayed one pipeline stage if the next instruction is a new instruction. Program counter control data is also delayed one pipeline stage. The write data, memory access address, memory access control data, program counter data and program counter control data are further delayed a number of pipeline stages to align with read data. The program counter data holds if the pipeline is stalled. The write data, memory access address, memory access control data, program counter data and program counter control data holds in the multistage pipeline delay register if the pipeline is stalled.

Abstract: A method and apparatus for providing a plurality of aligned instructions from an instruction stream provided by a memory unit for execution within a pipelined microprocessor is described. The microprocessor comprises a prefetch buffer, whereby the prefetch buffer stores prefetched instructions and additional information about the validity and size of the prefetch buffer. The method and apparatus use the prefetch buffer to buffer a part of an instruction stream. The actually aligned instruction stream is issued from the prefetch buffer or directly by instructions fetched from the memory, or from a combination of prefetched instructions and actually fetched instructions.

Abstract: An aspect of the present invention provides a method of processing unaligned data in a microprocessor including, storing a first part of the unaligned data in a first register, storing a second part of the unaligned data in a second register, calculating a shift amount applied to the unaligned data, concatenating the data stored in the first and second registers, shifting the concatenated data by the calculated shift amount, and storing the shifted result in one of the first and second registers.

Abstract: A processor that has a plurality of instruction slots each of which stores an instruction to be executed in parallel. One of the plurality of instruction slots is a first instruction slot and another a second instruction slot. A special instruction stored in the first instruction slot is executed by a first functional unit that executes instructions stored in the first instruction slot, and a second functional unit that executes instructions stored in the second instruction slot. An instruction stored in the second instruction slot is executed in parallel by a third functional unit that executes instructions stored in the second instruction slot.

Abstract: A system and method for extracting complex, variable length computer instructions from a stream of complex instructions each subdivided into a variable number of instructions bytes, and aligning instruction bytes of individual ones of the complex instructions. The system receives a portion of the stream of complex instructions and extracts a first set of instruction bytes starting with the first instruction bytes, using an extract shifter. The set of instruction bytes are then passed to an align latch where they are aligned and output to a next instruction detector. The next instruction detector determines the end of the first instruction based on said set of instruction bytes. An extract shifter is used to extract and provide the next set of instruction bytes to an align shifter which aligns and outputs the next instruction. The process is then repeated for the remaining instruction bytes in the stream of complex instructions.

Abstract: A digital signal processor is designed to execute variable-sized instructions that may include up to N elementary instruction codes. The processor comprises a memory program comprising I individually addressable, parallel-connected memory banks in which the codes of a program are recorded in an interlaced fashion, and a circuit for reading the program memory arranged to read a code in each of the I memory banks during a cycle for reading an instruction. A cycle for reading an instruction in the program memory includes reading a sequence of codes that includes the instruction code or codes to be read and can also include codes, belonging to a following instruction, that are filtered before the instruction is applied to execution units. The program memory of the digital signal processor does not include any no-operation type codes.

Abstract: Trace data is aligned in a processor having an instruction pipeline by delaying write data and read data a predetermined number of clock cycles, selectively swapping both most significant write data and read data with least significant write data and read dependent upon memory access control data. The write and read data pass normally for even memory bank accesses and are swapped for odd memory bank accesses. Memory access control data, program counter data and program counter control data are similarly delayed. At least the read data and optionally all the data are held upon a pipeline stall.

Abstract: Data transactions are partitioned to transfer data across a communication connection requiring naturally aligned data transfers of quad-words. It is determining from byte enable signals whether the bytes of the data to be transferred start in the high order dword or end in the low order dword of a quad-word. The transaction is separated into two transactions if the bytes of the data to be transferred start in the high order dword or end in the low order dword of a quad word. A second transaction is created by pre-appending if the bytes of the data to be transferred start in the high order dword. A second transaction is created by post-appending if the bytes of the data to be transferred end in the low order dword of a quad word.

Abstract: A disclosed address generation system includes a decrementer and a multiplexer. The decrementer produces a decremented address signal by subtracting a first integer value from an incremented address signal. The multiplexer produces either the incremented address signal or the decremented address signal dependent upon a control signal. A described instruction fetch apparatus includes an instruction queuing and selection subsystem producing either an even portion or an odd portion of an instruction data block, specified by a first address signal, as a fetched instruction dependent upon one or more control signals generated based on determining bits of second and third address signals. A disclosed central processing unit (CPU) includes an instruction cache and a processor core, wherein the processor core includes an address generation subsystem generating the first, second, and third address signals, and the instruction queuing and selection subsystem. A method is described for fetching an instruction.

Abstract: An instruction alignment unit for aligning instructions in a digital processor having a pipelined architecture includes an instruction queue, a current instruction buffer and a next instruction buffer in a pipeline stage n, an aligned instruction buffer in a pipeline stage n+1, instruction fetch logic for loading instructions into the current instruction buffer from an instruction cache or from the next instruction buffer and for loading instructions into the next instruction buffer from the instruction cache or from the instruction queue, and alignment control logic responsive to instruction length information contained in the instructions for controlling transfer of instructions from the current instruction buffer and the next instruction buffer to the aligned instruction buffer.

Abstract: A method is provided for translating a source operation to a target operation. The source operation acts on one or more source operands, each comprising a binary integer of a first bit-width. The target operation is required to be evaluated by a processor, such as a computer, which performs integer operations on binary integers of a second bit-width which is greater than first bit-width. The source operation is translated to a target operation having at least one target operand. The method identifies whether the value of unused bits of the or each target operand affects the value of the target operation and whether the target operand or any of the target operands is capable of having one or more unused bits of inappropriate value. If so, a correcting operation is added to the target operation for correcting the value of each of the bits of inappropriate value before performing the target operation.

Abstract: Controller component (155) of system (100) generates address pattern (902) through employment of one or more parameters (205), to store information (810) at a plurality of parts of storage, for example, one or more instances of banked data memory (140) that are employable with multiprocessing. The one or more parameters (205) are related to the information (810).

Abstract: Instructions asserted in a microprocessors instruction pipeline (3) are accompanied by control information, comprising a group of bits, asserted within a control information pipeline (5) that is synchronized to the instruction pipeline. At the execution stage, the control information is interpreted and appropriate action taken. The control information may indicate that the instruction has been reasserted (asserted again following an initial assertion) and may also indicate the number of times that the instruction has been consecutively asserted in the instruction pipeline. Applied to unaligned memory operations, in which a memory atom is asserted twice, the control information indicates which part of the unaligned data is to be fetched each time the atom is executed.

Abstract: Within a system supporting execution of variable length instructions a program is stored within discrete memory regions with a variable length instruction spanning a gap between two such discrete memory regions. When execution is attempted of such a variable length instruction spanning a gap, an abort handler is initiated which serves to copy the end portion of one of the memory regions together with the start portion of the other memory region into a separate fix-up memory region where these may be concatenated such that the whole of the variable length instruction will appear in one place. Execution of that variable length instruction from out of the fix-up memory region can then be triggered.

Abstract: Techniques for adjusting the boundary between bytes of data in a serial-to-parallel converter are provided. Bits of serial data are shifted into a first register. Data bytes are then shifted out of the first register along parallel signal lines into a second register. The timing of the parallel load of data from the first register to the second register determines the parallel data byte boundary. The boundary between the parallel data bytes can be shifted using a load enable signal. The phase of the load enable signal can be changed to shift the boundary between data bytes by one or more bits. The parallel data can then be loaded from the second register into a third register. The data output signal of the third register is synchronized to a core clock signal to ensure enough set up and hold time for signals output by the third register.

Abstract: A processor includes execution resources for handling a first memory operation and a concurrent second memory operation. If one of the memory operations is misaligned, the processor may allocate the execution resources for the other memory operation to that memory operation. In one embodiment, the older memory operation proceeds if misalignment is detected. The younger memory operation is retried and may be reexecuted at a later time. If the older memory operation is misaligned, the execution resources provided for the younger operation may be allocated to the older memory operation. If only the younger memory operation is misaligned, the younger memory operation may be the older memory operation during a subsequent reexecution and may thus be allocated the execution resources to allow the memory operation to complete.

Abstract: Data transactions are partitioned to transfer data across a communication connection requiring naturally aligned data transfers of quad-words. It is determining from byte enable signals whether the bytes of the data to be transferred start in the high order dword or end in the low order dword of a quad-word. The transaction is separated into two transactions if the bytes of the data to be transferred start in the high order dword or end in the low order dword of a quad word. A second transaction is created by pre-appending if the bytes of the data to be transferred start in the high order dword. A second transaction is created by post-appending if the bytes of the data to be transferred end in the low order dword of a quad word.

Abstract: A data processing unit having superscalar structure able to execute a plurality of instructions in parallel includes a memory for storing the instructions having a plurality of n-bit input/output ports, an instruction fetch unit, a coupling unit for coupling said memory with the instruction fetch unit, and an instruction stream request control unit for addressing the mmory to provide an instruction stream at its output ports. The coupling unit includes a shifter having an input and an output and a control input, the input being coupled with the output ports of the memory, the output being coupled with the instruction fetch unit, and the control input being coupled with the instruction stream request control unit. The instruction fetch unit has a register for storing said instruction stream and a shifter to shift the content of the register.

Abstract: An apparatus and method for issue grouping of instructions in a VLIW processor is disclosed. There can be one, two, or three issue groups (but no greater than three issue groups) in each VLIW packet. In one embodiment, a template in the VLIW packet comprises two issue group end markers where each issue group end marker comprises three bits. The three bits in the first issue group end marker identifies the instruction which is the last instruction in the first issue group. Likewise, the three bits in the second issue group end marker identifies the instruction which is the last instruction in the second issue group. Any instructions in the VLIW packet falling outside the two expressly defined first and second issue groups are placed in a third issue group. As such, three issue groups can be identified by use of the two issue group end markers. In one embodiment, the template of the VLIW packet includes a chaining bit.

Abstract: A processing engine 10 includes an instruction buffer 502 operable to buffer single and compound instructions pending execution. A decode mechanism is configured to decode instructions from the instruction buffer. The decode mechanism is arranged to respond to a predetermined tag in a tag field of an instruction, which predetermined tag is representative of the instruction being a compound instruction formed from separate programmed memory instructions. The decode mechanism is operable in response to the predetermined tag to decode at least first data flow control for a first programmed instruction and second data flow control for a second programmed instruction. The use of compound instructions enables effective use of the bandwidth available within the processing engine. A soft dual memory instruction can be compiled from separate first and second programmed memory instructions.

Abstract: A smart card-based information processing system capable of compatibly operating under a standard requiring the complete processing of one command at a time, but which is also capable of queuing commands received from applications external to the smart card that it cannot immediately process. When the smart card receives a command that it can process immediately, it processes the command and returns an appropriate status response word. When the smart card receives a command that it cannot process immediately, it places the command in a command queue and returns a status response word indicating that it cannot immediately process the command, along with an index/identifier defining the memory location of the queued command in the command queue. If the smart card also has data or other information developed as a result of executing a previously queued command, it transmits an appropriate proactive command to the application, so that the application can send a command to request the information.

Abstract: The invention is directed to a method for fetching at least one word instruction in a word-based processor. The word instruction includes several types of a full-word instruction or a half-word instruction. The processor employs a data bus with a word length in bit. The method includes dividing the word length into a plurality of world units by 2n bits. The processor checks the memory request to obtain whether or not the word instruction to be fetched is in a sequential half-word aligned address. If it is, then the processor fetches the sequential multiple half-word instructions at the same time in full word length at a first fetch cycle. The half-word instructions are stored in the word units. Then, the half-word instructions are executed without directly fetching the half-word instructions from the memory in each the fetch cycles. A circuit is also provided to fetch the word instruction.

Abstract: Speculatively decoding instruction lengths in order to increase instruction throughput. Instructions are speculatively decoded within a pipelined microprocessor architecture such that up to four instruction lengths may be decoded within a maximum of two processor clock cycles.

Abstract: An asynchronous processor having pipelined instruction fetching and execution to implement concurrent execution of instructions by two or more execution units. A writeback unit is connected to execution units and memory units to control information updates and to handle precise exception. A pipelined completion mechanism can be implemented to improve the throughput.

Abstract: A processing or control system having arrangements for separately and simultaneously generating instruction addresses and data addresses having two bus systems for accessing instruction and data storage, and having a single address range for both instructions and data. The boundary between the instruction range and the data range can be varied and placed under the control of the processor according to the needs of the particular application being processed. Some or all of the blocks of storage can access either the instruction bus or the data bus system, and the selection is made under the control of a control register within the processor. Advantageously, applications which require a larger amount of instruction storage, this can be provided; for applications which require a larger amount of data storage, that can be provided also; both are limited only by the total amount of storage available.

Abstract: An instruction aligner and method evaluates a fixed length instruction cache line by breaking it into at least two components. These two components, in one embodiment, include half of the instruction cache line being designated as most significant bytes and the second half of the instruction cache line being designated as least significant bytes. A byte right rotator is responsible for feeding the next sixteen bytes of the instruction stream, while a byte right shifter shifts the unused bytes of the current sixteen bytes the aligner is working on. The byte rotator and byte shifter combine to provide aligned variable length instructions for decoding based on either a fetch PC value or current instruction length.

Abstract: A line predictor caches alignment information for instructions. In response to each fetch address, the line predictor provides information for the instruction beginning at the fetch address, as well as alignment information for up to one or more additional instructions subsequent to that instruction. The line predictor may include a memory having multiple entries, each entry storing up to a predefined maximum number of instruction pointers and a fetch address corresponding to the instruction identified by a first one of the instruction pointers. Since the line predictor provides alignment information from one entry per fetch, the line predictor may provide a flow control mechanism for the initial portion of the pipeline within a microprocessor. Each entry may store combinations of instructions which the hardware within the pipeline may handle without creating stalls resulting from the combinations.

Abstract: A data address prediction structure for a superscalar microprocessor is provided. The data address prediction structure predicts a data address that a group of instructions is going to access while that group of instructions is being fetched from the instruction cache. The data bytes associated with the predicted address are placed in a relatively small, fast buffer. The decode stages of instruction processing pipelines in the microprocessor access the buffer with addresses generated from the instructions, and if the associated data bytes are found in the buffer they are conveyed to the reservation station associated with the requesting decode stage. Therefore, the implicit memory read associated with an instruction is performed prior to the instruction arriving in a functional unit. The functional unit is occupied by the instruction for a fewer number of clock cycles, since it need not perform the implicit memory operation.

Abstract: An apparatus and method are provided for improving the speed at which a pipeline microprocessor accesses misaligned memory operands. The apparatus includes page boundary evaluation logic and address logic. The page boundary evaluation logic evaluates an address corresponding to the misaligned memory operand, and determines whether or not access to the misaligned memory operand is within a single memory page. The address logic is coupled to the page boundary evaluation logic. When access to the misaligned memory operand is within the single memory page, the address logic eliminates an access tickle instruction from an instruction sequence generated to access the misaligned memory operand.