Abstract: A superscalar microprocessor is provided that includes a predecode unit adapted for predecoding variable byte-length instructions. The predecode unit predecodes the instructions prior to their storage within an instruction cache. In one system, a predecode unit is configured to generate a plurality of predecode bits including a start bit, an end bit, and a functional bit for each instruction byte. The plurality of predecode bits associated with each instruction byte are collectively referred to as a predecode tag. An instruction alignment unit then uses the predecode tags to dispatch the variable byte-length instructions to a plurality of decode units within the superscalar microprocessor. The predecode unit is configured such that the meaning of the functional bit of a particular predecode tag is dependent upon the status of the end bit.

Abstract: A processor is configured to predecode instruction bytes prior to storing them in an instruction cache. The predecode information generated by the processor includes instruction boundary indications identifying which of the instruction bytes are boundaries of instructions and control transfer indications identifying which of the instructions are control transfer instructions. The combination of the control transfer indications and the instruction boundary indications allows the branch prediction mechanism to locate the branch instructions in a group of instruction bytes fetched from instruction cache by scanning the control transfer and instruction boundary indications. In one embodiment, the branch prediction mechanism attempts to predict up to two branch instructions per clock cycle. Accordingly, the branch prediction mechanism scans the control transfer and instruction boundary indications to locate the first two branch instructions within a group of instruction bytes fetched from the instruction cache.

Abstract: An instruction cache having a pattern detector for use in predicting the length of variable length instructions in a microprocessor. The instruction cache comprises an instruction length calculation unit and the pattern detector. The pattern detector is configured with a content addressable memory and update logic. The content addressable memory stores fetch addresses and instruction lengths calculated by the calculation unit. The content addressable memory compares particular fetch addresses that it receives with fetch addresses already stored and outputs corresponding predicted instruction length sequences. The content addressable memory may receive, compare, and store instruction lengths or instruction bytes in addition to, or in lieu of, fetch addresses. A neural network or other type of memory configuration may be used in place of the content addressable memory.

Abstract: The invention, in one embodiment, is a static instruction decoder including a plurality of instruction inputs, a circular instruction queue, and an instruction rotator. The circular instruction queue is capable of receiving instructions from the instruction inputs, statically decoding the received instructions, indicating how many of the decoded instructions may issue in a next clock cycle, and outputting the decoded instructions in the next clock cycle, the number of instructions output being the number indicated. The instruction rotator is indexed by the indication of the circular instruction queue and points to the first instruction to issue in the next clock cycle.

Abstract: A non-aligned double word fetch buffer is integrated into a digital signal processor to handle non-aligned double word (32 bit) fetches. When a misaligned double word fetch is detected, the buffer causes a two cycle non-interruptable instruction to be initiated. The first cycle is a 16-bit misaligned data fetch. The address pointer is incremented by 2 and stored in a temporary pointer register. The second cycle is a 32-bit double word fetch based on the temporary pointer with its least significant bit set to 0 (an aligned fetch). The low word from this fetch is used to satisfy the current misaligned double word fetch and the high word is stored in a temporary buffer register in case it proves useful in subsequent misaligned double fetch instructions. Finally, the temporary address pointer is incremented by 2 for possible use in subsequent misaligned fetches.

Abstract: There is disclosed a dynamic cache which is divided into sections, or chunks, for the storage of optimized code. The optimized code may contain pointers to code in other chunks. When a cache chunk is to be reused, then the pointers to other caches, as well as the pointers from other caches to code contained with the cache that is to be removed, are changed to point to either code contained in a victim chunk of the cache, or, alternatively, to point back to the translator. The system can dynamically change the number and size of the cache chunks and the number and size of the victim chunks, if any.

Abstract: A microprocessor implements an instruction tracing mechanism that saves the state of the microprocessor without special hardware. Prior to the execution of a traced instruction, a trace microcode routine is implemented that saves the state of the microprocessor to external memory. The state information saved by the trace microcode routine varies depending upon the amount of data needed by the end user. After the state of the processor has been saved, the trace instruction is executed. State information that changed during the execution of the trace instruction is saved to memory prior to a subsequent instruction. The trace instruction mechanism advantageously requires minimal special hardware and expedites the saving of the processor state information.

Abstract: A compact and small compensating-electric-power data processor is realized by dividing a plurality of calculations to be carried out by a complex instruction into a number of executing units to be processed, instead of executing the calculations in parallel as in the past. For this purpose there is provided a decoder having a detecting part for decoding an instruction and for detecting whether the instruction is an instruction for executing a plurality of calculations, a field rearranging part for rearranging a part of the fields of said instruction based on a predetermined number of calculations to be processed if it is judged by said detecting part that the instruction is an instruction for executing a plurality of calculations, and a calculation control part for performing control to execute the calculations in plural cycles in synchronism with the order of said rearranged fields.

Abstract: A microprocessor includes an instruction alignment unit for locating instructions and conveying the located instructions to a set of decode units. The instruction alignment unit includes dual instruction queues. The first instruction queue receives instruction blocks fetched from the instruction cache. The instruction alignment unit uses instruction identification information provided by the instruction cache to select instructions from the first instruction queue for conveyance to the second instruction queue. Additionally, the instruction alignment unit applies a predetermined selection criteria to the instructions within the second instruction queue in order to select instructions for dispatch to the decode units. Selection logic for the first instruction queue need not consider the type of instruction, etc., in selecting instructions for conveyance to the second instruction queue. Selection logic for the second instruction queue considers instruction type, etc.

Abstract: A microprocessor optimized to execute two instruction sets in a long instruction word (LIW) format. One instruction set may have variable length instructions. The microprocessor has an alignment unit configured to detect variable length instructions as they are fetched from an instruction cache, and then embed the variable length instructions within a long instruction word. The long instruction words are stored in a central window until they are executed by a number of functional units. A number of the microprocessor's functional units may be configured to execute instructions from both instruction sets. These dual instruction set-capable functional units may be used in conjunction with an MROM unit configured to translate a subset of instructions from one instruction set into less complex instructions in either instruction set. The central window may be configured to shift the order of the long instruction words before they are issued in order to minimize the amount of time the functional units are idle.

Abstract: A system and method for aligning data in stack memory in a data processing system where the stack memory provides temporary storage for storing parameters for a function call. The method first determines if any of the parameters in the function being call are of a selected type. If a parameter is of a selected type, code is generated for aligning the parameter on a stricter boundary than the default boundary for the stack memory. Code is then generated to align the remaining parameters in the function call on the default boundary in the stack memory. The aligned parameter in the stack provides a reference point which is used by the called function to align locally scoped variables in the stack. By aligning a parameter of a selected type on stricter boundary in the stack, for example, a double precision floating point aligned on an 8 byte boundary, the execution performance of the compiled program code is improved.

Abstract: A VLIW microprocessor capable of executing two or more instructions having data dependency in a single cycle. The microprocessor includes an instruction fetch and decode unit, a register file, and a plurality of execution units communicating with the instruction fetch and decode unit and with the register file. At least two of the execution units are connected such that the output of a first one of the two execution units is connected to the input of a second one of the two execution units, such that the output of the first execution unit is available as an input to the second execution unit during said single cycle, and such that both execution units can execute in said single cycle. In an exemplary embodiment, the first execution unit is a shift left unit, and the second execution unit is a shift right unit. With this embodiment, a complete extract operation can be performed in a single cycle.

Abstract: A high performance digital signal processor includes a memory for storing instructions and operands for digital signal computations and a core processor connected to the memory. The memory may include first, second and third memory banks connected to the core processor by first, second and third data and address buses, respectively. The core processor includes a program sequencer and may include first and second computation blocks for performing first and second subsets, respectively, of the digital signal computations. A data alignment buffer is provided between the memory banks and the computation blocks. The data alignment buffer permits unaligned accesses to specified operands that are stored in different memory rows. The specified operands are supplied to one or both of the computation blocks in the same processor cycle.

Abstract: An arrangement for providing command responses in a sequence that is independent of the sequence that commands are initiated by an initiating bus to a target bus. A first memory array stores commands from the initiating bus in a first sequence, and provides the commands to the target bus in a first sequence. Multiple delayed completion registers are provided, each to receive and store one of the commands entered into the first memory array. The delayed completion registers re-enter its corresponding stored command into the first memory array when a request is received to reissue the command. A second memory array stores command responses in a second sequence that relates to the order that their corresponding commands were successfully completed on the target bus.

Abstract: A predecode unit is configured to predecode variable byte-length instructions prior to their storage within an instruction cache of a superscalar microprocessor. The predecode unit generates three predecode bits associated with each byte of instruction code: a "start" bit, an "end" bit, and a "functional" bit. The start bit is set if the associated byte is the first byte of the instruction. Similarly, the end bit is set if the byte is the last byte of the instruction. The functional bits convey information regarding the location of an opcode byte for a particular instruction as well as an indication of whether the instruction can be decoded directly by the decode logic of the processor or whether the instruction is executed by invoking a microcode procedure controlled by an MROM unit. For fast path instructions, the functional bit is set for each prefix byte included in the instruction, and cleared for other bytes.

Abstract: A processor architecture is disclosed including a fetcher, packet unit and branch target buffer. The branch target buffer is provided with a tag RAM that is organized in a set associative fashion. In response to receiving a search address, multiple sets in the tag RAM are simultaneously searched for a branch instruction that is predicted to be taken. The packet unit has a queue into which fetched cache blocks are stored containing instructions. Sequentially fetched cache blocks are stored in adjacent locations of the queue. The queue entries also have indicators that indicate whether or not a starting or final data word of an instruction sequence is contained in the queue entry and if so, an offset indicating the particular starting or final data word. In response, the packet unit concatenates data words of an instruction sequence into contiguous blocks. The fetcher generates a fetch address for fetching a cache block from the instruction cache containing instructions to be executed.

Abstract: A method and apparatus for efficiently transferring a data block of bytes from a source to a destination in memory of a computer system. The method transfers bytes in multiple-byte words on word-aligned boundaries of memory as much as possible to reduce the number of fetches and writes and the number of memory cycles required to execute the transfer. For handling data block transfers of various sizes and locations, the method is implemented in a compiler that compiles different portions of code at run time into a block of code that is then immediately executed. The compiler employs a state machine stored in memory and having a plurality of states. Each state is associated with a portion of code for aligning a destination address or for transferring bytes in multiple-byte words on word-aligned boundaries. The states correspond to different starting source and destination addresses.

Abstract: Apparatus, methods and computer program products are disclosed that enable a compiler to generate efficient code to access stack registers on a register stack. The invention operates by transforming a three-operand instruction, within a compiler's intermediate representation, to one or more fewer-than-three-operand instructions. The invention also transforms the instruction's operand addressing from an access to a pseudo-named register to an access to a stack register through stack offset into a register stack. The invention also determines the register stack state at each instruction responsive to register stack permutations and maps the stack offset accordingly for each subsequent access to a stack register.

Abstract: An apparatus and method for loading aligned/misaligned data from a cache within a microprocessor is provided. The apparatus contains a first ALU for generating a partial offset, alignment check logic for quickly estimating the alignment of the data, a second ALU for generating a linear address, and alignment confirmation logic for confirming the alignment of the data. Quick estimation of data alignment allows the load of data to proceed before full alignment calculations are completed. A mandatory slip during data alignment checking is eliminated.

Abstract: An instruction alignment unit is provided which is capable of routing variable byte length instructions simultaneously to a plurality of decode units which form fixed issue positions within a superscalar microprocessor. The instruction alignment unit may be implemented with a relatively small number of cascaded levels of logic gates, thus accomodating very high frequencies of operation. In one embodiment, the superscalar microprocessor includes an instruction cache for storing a plurality of variable byte-length instructions and a predecode unit for generating predecode tags which identify the location of the start byte of each variable byte-length instruction. An instruction alignment unit is configured to channel a plurality of the variable byte-length instructions simultaneously to predetermined issue positions depending upon the locations of their corresponding start bytes in a cache line.

Abstract: A method of reducing microprocessor peak power by scheduling execution of instructions to multiple execution units. In the prior art, parallel processing of instructions by high-power execution units caused the microprocessor peak power to increase. The method of the present invention attempts to reduce microprocessor peak power by ensuring that two high-power execution units are not executing simultaneously. While a first instruction is being executed by a first execution unit, a first signal is asserted. A second instruction is prevented from being dispatched to a second execution unit while the first signal is asserted. Thus, the second execution unit remains in an idle state while the first execution unit is executing the first instruction.

Abstract: A superscalar microprocessor having an instruction alignment unit, an instruction cache, a plurality of decode units and a predecode unit is provided. The instruction alignment unit transfers a fixed number of instructions from the instruction cache to each of the plurality of decode units. The instructions are selected from a quantity of bytes according to a predecode tag generated by the predecode unit. The predecode tag includes start-byte bits that indicate which bytes within the quantity of bytes are the first byte of an instruction. The instruction alignment unit independently scans a plurality of groups of instruction bytes, selecting start bytes and a plurality of contiguous bytes for each of a plurality of issue positions. Initially, the instruction alignment unit selects a group of issue positions for each of the plurality of groups of instructions.

Abstract: A conventional bi-endian computer system is enhanced to include mixed-endian mechanisms that allows the computer system to dynamically change its endian mode. The mixed-endian computer system can change endian mode on a task by task basis if necessary. The mixed-endian mechanisms automatically format the data in the form expected by the running task, regardless of whether the task expects the data to be in big endian format or in little endian format. The mixed-endian mechanisms also format big and little endian instructions such that they can execute on the same computer system.

Abstract: An instruction scanning unit for a superscalar microprocessor is disclosed. The instruction scanning unit processes start, end, and functional byte information (or predecode data) associated with a plurality of contiguous instruction bytes. The processing of start byte information and end byte information is performed independently and in parallel, and the instruction scanning unit produces a plurality of scan values which identify valid instructions within the plurality of contiguous instruction bytes. Additionally, the instruction scanning unit is scaleable. Multiple instruction scanning units may be operated in parallel to process a larger plurality of contiguous instruction bytes. Furthermore, the instruction scanning unit detects error conditions in the predecode data in parallel with scanning to locate instructions. Moreover, in parallel with the error checking and scanning to locate instructions, MROM instructions are located for dispatch to an MROM unit.

Abstract: A process is provided for determining the beginning and ending of each instruction of a variable length instruction. Data lines are stored in a first memory area which illustratively is an instruction cache. Each data line comprises a sequence of data words that are stored at sequential address in a main memory. The data lines contain multiple encoded variable length instructions that are contiguously stored in the main memory. Multiple indicators are stored in a second memory area, including one indicator associated with each data word of the data lines stored in the first memory area. Each indicator indicates whether or not its associated data word is the initial data word of a variable length instruction. A sequence of data words may be fetched from the cache. The fetched sequence of data words includes a starting data word and at least the number of data words in the longest permissible instruction. Plural indicators (i.e.

Abstract: An instruction execution pipeline in a computer system having variable-length instructions uses branch prediction to perform self-timed marking of instructions prior to decoding. Branch handling logic is provided in an instruction marking circuit to directly mark a target instruction of a predicted branch as the next instruction to be decoded. Additionally, a branch target FIFO may be used to store information about the location of the target instruction in the instruction stream.

Abstract: Apparatus and a method for providing a single instruction that can load a character from memory and perform a character compare. In an illustrative embodiment, this is accomplished by providing indexing apparatus which permits indexing on character boundaries. The characters are loaded from memory, and provided to an ALU unit in a processor, wherein a compare is made with a desired value. The ALU provides a compare result to a jump skip logic block, which notifies the processor whether the instruction immediately following the instruction of the present invention should be skipped or executed.

Abstract: A wide data width processor has an execution unit including an aligner that aligns data for load/store instructions and shifts or rotates data for arithmetic logic instructions. Use of the same circuitry and execution unit for these different types of instructions reduces overall circuit size because alignment circuitry need not be repeated, once in a load/store unit and once in an arithmetic logic unit.