Decoding By Plural Parallel Decoders Patents (Class 712/212)
  • Patent number: 11099847
    Abstract: A processor includes an execution unit and a processing logic operatively coupled to the execution unit, the processing logic to: enter a first execution state and transition to a second execution state responsive to executing a control transfer instruction. Responsive to executing a target instruction of the control transfer instruction, the processing logic further transitions to the first execution state responsive to the target instruction being a control transfer termination instruction of a mode identical to a mode of the processing logic following the execution of the control transfer instruction; and raises an execution exception responsive to the target instruction being a control transfer termination instruction of a mode different than the mode of the processing logic following the execution of the control transfer instruction.
    Type: Grant
    Filed: January 13, 2020
    Date of Patent: August 24, 2021
    Assignee: Intel Corporation
    Inventors: Vedvyas Shanbhogue, Jason W. Brandt, Ravi L. Sahita, Xiaoning Li
  • Patent number: 10825423
    Abstract: A display controller 12 comprises a first display processing core 20 comprising a first input stage 21 operable to read at least one input surface, a first processing stage operable to process one or more input surfaces to generate an output surface, and a first output stage 26 operable to provide an output surface for display to a first display 6, and a second display processing core 40 comprising a second input stage 41 operable to read at least one input surface, a second processing stage operable to process one or more input surfaces to generate an output surface, and a second output stage 46 operable to provide an output surface for display to a second display 8. The display controller 12 also comprises an internal data path 30 for passing pixel data of an output surface from the second display core 40 to the first display core 20.
    Type: Grant
    Filed: October 29, 2019
    Date of Patent: November 3, 2020
    Assignee: Arm Limited
    Inventors: Daren Croxford, Damian Piotr Modrzyk, Piotr Tadeusz Chrobak
  • Patent number: 10824927
    Abstract: A computer-implemented method, data processing system and computer readable medium manages processing of data entries in a data buffer. Data entries are stored in a data buffer. A representation of a two-directional matrix is annotated to mark the data arrivals as a plurality of entries. In addition, the two-directional matrix is annotated to define a valid processing period for the data entries. The data entries in the data buffer are processed by removing the data entries from the data buffer, marked for processing in the two-dimensional matrix during the valid processing period, by annotating the matrix, labeled as ACS, to define the number of available entries as a cumulative sum along the columns, A-X, such that ACS=cumsum(A-X), where ‘cumsum’ is the cumulative column-sum. Finally, the data entries from the data buffer are processed to determine the entries removed from the data buffer as defined by the row-sum of X.
    Type: Grant
    Filed: September 21, 2019
    Date of Patent: November 3, 2020
    Assignee: Enernet Global, LLC
    Inventors: Stephen Schneider, Brian Gardner
  • Patent number: 10776117
    Abstract: A method and circuit arrangement for selectively predicating an instruction in an instruction stream based upon a value corresponding to a predication register address indicated by a portion of an operand associated with the instruction. A first compare instruction in an instruction stream stores a compare result in at a register address of a predication register. The register address of the predication register is stored in a portion of an operand associated with a second instruction, and during decoding the second instruction, the predication register is accessed to determine a value stored at the register address of the predication register, and the second instruction is selectively predicated based on the value stored at the register address of the predication register.
    Type: Grant
    Filed: July 5, 2016
    Date of Patent: September 15, 2020
    Assignee: International Business Machines Corporation
    Inventors: Adam J. Muff, Paul E. Schardt, Robert A. Shearer, Matthew R. Tubbs
  • Patent number: 10747537
    Abstract: A set machine instruction is provided that has associated therewith a result location to be used with a set operation. The set machine instruction is executed, which includes checking contents of a selected field, and determining, based on the checking, whether the contents of the selected field indicate a first condition, a second condition or a third condition represented in one data type. The result location is set to a value based on the determining, wherein the value, based on the setting, is of a data type different from the one data type and represents a result of a previously executed instruction. The result of the previously executed instruction being one of the first condition, the second condition or the third condition.
    Type: Grant
    Filed: September 29, 2015
    Date of Patent: August 18, 2020
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Michael K. Gschwind, Brett Olsson
  • Patent number: 10698688
    Abstract: A set machine instruction is provided that has associated therewith a result location to be used with a set operation. The set machine instruction is executed, which includes checking contents of a selected field, and determining, based on the checking, whether the contents of the selected field indicate a first condition, a second condition or a third condition represented in one data type. The result location is set to a value based on the determining, wherein the value, based on the setting, is of a data type different from the one data type and represents a result of a previously executed instruction. The result of the previously executed instruction being one of the first condition, the second condition or the third condition.
    Type: Grant
    Filed: June 24, 2015
    Date of Patent: June 30, 2020
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Michael K. Gschwind, Brett Olsson
  • Patent number: 10628153
    Abstract: A method and system to provide user-level multithreading are disclosed. The method according to the present techniques comprises receiving programming instructions to execute one or more shared resource threads (shreds) via an instruction set architecture (ISA). One or more instruction pointers are configured via the ISA; and the one or more shreds are executed simultaneously with a microprocessor, wherein the microprocessor includes multiple instruction sequencers.
    Type: Grant
    Filed: April 2, 2018
    Date of Patent: April 21, 2020
    Assignee: Intel Corporation
    Inventors: Edward Grochowski, Hong Wang, John P. Shen, Perry H. Wang, Jamison D. Collins, James Held, Partha Kundu, Raya Leviathan, Tin-Fook Ngai
  • Patent number: 10613858
    Abstract: A method and system to provide user-level multithreading are disclosed. The method according to the present techniques comprises receiving programming instructions to execute one or more shared resource threads (shreds) via an instruction set architecture (ISA). One or more instruction pointers are configured via the ISA; and the one or more shreds are executed simultaneously with a microprocessor, wherein the microprocessor includes multiple instruction sequencers.
    Type: Grant
    Filed: April 2, 2018
    Date of Patent: April 7, 2020
    Assignee: Intel Corporation
    Inventors: Edward Grochowski, Hong Wang, John P. Shen, Perry H. Wang, Jamison D. Collins, James Held, Partha Kundu, Raya Leviathan, Tin-Fook Ngai
  • Patent number: 10585667
    Abstract: A method and system to provide user-level multithreading are disclosed. The method according to the present techniques comprises receiving programming instructions to execute one or more shared resource threads (shreds) via an instruction set architecture (ISA). One or more instruction pointers are configured via the ISA; and the one or more shreds are executed simultaneously with a microprocessor, wherein the microprocessor includes multiple instruction sequencers.
    Type: Grant
    Filed: February 20, 2018
    Date of Patent: March 10, 2020
    Assignee: Intel Corporation
    Inventors: Edward Grochowski, Hong Wang, John P. Shen, Perry H. Wang, Jamison D. Collins, James Held, Partha Kundu, Raya Leviathan, Tin-Fook Ngai
  • Patent number: 10503511
    Abstract: A processor is provided for use with a memory having selectable memory areas. In an example, the processor includes a memory area selection circuit (MMU) to select one of the selectable memory areas, and an instruction fetch circuit to fetch a target instruction at an address from the selected memory area. The processor includes an execution circuit (Pipeline) to execute instructions from the instruction fetch circuit and to execute a first instruction for changing the selection by the MMU to a second selectable memory area. The Pipeline executes a branch instruction that points to a target instruction, where access to the target instruction depends on actual change of selection to the second memory area. The processor also includes a logic circuit to ensure fetch of the target instruction in response to the branch instruction after actual change of selection. Other circuits, devices, systems, apparatus, and processes are also disclosed.
    Type: Grant
    Filed: May 31, 2016
    Date of Patent: December 10, 2019
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Hiroyuki Mizuno, Yoann Foucher
  • Patent number: 10489260
    Abstract: Apparatuses and methods for nested mode registers to extend mode register functionality are disclosed. An example apparatus comprises a mode register configured to store address information and write data, a plurality of nested mode registers coupled to the mode register and configured to store the write data, and a decoder circuit coupled to the mode register and the plurality of nested mode registers and configured to selectively enable a nested mode register of the plurality of nested mode registers to store the write data based, at least in part, on the address information.
    Type: Grant
    Filed: July 11, 2018
    Date of Patent: November 26, 2019
    Assignee: Micron Technology, Inc.
    Inventors: Kallol Mazumder, William O'Leary
  • Patent number: 10474463
    Abstract: An apparatus and method are described for down-converting from a source operand to a destination operand with masking. For example, a method according to one embodiment includes the following operations: reading a source operand value to be down-converted from a first value to a down-converted value and stored in a destination location; reading each mask register bit stored in a mask register, the mask register bit(s) indicating whether to perform a masking operation or a conversion operation on the source operand value; if the mask register bit(s) indicates that a masking operation is to be performed, then performing a specified masking operation and storing the results of the masking operation in the destination location; and if the mask register bit indicates that a masking operation is not to be performed, then down-converting the source operand value and storing the down-converted value in the specified destination location.
    Type: Grant
    Filed: December 23, 2011
    Date of Patent: November 12, 2019
    Assignee: INTEL CORPORATION
    Inventors: Elmoustapha Ould-Ahmed-Vall, Robert Valentine, Tal Uliel, Jesus Corbal, Zeev Sperber, Amit Gradstein
  • Patent number: 10255944
    Abstract: Systems and methods of reading data from a storage device are provided. A first codeword and a second codeword are read from a storage device, where the second codeword is positioned after the first codeword. The first and second codewords are decoded in parallel, and the decoding of the second codeword completes before the decoding of the first codeword completes. The decoded second codeword and a signal indicating whether the decoding of the second codeword is complete are transmitted to control circuitry before the decoding of the first codeword completes.
    Type: Grant
    Filed: June 12, 2013
    Date of Patent: April 9, 2019
    Assignee: Marvell World Trade Ltd.
    Inventors: Hongying Sheng, Panu Chaichanavong, Gregory Burd
  • Patent number: 10198369
    Abstract: A data processing system includes a memory that includes a first memory bank and a second memory bank. The data processing system also includes a conflict detector connected to the memory and adapted to receive memory access information. The conflict detector tracks memory access statistics of the first memory bank, and determines if the first memory bank contains frequent row conflicts. The conflict detector also remaps a frequent row conflict in the first memory bank to the second memory bank. An indirection table is connected to the conflict detector and adapted to receive a memory access request, and redirects an address into a dynamically selected physical memory address in response to a remapping of the frequent row conflict to the second memory bank.
    Type: Grant
    Filed: March 24, 2017
    Date of Patent: February 5, 2019
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Yasuko Eckert, Reena Panda, Nuwan Jayasena
  • Patent number: 10175988
    Abstract: A method including fetching a group of instructions, where the group of instructions is configured to execute atomically by a processor, is provided. The method further includes scheduling at least one of the group of instructions for execution by the processor before decoding the at least one of the group of instructions based at least on pre-computed ready state information associated with the at least one of the group of instructions.
    Type: Grant
    Filed: June 26, 2015
    Date of Patent: January 8, 2019
    Assignee: Microsoft Technology Licensing, LLC
    Inventors: Jan Gray, Doug Burger, Aaron Smith
  • Patent number: 10043587
    Abstract: Apparatuses and methods for nested mode registers to extend mode register functionality are disclosed. An example apparatus comprises a mode register configured to store address information and write data, a plurality of nested mode registers coupled to the mode register and configured to store the write data, and a decoder circuit coupled to the mode register and the plurality of nested mode registers and configured to selectively enable a nested mode register of the plurality of nested mode registers to store the write data based, at least in part, on the address information.
    Type: Grant
    Filed: July 20, 2016
    Date of Patent: August 7, 2018
    Assignee: Micron Technology, Inc.
    Inventors: Kallol Mazumder, William O'Leary
  • Patent number: 9710277
    Abstract: A processor and method are disclosed. In one embodiment the processor includes a prefetch buffer that stores macro instructions. The processor also includes a clock circuit that can provide a clock signal for at least some of the functional units within the processor. The processor additionally includes macro instruction decode logic that can determine a class of each macro instruction. The processor also includes a clock management unit that can cause the clock signal to remain in a steady state entering at least one of the units in the processor that do not operate on a current macro instruction being decoded. Finally, the processor also includes at least one instruction decoder unit that can decode the first macro instruction into one or more opcodes.
    Type: Grant
    Filed: September 24, 2010
    Date of Patent: July 18, 2017
    Assignee: Intel Corporation
    Inventors: Venkateswara R. Madduri, Jonathan Y. Tong, Hoichi Cheong
  • Patent number: 9384003
    Abstract: An electronic processor is provided for use with a memory (2530) having selectable memory areas. The processor includes a memory area selection circuit (MMU) operable to select one of the selectable memory areas at a time, and an instruction fetch circuit (2520, 2550) operable to fetch a target instruction at an address from the selected one of the selectable memory areas.
    Type: Grant
    Filed: September 24, 2008
    Date of Patent: July 5, 2016
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Hiroyuki Mizuno, Yoann Foucher
  • Patent number: 9372696
    Abstract: A microprocessor includes a plurality of memories each configured to hold microcode instructions. At least a first of the plurality of memories is configured to provide M-bit wide words of compressed microcode instructions, and at least a second of the plurality of memories is configured to provide N-bit wide words of uncompressed microcode instructions. M and N are integers greater than zero and N is greater than M. The microprocessor also includes a decompression unit configured to decompress the compressed microcode instructions after being fetched from the at least a first of the plurality of memories and before being executed.
    Type: Grant
    Filed: November 25, 2013
    Date of Patent: June 21, 2016
    Assignee: VIA TECHNOLOGIES, INC.
    Inventors: G. Glenn Henry, Terry Parks, Brent Bean
  • Patent number: 9367349
    Abstract: A multi-core system includes multiple processor cores; a bus connected to the processor cores; multiple peripheral devices accessed by the processor cores via the bus; profile information including information concerning access of the peripheral devices by each task assigned to the processor cores; a monitor that based on the profile information, monitors access requests to the peripheral devices from tasks under execution at the processor cores and prohibits an access request that causes contention at the bus; and a scheduler that when the monitor prohibits an access request that causes contention at the bus, switches to a different task.
    Type: Grant
    Filed: December 21, 2012
    Date of Patent: June 14, 2016
    Assignee: FUJITSU LIMITED
    Inventors: Koji Kurihara, Koichiro Yamashita, Hiromasa Yamauchi, Takahisa Suzuki
  • Patent number: 9354876
    Abstract: A processor includes a processor core. The processor core includes a first execution unit and a second execution unit. The first execution unit is configured to 1) execute a complex instruction that requires multiple instruction cycles to execute; 2) generate a wait signal that when asserted suspends execution of instructions by the second execution unit for at least a portion of the execution of the complex instruction; and 3) maintain information defining parameters of the wait signal generation across interruption of the complex instruction by execution of a different instruction in the first execution unit.
    Type: Grant
    Filed: June 14, 2013
    Date of Patent: May 31, 2016
    Assignee: TEXAS INSTRUMENTS DEUTSCHLAND GMBH
    Inventors: Horst Diewald, Johann Zipperer
  • Patent number: 9304775
    Abstract: An embodiment of a computing system is configured to process data using a multithreaded SIMD architecture that includes heterogeneous processing engines to execute a program. The program is constructed of various program instructions. A first type of the program instructions can only be executed by a first type of processing engine and a second type of program instructions can only be executed by a second type of processing engine. A third type of program instructions can be executed by the first and the second type of processing engines. An instruction dispatcher is configured to identify and remove program instruction execution conflicts for the heterogeneous processing engines to improve instruction execution throughput.
    Type: Grant
    Filed: November 5, 2007
    Date of Patent: April 5, 2016
    Assignee: NVIDIA Corporation
    Inventors: John Erik Lindholm, Jered Wierzbicki
  • Patent number: 9129667
    Abstract: A semiconductor device in which a nonvolatile memory can normally operate and power saving can be performed with a P-state function, and a driving method of the semiconductor device are provided. The semiconductor device includes: a first circuit configured to control a state including a driving voltage and a clock frequency of a processor core; a first memory circuit and a second memory circuit which store state data; a second circuit generating a power supply voltage and a third circuit generating a clock which are electrically connected to the first circuit; and the processor core electrically connected to the second circuit and the third circuit through a switch. The processor cores includes: a volatile memory; and a nonvolatile memory transmitting and receiving data to/from the first memory.
    Type: Grant
    Filed: May 22, 2013
    Date of Patent: September 8, 2015
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Yasuyuki Takahashi, Seiichi Yoneda
  • Patent number: 9063532
    Abstract: State machine engines are disclosed, including those having an instruction insertion register. One such instruction insertion register may provide an initialization instruction, such as to prepare a state machine engine for data analysis. An instruction insertion register may also provide an instruction in an attempt to resolve an error that occurs during operation of a state machine engine. An instruction insertion register may also be used to debug a state machine engine, such as after the state machine experiences a fatal error.
    Type: Grant
    Filed: August 31, 2012
    Date of Patent: June 23, 2015
    Assignee: Micron Technology, Inc.
    Inventor: David R. Brown
  • Patent number: 8990767
    Abstract: A method, system, and article of manufacture for solving ordinary differential equations described in a graphical model with nodes as blocks and dependencies as links using the processing of a computer with a plurality of processors. The method includes: generating segments of block with or without duplication for each block with an internal state and for each block without any output by traversing the graphical model from each block with an internal state to each block without any output; merging the segment to reduce duplication; compiling and converting each segment from the merged results in an executable code; and individually allocating the executable code for each segment to a plurality of processors for parallel execution.
    Type: Grant
    Filed: February 7, 2013
    Date of Patent: March 24, 2015
    Assignee: International Business Machines Corporation
    Inventors: Kumiko Maeda, Shuichi Shimizu, Takeo Yoshizawa
  • Patent number: 8954941
    Abstract: Method of generating respective instruction compaction schemes for subsets of instructions to be processed by a programmable processor, comprising the steps of a) receiving at least one input code sample representative for software to be executed on the programmable processor, the input code comprising a plurality of instructions defining a first set of instructions (S1), b) initializing a set of removed instructions as empty (S3), c) determining the most compact representation of the first set of instructions (S4) d) comparing the size of said most compact representation with a threshold value (S5), e) carrying out steps e1 to e3 if the size is larger than said threshold value, e1) determining which instruction of the first set of instructions has a highest coding cost (S6), e2) removing said instruction having the highest coding cost from the first set of instructions and (S7), e3) adding said instruction to the set of removed instructions (S8), f) repeating steps b-f, wherein the first set of instructions
    Type: Grant
    Filed: September 3, 2010
    Date of Patent: February 10, 2015
    Assignee: Intel Corporation
    Inventors: Hendrik Tjeerd Joannes Zwartenkot, Alexander Augusteijn, Yuanging Guo, Jürgen Von Oerthel, Jeroen Anton Johan Leijten, Erwan Yann Maurice Le Thenaff
  • Patent number: 8850410
    Abstract: A system and method for improving software maintainability, performance, and/or security by associating a unique marker to each software code-block; the system comprising of a plurality of processors, a plurality of code-blocks, and a marker associated with each code-block. The system may also include a special hardware register (code-block marker hardware register) in each processor for identifying the markers of the code-blocks executed by the processor, without changing any of the plurality of code-blocks.
    Type: Grant
    Filed: January 29, 2010
    Date of Patent: September 30, 2014
    Assignee: International Business Machines Corporation
    Inventors: Ramanjaneya S. Burugula, Joefon Jann, Pratap C. Pattnaik
  • Patent number: 8762620
    Abstract: A storage controller containing multiple processors. The processors are divided into groups, each of which handles a different stage of a pipelined process of performing host reads and writes. In one embodiment, the storage controller operates with a flash memory module, and includes multiple parallel pipelines that allow plural host commands to be handled simultaneously.
    Type: Grant
    Filed: April 8, 2008
    Date of Patent: June 24, 2014
    Assignee: Sandisk Enterprise IP LLC
    Inventors: Douglas A. Prins, Aaron K. Olbrich
  • Patent number: 8665458
    Abstract: Disclosed is an image forming apparatus which generates print data based on control data for page print inputted from an external device and which forms an image based on the print data. The image forming apparatus includes a control unit having a plurality of arithmetic processing units, and an image forming unit for forming an image based on the print data which is outputted by the control unit. The control unit generates the print data by carrying out a rasterizing process of one page in band unit constituted by a predetermined number of lines based on the control data for page print and sequentially outputs the generated print data at output timings defined in a constant output interval, wherein the rasterizing process is controlled based on whether or not generation of print data is to be completed within the output interval for all of bands in the one page.
    Type: Grant
    Filed: January 25, 2011
    Date of Patent: March 4, 2014
    Assignee: Konica Minolta Business Technologies, Inc.
    Inventors: Masahiro Ozawa, Fumihito Akiyama, Jun Kuroki, Takahisa Matsunaga, Hiroshi Nogawa, Yasufumi Aoyama, Kunikazu Satou, Yasutaka Shimohara
  • Publication number: 20140052964
    Abstract: An architecture for microprocessors and the like in which instructions include a type identifier, which selects one of several interpretation registers. The interpretation registers hold information for interpreting the opcode of each instruction, so that a stream of compressed instructions (with type identifiers) can be translated into a stream of expanded instructions. Preferably the type identifiers also distinguish sequencer instructions from processing-element instructions, and can even distinguish among different types of sequencer instructions (as well as among different types of processing-element instructions).
    Type: Application
    Filed: October 27, 2013
    Publication date: February 20, 2014
    Applicant: 3Dlabs Inc., Ltd.
    Inventors: Jonathan BLOOMFIELD, John ROBSON, Nick Murphy
  • Patent number: 8650386
    Abstract: A data processor includes a first register file including registers, a second register file including registers, a number of which is larger than that of the registers of the first register file, an instruction decoder and an operation unit. The instruction decoder decodes an instruction described in first and second instruction formats. The first instruction format includes a first register-addressing field for designating the first register file. The second instruction format includes a second register-addressing field for designating the second register file, a size of which is larger than that of the first register-addressing field. The operation unit executes an instruction described in the first and second instruction formats using operand data stored in the first and second register files, respectively, based on the instruction decoder, and executes operations in parallel, a number of which is determined by a certain field included in the second instruction format.
    Type: Grant
    Filed: April 12, 2013
    Date of Patent: February 11, 2014
    Assignee: Panasonic Corporation
    Inventors: Takeshi Kishida, Masaitsu Nakajima
  • Patent number: 8638886
    Abstract: A parallel implementation of the Viterbi decoder becomes more efficient when it employs end-state information passing as disclosed herein. The improved efficiency enables the usage of less area and/or provides the capacity to handle higher data rates within a given heat budget. In at least some embodiments, a decoder chip employs multiple decoders that operate in parallel on a stream of overlapping data blocks, using add-compare-select operations, to obtain a sequence of state metrics representing a most likely path to each state. Each decoder passes information indicative of a selected end-state for a decoder operating on a preceding data block. Each decoder in turn receives, from a decoder operating on a subsequent data block, the information indicative of the selected end-state. The end-state information eliminates any need for post-data processing, thereby abbreviating the decoding process.
    Type: Grant
    Filed: September 24, 2009
    Date of Patent: January 28, 2014
    Assignee: Credo Semiconductor (Hong Kong) Limited
    Inventor: Runsheng He
  • Patent number: 8612727
    Abstract: An apparatus in a microprocessor that has an instruction set architecture in which instructions may include a length-modifying prefix used to select an address/operand size other than a default address/operand size, wherein the apparatus marks the start byte and the end byte of each instruction in a stream of instruction bytes. Decode logic decodes each instruction byte of a predetermined number of instruction bytes to determine whether the instruction byte specifies a length-modifying prefix and generates a start mark and an end mark for each of the instruction bytes based on an address/operand size. Operand/address size logic provides the default operand/address size to the decode logic to use to generate the start and end marks during a first clock cycle during which the decode logic decodes the predetermined number of instruction bytes.
    Type: Grant
    Filed: October 1, 2009
    Date of Patent: December 17, 2013
    Assignee: VIA Technologies, Inc.
    Inventors: Thomas C. McDonald, John L. Duncan
  • Patent number: 8543736
    Abstract: A data processing circuit is disclosed in the present invention. The data processing circuit includes a decoder and a number of N-stage circuits. The circuits receive input data from at least a memory and separate the input data into N stages. The circuit process and store the N input data simultaneously to decrease the time of data processing in the data processing circuit.
    Type: Grant
    Filed: September 8, 2010
    Date of Patent: September 24, 2013
    Assignee: Etron Technology, Inc.
    Inventors: Chien-Chou Chen, Ming-Sung Huang, Wen Min Lu
  • Publication number: 20130145126
    Abstract: A processor core supports execution of program instruction from both a first instruction set and a second instruction set. An architectural register file 18 containing architectural registers is shared by the two instruction sets. The two instruction sets employ logical register specifiers which for at least some values of those logical registers specifiers correspond to different architectural registers within the architectural register file 18. A first decoder 4 for the first instruction set and a second decoder 6 for the second instruction set serve to decode the logical register specifiers to a common register addressing format. This common register addressing format is used to supply register specifiers to renaming circuitry 10 for supporting register renaming in conjunction with a physical register file 16 and an architectural register file 18.
    Type: Application
    Filed: December 2, 2011
    Publication date: June 6, 2013
    Applicant: ARM LIMITED,
    Inventors: Glen Andrew Harris, James Nolan Hardage, Mark Carpenter Glass
  • Patent number: 8443172
    Abstract: An apparatus in a microprocessor that has an instruction set architecture in which instructions may include a length-modifying prefix used to select an address/operand size other than a default address/operand size, wherein the apparatus marks the start byte and the end byte of each instruction in a stream of instruction bytes. Decode logic decodes each instruction byte of a predetermined number of instruction bytes to determine whether the instruction byte specifies a length-modifying prefix and generates a start mark and an end mark for each of the instruction bytes based on an address/operand size. Operand/address size logic provides the default operand/address size to the decode logic to use to generate the start and end marks during a first clock cycle during which the decode logic decodes the predetermined number of instruction bytes.
    Type: Grant
    Filed: October 1, 2009
    Date of Patent: May 14, 2013
    Assignee: VIA Technologies, Inc.
    Inventors: Thomas C. McDonald, John L. Duncan
  • Patent number: 8415968
    Abstract: The present disclosure relates to methods and systems for data tag control for quantum dot cellular automata (QCA). An example method includes receiving data, associating a data tag with the data, communicating the data tag along a first wire-like element to a local tag decoder, reading instructions from the data tag using the local tag decoder, communicating the instructions to a processing element, communicating the data along a second wire-like element to the processing element, and processing the data with the processing element according to the instructions. A length of the first wire-like elements and a length of the second wire-like element are approximately the same such that communication of the instructions and the data to the processing element are synchronized.
    Type: Grant
    Filed: July 30, 2010
    Date of Patent: April 9, 2013
    Assignee: The Board of Regents of the University of Texas System
    Inventors: Earl E. Swartzlander, Jr., Inwook Kong
  • Patent number: 8302083
    Abstract: An architecture includes a controller. The controller is configured to receive a microprogram. The microprogram is configured for performing at least one of hierarchical or a sequence of polynomial computations. The architecture also includes an arithmetic logic unit (ALU) communicably coupled to the controller. The ALU is controlled by the controller. Additionally, the microprogram is compiled prior to execution by the controller, the microprogram is compiled into a plurality of binary tables, and the microprogram is programmed in a command language in which each command includes a first portion for indicating at least one of a command or data transferred to the ALU, and a second portion for including a control command to the controller. The architecture and implementation of the programmable controller may be for cryptographic applications, including those related to public key cryptography.
    Type: Grant
    Filed: January 23, 2009
    Date of Patent: October 30, 2012
    Assignee: LSI Corporation
    Inventors: Anatoli A. Bolotov, Mikhail I. Grinchuk, Lav Ivanovic, Alexei Galatenko
  • Patent number: 8275974
    Abstract: An advantageous system and method are provided for supporting and/or enabling the creation of dynamic reports and/or data presentation(s) in connection with a spreadsheet-based application or program. The system and method offer a full complement of spreadsheet-based formatting and calculation capabilities. In addition, the system and method may be used in conjunction with and/or incorporated as part of spreadsheet-based application(s) and/or program(s) found on stand-alone clients and/or networked clients. The system and method generally include an electronic spreadsheet having a plurality of cells that are arrayed in a defined number of columns and rows, a database in communication with the electronic spreadsheet, and an expansion formula that functions to control retrieval of data from the database and automatically varies/expands at least one of the defined number of columns and rows to accommodate the data retrieval.
    Type: Grant
    Filed: July 21, 2006
    Date of Patent: September 25, 2012
    Assignee: Outlooksoft Corporation
    Inventor: Perlie E. Voshell
  • Patent number: 8230410
    Abstract: An enhanced mechanism for parallel execution of computer programs utilizes a bidding model to allocate additional registers and execution units for stretches of code identified as opportunities for microparallelization. A microparallel processor architecture apparatus permits software (e.g. compiler) to implement short-term parallel execution of stretches of code identified as such before execution. In one embodiment, an additional paired unit, if available, is allocated for execution of an identified stretch of code. Each additional paired unit includes an execution unit and a half set of registers. This apparatus is available for compilers or assembler language coders to use and allows software to unlock parallel execution capabilities that are present in existing computer programs but heretofore were executed sequentially for lack of a suitable apparatus.
    Type: Grant
    Filed: October 26, 2009
    Date of Patent: July 24, 2012
    Assignee: International Business Machines Corporation
    Inventor: Larry W. Loen
  • Publication number: 20120079249
    Abstract: In an embodiment, a decode unit includes multiple decoders configured to decode different types of instructions. One or more of the decoders may be complex decoders, and the decode unit may disable the complex decoders if an instruction of the corresponding type is not being decoded. In an embodiment, the decode unit may disable the complex decoders by data-gating the instruction into the decoder. The decode unit may also include a control unit that is configured to detect instructions of the type decoded by the complex decoders, and to enable the complex decoders and redirect the fetching in response to the detection. The decode unit may also record an indication of the instruction (e.g. the program counter address (PC) of the instruction) to more rapidly detect the instruction and prevent a redirect in subsequent fetches.
    Type: Application
    Filed: September 28, 2010
    Publication date: March 29, 2012
    Inventors: Wei-Han Lien, Ian D. Kountanis, Shyam Sundar
  • Publication number: 20120030449
    Abstract: The present disclosure relates to methods and systems for data tag control for quantum dot cellular automata (QCA). An example method includes receiving data, associating a data tag with the data, communicating the data tag along a first wire-like element to a local tag decoder, reading instructions from the data tag using the local tag decoder, communicating the instructions to a processing element, communicating the data along a second wire-like element to the processing element, and processing the data with the processing element according to the instructions. A length of the first wire-like elements and a length of the second wire-like element are approximately the same such that communication of the instructions and the data to the processing element are synchronized.
    Type: Application
    Filed: July 30, 2010
    Publication date: February 2, 2012
    Inventors: Earl E. Swartzlander, JR., Inwook Kong
  • Publication number: 20120005458
    Abstract: In one embodiment, a rotator, a mask generator, and circuitry configured to mask the rotated operand output by the rotator with the output mask generated by the mask generator perform a shift operation. The rotator is configured to rotate the input operand by the shift count. The mask generator is configured to generate an output mask by decoding a most significant bit (MSB) field of the shift count to generate a first mask, decoding a least significant bit (LSB) field of the shift count to generate a second mask, logically ANDing the bits of the second mask with the corresponding bit of the first mask and logically ORing the result with an adjacent bit of the first mask that is selected responsive to the shift direction.
    Type: Application
    Filed: September 14, 2011
    Publication date: January 5, 2012
    Inventor: Honkai Tam
  • Patent number: 7958335
    Abstract: A method and a data processing apparatus operable to process instructions from a plurality of instruction sets, the plurality of instruction sets each sharing a sub-set of common instructions and each having a remaining set of instructions is disclosed. The data processing apparatus comprises: a plurality of decode units, each decode unit being operable to only decode the remaining set of instructions from a corresponding one of the plurality of instruction sets; and a common decode unit operable to decode a number of the sub-set of common instructions from each of the plurality of instruction sets. This enables the common instructions from each instruction set to be decoded by the common decode unit. Hence, the logic which would otherwise be duplicated in each of the individual decode units for each instruction set can be removed from those decode units and provided just once in the common decode unit.
    Type: Grant
    Filed: August 5, 2005
    Date of Patent: June 7, 2011
    Assignee: ARM Limited
    Inventors: Conrado Blasco Allue, Glen Andrew Harris, Stephen John Hill
  • Patent number: 7890735
    Abstract: A multi-threaded microprocessor (1105) for processing instructions in threads. The microprocessor (1105) includes first and second decode pipelines (1730.0, 1730.1), first and second execute pipelines (1740, 1750), and coupling circuitry (1916) operable in a first mode to couple first and second threads from the first and second decode pipelines (1730.0, 1730.1) to the first and second execute pipelines (1740, 1750) respectively, and the coupling circuitry (1916) operable in a second mode to couple the first thread to both the first and second execute pipelines (1740, 1750). Various processes of manufacture, articles of manufacture, processes and methods of operation, circuits, devices, and systems are disclosed.
    Type: Grant
    Filed: August 23, 2006
    Date of Patent: February 15, 2011
    Assignee: Texas Instruments Incorporated
    Inventor: Thang Tran
  • Patent number: 7818543
    Abstract: A mechanism for superscalar decode of variable length instructions. A length decode unit may obtain a plurality of instruction bytes based on a scan window of a predetermined size. The instruction bytes may be associated with a plurality of variable length instructions, which are scheduled to be executed by a processing unit. The length decode unit may, for each instruction byte, estimate the start of a next variable length instruction following a current variable length instruction, and store a first pointer. A pre-pick unit may, for each instruction byte, use the first pointer to estimate the start of a subsequent variable length instruction following the next variable length instruction within the scan window, and store a second pointer. A pick unit may use a start pointer and related first and second pointers to determine the actual start of the variable length instructions within the scan window, and generate instruction pointers.
    Type: Grant
    Filed: July 10, 2007
    Date of Patent: October 19, 2010
    Assignee: GlobalFoundries Inc.
    Inventors: Gene W. Shen, Sean Lie
  • Patent number: 7818542
    Abstract: A mechanism for superscalar decode of variable length instructions. The decode mechanism may be included within a processing unit, and may comprise a length decode unit. The length decode unit may obtain a plurality of instruction bytes. The instruction bytes may be associated with a plurality of variable length instructions, which are to be executed by the processing unit. The length decode unit may perform a length decode operation for each of the plurality of instruction bytes. For each instruction byte, the length decode unit may estimate the instruction length of a current variable length instruction associated with a current instruction byte. Furthermore, during the length decode operation, for each instruction byte, the length decode unit may estimate the start of a next variable length instruction based on the estimated instruction length of the current variable length instruction, and store a first pointer to the estimated start of the next variable length instruction.
    Type: Grant
    Filed: July 10, 2007
    Date of Patent: October 19, 2010
    Assignee: GLOBALFOUNDRIES Inc.
    Inventors: Gene W. Shen, Sean Lie
  • Patent number: 7805710
    Abstract: Subject program code is translated to target code in basic block units at run-time in a process wherein translation of basic blocks is interleaved with execution of those translations. A shared code cache mechanism is added to persistently store subject code translations, such that a translator may reuse translations that were generated and/or optimized by earlier translator instances.
    Type: Grant
    Filed: March 30, 2004
    Date of Patent: September 28, 2010
    Assignee: International Business Machines Corporation
    Inventor: Geraint North
  • Publication number: 20100241791
    Abstract: A controller includes an instruction table memory, a program counter, a first decoder, and a first executing unit. The instruction table memory stores an instruction code obtained by coding a sequence to access a nonvolatile semiconductor memory. A read address in the instruction table memory is set to the program counter. The first decoder decodes the instruction code read from the instruction table memory to output a first decode signal. The first executing unit executes access to the nonvolatile semiconductor memory on the basis of the first decode signal output from the first decoder.
    Type: Application
    Filed: September 4, 2009
    Publication date: September 23, 2010
    Inventors: Tarou Iwashiro, Takahide Nishiyama, Seiichi Tomita
  • Patent number: RE41751
    Abstract: A processor can decode short instructions with a word length equal to one unit field and long instructions with a word length equal to two unit fields. An opcode of each kind of instruction is arranged into the first unit field assigned to the instruction. The number of instructions to be executed by the processor in parallel is s. When the ratio of short to long instructions is s-1:1, the s-1 short instructions are assigned to the first unit field to the s-1tA unit field in the parallel execution code, and the long instruction is assigned to the sth unit field to the (s+k?1)th unit field in the same parallel execution code.
    Type: Grant
    Filed: November 24, 2003
    Date of Patent: September 21, 2010
    Assignee: Panasonic Corporation
    Inventors: Taketo Heishi, Tetsuya Tanaka, Nobuo Higaki, Shuichi Takayama, Kensuke Odani