Instruction Decoding (e.g., By Microinstruction, Start Address Generator, Hardwired) Patents (Class 712/208)
  • Patent number: 10409815
    Abstract: A system comprises generation of a parse tree comprising a plurality of query parse nodes, each of the plurality of query parse nodes corresponding to a respective one of a plurality of portions of a script definition, generation of a first intermediate representation tree comprising an intermediate representation node corresponding to a respective one of each of the plurality of query parse nodes, wherein an intermediate representation node represents a logical operation corresponding to the portion of the script definition of the query parse node which corresponds to the intermediate representation node, definition of links between each of the plurality of query parse nodes and its corresponding the intermediate representation node, determination of a second intermediate representation tree, the second intermediate representation tree resulting from an optimizer transformation executed on the first intermediate representation tree, generation of an intermediate representation node corresponding to a transfo
    Type: Grant
    Filed: June 14, 2017
    Date of Patent: September 10, 2019
    Assignee: SAP SE
    Inventors: Chanho Jeong, Jaeha Lee
  • Patent number: 10303525
    Abstract: Systems, methods, and apparatuses for data speculation execution (DSX) are described. In some embodiments, a hardware apparatus for performing DSX comprises a hardware decoder to decode an instruction, the instruction to include an opcode and an operand to store a portion of a fallback address, execution hardware to execute the decoded instruction to initiate a data speculative execution (DSX) region by activating DSX tracking hardware to track speculative memory accesses and detect ordering violations in the DSX region, and storing the fallback address.
    Type: Grant
    Filed: December 24, 2014
    Date of Patent: May 28, 2019
    Assignee: Intel Corporation
    Inventors: Elmoustapha Ould-Ahmed-Vall, Christopher J. Hughes, Robert Valentine, Milind B. Girkar, Hideki Ido, Youfeng Wu, Cheng Wang
  • Patent number: 10296489
    Abstract: A processor including a first vector register for storing a plurality of source data elements, a second vector register for storing a plurality of control elements, and a vector bit shuffle logic. Each of the control elements in the first vector register corresponds to a different source data element and includes a plurality of bit fields. Each of the bit fields is associated with a single corresponding bit position in a destination mask register and identifies a single bit from the corresponding source data element to be copied to the single corresponding bit position in the destination mask register. The vector bit shuffle logic is to read the bit fields from the second vector register and, for each bit field, to identify a single bit from a single corresponding source data element and copy it to a single corresponding bit position in the destination mask register.
    Type: Grant
    Filed: December 27, 2014
    Date of Patent: May 21, 2019
    Assignee: Intel Corporation
    Inventors: Elmoustapha Ould-Ahmed-Vall, Jesus Corbal San Adrian, Robert Valentine, Mark J. Charney, Guillem Sole, Roger Espasa
  • Patent number: 10235174
    Abstract: A conditional instruction end facility is provided that allows completion of an instruction to be delayed. In executing the machine instruction, an operand is obtained, and a determination is made as to whether the operand has a predetermined relationship with respect to a value. Based on determining that the operand does not have the predetermined relationship with respect to the value, the obtaining and the determining are repeated. Based on determining that the operand has the predetermined relationship with respect to the value, execution of the instruction is completed.
    Type: Grant
    Filed: January 30, 2017
    Date of Patent: March 19, 2019
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Dan F. Greiner, Christian Jacobi, Marcel Mitran, Donald W. Schmidt, Timothy J. Slegel
  • Patent number: 10201760
    Abstract: A system and method are described below for encoding interactive low-latency video using interframe coding. For example, one embodiment of a computer-implemented method for performing video compression comprises: logically subdividing each of a sequence of images into a plurality of tiles, each of the tiles having a defined position within each of the sequence of images, the defined position remaining the same between successive images; detecting motion within the sequence of images occurring at each of the positions of each of the tiles; and encoding each tile within each image of the sequence of images using a first compression format or a second compression format, wherein the frequency at which a particular tile is encoded according to the first compression format across the sequence of images is based on the detected amount of motion at the position of that tile across the sequence of images.
    Type: Grant
    Filed: January 23, 2009
    Date of Patent: February 12, 2019
    Assignee: Sony Interactive Entertainment America LLC
    Inventors: Roger van der Laan, Stephen G. Perlman
  • Patent number: 10191746
    Abstract: A method for accelerating code optimization a microprocessor. The method includes fetching an incoming microinstruction sequence using an instruction fetch component and transferring the fetched macroinstructions to a decoding component for decoding into microinstructions. Optimization processing is performed by reordering the microinstruction sequence into an optimized microinstruction sequence comprising a plurality of dependent code groups. The plurality of dependent code groups are then output to a plurality of engines of the microprocessor for execution in parallel. A copy of the optimized microinstruction sequence is stored into a sequence cache for subsequent use upon a subsequent hit optimized microinstruction sequence.
    Type: Grant
    Filed: November 22, 2011
    Date of Patent: January 29, 2019
    Assignee: INTEL CORPORATION
    Inventor: Mohammad Abdallah
  • Patent number: 10146543
    Abstract: A conversion system that converts a standard executable program according to a predetermined ISA into a custom executable program executable by a general purpose processor. The processor includes a PEU that is programmable to execute a UDI. The conversion system includes a PEU programming tool that converts a functional description of a processing operation to be performed by the PEU of the processor into programming information for the PEU to perform the processing operation in response to the UDI. A converter converts the standard executable program into the custom executable program and includes an optimization routine that replaces a portion of the standard executable program with the specified UDI and that inserts the UDI into the custom executable program, and that further inserts a UDI load instruction that specifies the UDI and a location of the programming information in the custom executable program.
    Type: Grant
    Filed: December 7, 2016
    Date of Patent: December 4, 2018
    Assignee: VIA ALLIANCE SEMICONDUCTOR CO., LTD.
    Inventors: G. Glenn Henry, Rodney E. Hooker, Terry Parks, Douglas R. Reed
  • Patent number: 10146828
    Abstract: A system and method of storing and analyzing information is disclosed. The system includes a compiler layer to convert user queries to data parallel executable code. The system further includes a library of multithreaded algorithms, processes, and data structures. The system also includes a multithreaded runtime library for implementing compiled code at runtime. The executable code is dynamically loaded on computing elements and contains calls to the library of multithreaded algorithms, processes, and data structures and the multithreaded runtime library.
    Type: Grant
    Filed: July 23, 2014
    Date of Patent: December 4, 2018
    Assignee: Battelle Memorial Institute
    Inventors: John T. Feo, David J. Haglin, Alessandro Morari, Antonino Tumeo, Oreste Villa, Jesse R. Weaver
  • Patent number: 10127041
    Abstract: A compiler system that converts an application source program into an executable program according to a predetermined ISA executable by a general purpose processor. The processor includes a PEU that is programmable to execute a UDI. The compiler system includes a PEU programming tool that converts a functional description of a processing operation to be performed by the PEU of the processor into programming information for programming the PEU to perform the processing operation in response to the specified UDI. The compiler system includes a compiler that converts the application source program into the executable program, which includes an optimization routine that represents a portion of the application source program with the specified UDI and that inserts the UDI into the executable program, and that further inserts into the executable program a UDI load instruction that specifies the UDI and a location of the programming information in the executable program.
    Type: Grant
    Filed: December 7, 2016
    Date of Patent: November 13, 2018
    Assignee: VIA ALLIANCE SEMICONDUCTOR CO., LTD.
    Inventors: G. Glenn Henry, Rodney E. Hooker, Terry Parks, Douglas R. Reed
  • Patent number: 10120689
    Abstract: An apparatus including first and second reservation stations. The first reservation station dispatches a load micro instruction, and indicates on a hold bus if the load micro instruction is a specified load micro instruction directed to retrieve an operand from a prescribed resource other than on-core cache memory. The second reservation station is coupled to the hold bus, and dispatches one or more younger micro instructions therein that depend on the load micro instruction for execution after a number of clock cycles following dispatch of the first load micro instruction, and if it is indicated on the hold bus that the load micro instruction is the specified load micro instruction, the second reservation station is configured to stall dispatch of the one or more younger micro instructions until the load micro instruction has retrieved the operand. The plurality of non-core resources includes a control element, coupled to the out-of order processor via a control bus.
    Type: Grant
    Filed: November 24, 2015
    Date of Patent: November 6, 2018
    Assignee: VIA ALLIANCE SEMICONDUCTOR CO., LTD
    Inventors: Gerard M. Col, Colin Eddy, G. Glenn Henry
  • Patent number: 10108430
    Abstract: An apparatus including first and second reservation stations. The first reservation station dispatches a load micro instruction, and indicates on a hold bus if the load micro instruction is a specified load micro instruction directed to retrieve an operand from a prescribed resource other than on-core cache memory. The second reservation station is coupled to the hold bus, and dispatches one or more younger micro instructions therein that depend on the load micro instruction for execution after a number of clock cycles following dispatch of the first load micro instruction, and if it is indicated on the hold bus that the load micro instruction is the specified load micro instruction, the second reservation station is configured to stall dispatch of the one or more younger micro instructions until the load micro instruction has retrieved the operand. The plurality of non-core resources includes a control element, coupled to the out-of order processor via a control bus.
    Type: Grant
    Filed: December 14, 2014
    Date of Patent: October 23, 2018
    Assignee: VIA ALLIANCE SEMICONDUCTOR CO., LTD
    Inventors: Gerard M. Col, Colin Eddy, G. Glenn Henry
  • Patent number: 10043230
    Abstract: Computer and graphics processing elements, connected generally in series, form a pipeline. Circuit elements known as di/dt throttles are inserted within the pipeline at strategic locations where the potential exists for data flow to transition from an idle state to a maximum data processing rate. The di/dt throttles gently ramp the rate of data flow from idle to a typical level. Disproportionate current draw and the consequent voltage droop are thus avoided, allowing an increased frequency of operation to be realized.
    Type: Grant
    Filed: September 20, 2013
    Date of Patent: August 7, 2018
    Assignee: NVIDIA CORPORATION
    Inventors: Philip Payman Shirvani, Peter Sommers, Eric T. Anderson
  • Patent number: 9996359
    Abstract: Fast issuance and execution of a multi-width instruction across multiple slices in a parallel slice processor core is supported in part through the use of an early notification signal passed between issue logic associated with multiple slices handling that multi-width instruction coupled with an issuance of a different instruction by the originating issue logic for the early notification signal.
    Type: Grant
    Filed: April 7, 2016
    Date of Patent: June 12, 2018
    Assignee: International Business Machines Corporation
    Inventors: Salma Ayub, Jeffrey C. Brownscheidle, Sundeep Chadha, Dung Q. Nguyen, Tu-An T. Nguyen, Salim A. Shah, Brian W. Thompto
  • Patent number: 9990198
    Abstract: A method for forwarding data from the store instructions to a corresponding load instruction in an out of order processor. The method includes accessing an incoming sequence of instructions, and of said sequence of instructions, splitting store instructions into a store address instruction and a store data instruction, wherein the store address performs address calculation and fetch, and wherein the store data performs a load of register contents to a memory address. The method further includes, of said sequence of instructions, splitting load instructions into a load address instruction and a load data instruction, wherein the load address performs address calculation and fetch, and wherein the load data performs a load of memory address contents into a register, and reordering the store address and load address instructions earlier and further away from LD/SD the instruction sequence to enable earlier dispatch and execution of the loads and the stores.
    Type: Grant
    Filed: December 11, 2014
    Date of Patent: June 5, 2018
    Assignee: Intel Corporation
    Inventors: Mohammad A. Abdallah, Gregory A. Woods
  • Patent number: 9985780
    Abstract: A hash value generating device for generating a hash value based on the KECCAK algorithm includes a ? processing unit, a ? processing unit, a ? processing unit, a ? processing unit, and an ? processing unit for performing processing of five steps ?, ?, ?, ?, and ?, included in round processing of the KECCAK algorithm. The ? processing unit includes a ?1 processing unit for performing column sum calculation processing and a ?2 processing unit for performing column sum addition processing. In the round processing, the ? processing unit performs processing before the ?2 processing unit and the ? processing unit performs processing, and the ? processing unit performs processing on a lane after rearrangement processing by the ? processing unit.
    Type: Grant
    Filed: February 17, 2014
    Date of Patent: May 29, 2018
    Assignee: Canon Kabushiki Kaisha
    Inventor: Shinya Yamada
  • Patent number: 9940242
    Abstract: A technique for processing instructions includes examining instructions in an instruction stream of a processor to determine properties of the instructions. The properties indicate whether the instructions may belong in an instruction sequence subject to decode-time instruction optimization (DTIO). Whether the properties of multiple ones of the instructions are compatible for inclusion within an instruction sequence of a same group is determined. The instructions with compatible ones of the properties are grouped into a first instruction group. The instructions of the first instruction group are decoded subsequent to formation of the first instruction group. Whether the first instruction group actually includes a DTIO sequence is verified based on the decoding. Based on the verifying, DTIO is performed on the instructions of the first instruction group or is not performed on the instructions of the first instruction group.
    Type: Grant
    Filed: November 17, 2014
    Date of Patent: April 10, 2018
    Assignee: International Business Machines Corporation
    Inventors: Michael K. Gschwind, Valentina Salapura
  • Patent number: 9922135
    Abstract: Technologies are described herein for distributed storage and retrieval of directed acyclic graphs, such as version control graphs maintained by a version control system. In order to store data contained in a directed acyclic graph, objects stored in the graph may be grouped into chunks utilizing a relatedness heuristic. The chunks may then be stored in a distributed object store. An index to the objects stored in the chunks may also be created that includes an index entry for each object. The index entry for each object includes a unique identifier for the object and data identifying the location of the object in the distributed object store. The index may be utilized to traverse the directed acyclic graph and to obtain all or a portion of the objects in the directed acyclic graph from the distributed object store.
    Type: Grant
    Filed: December 12, 2013
    Date of Patent: March 20, 2018
    Assignee: Amazon Technologies, Inc.
    Inventor: Matthew Roy Noble
  • Patent number: 9917512
    Abstract: An electronic device is provided, which includes a user interface unit configured to receive an input of a user command, a controller configured to perform an operation according to the input user command and to control the user interface to display a screen according to the result of the operation, and a power supply configured to provide a power to the user interface and the controller, wherein the power supply includes a plurality of converters configured to supply the power to respective loads of the electronic device, and the plurality of converters output voltage values that correspond to levels of the respective loads connected thereto.
    Type: Grant
    Filed: July 17, 2014
    Date of Patent: March 13, 2018
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventor: Jae-deok Cha
  • Patent number: 9870045
    Abstract: Reducing power consumption in a multi-slice computer processor that includes a re-order buffer and an architected register file, including: designating an entry in the re-order buffer as being invalid and unwritten; assigning a pending instruction to the entry in the re-order buffer; responsive to assigning the pending instruction to the entry in the re-order buffer, designating the entry as being valid; writing data generated by executing the pending instruction into the re-order buffer; and responsive to writing data generated by executing the pending instruction into the re-order buffer, designating the entry as being written.
    Type: Grant
    Filed: February 17, 2016
    Date of Patent: January 16, 2018
    Assignee: International Business Machines Corporation
    Inventors: Steven J. Battle, Owen Chiang, Sam G. Chu, Saiful Islam, Dung Q. Nguyen, David R. Terry, Eula A. Tolentino
  • Patent number: 9870253
    Abstract: A transaction within a computer program or computer application comprises program instructions performing multiple store operations that appear to run and complete as a single, atomic operation. The program instructions forming a current transaction comprise a transaction begin indicator, a plurality of instructions (e.g., store operations), and a transaction end indicator. A near-end of transaction indicator is triggered based on a speculative look ahead operation such that an interfering transaction requiring a halt operation may be delayed to allow the current transaction to end. A halt operation, also referred to as an abort operation, as used herein refers to an operation responsive to a condition where two transactions have been detected to interfere where at least one transaction must be aborted and the state of the processor is reset to the state at the beginning of the aborted transaction by performing a rollback.
    Type: Grant
    Filed: May 27, 2015
    Date of Patent: January 16, 2018
    Assignee: International Business Machines Corporation
    Inventors: Michael Karl Gschwind, Maged M. Michael, Valentina Salapura
  • Patent number: 9832199
    Abstract: A computer-implemented method, system, and/or computer program product protects access to hardware devices through use of a secure processor. A security computer receives a request from a requesting computer for access to a hardware device on a network. A secure processor within the security computer encrypts the request to generate an encrypted request, which is generated within a core of the secure processor. The secure processor protects a secure application that is used to process the request from other software on the secure processor. The security computer transmits the encrypted request to the hardware device, and then receives an encrypted acknowledgement of the encrypted request from a processor associated with the hardware device. The security computer then creates a communication session between the requesting computer and the hardware device.
    Type: Grant
    Filed: September 25, 2015
    Date of Patent: November 28, 2017
    Assignee: International Business Machines Corporation
    Inventors: Richard H. Boivie, Robert R. Friedlander, James R. Kraemer, Jeb R. Linton
  • Patent number: 9830284
    Abstract: The disclosure includes, in general, among other aspects, an apparatus having multiple programmable units integrated within a processor. The apparatus has circuitry to map addresses in a single address space to resources within the multiple programmable units where the single address space includes addresses for different ones of the resources in different ones of the multiple programmable units and where there is a one-to-one correspondence between respective addresses in the single address space and resources within the multiple programmable units.
    Type: Grant
    Filed: July 27, 2015
    Date of Patent: November 28, 2017
    Assignee: Intel Corporation
    Inventors: Gilbert Wolrich, Debra Bernstein, Daniel Cutter, Christopher Dolan, Matthew J. Adiletta
  • Patent number: 9817967
    Abstract: An access management robot facilitation system facilitates a robot to execute access management tasks on a target system.
    Type: Grant
    Filed: January 13, 2017
    Date of Patent: November 14, 2017
    Assignee: ACCENTURE GLOBAL SOLUTIONS LIMITED
    Inventors: Sanjeev Shukla, Gaurav Tandon, Rexall E. Thexton, Neha Joshi, David Michael Parker, Avinash Ramesh, Krishna M. Dasari, Parvathy Ramakrishnan
  • Patent number: 9811335
    Abstract: End-user software is used to select lists of values of control signals from a predetermined design of a processor, and a unique value of an opcode is assigned to each selected list of values of control signals. The assignments, of opcode values to lists of values of control signals, are used to create a new processor design customized for the end-user software, followed by synthesis, place and route, and netlist generation based on the new processor design, followed by configuring an FPGA based on the netlist, followed by execution of the end-user software in customized processor implemented by the FPGA. Different end-user software may be used as input to generate different assignments, of opcode values to lists of control signal values, followed by generation of different netlists. The different netlists may be used at different times, to reconfigure the same FPGA, to execute different end-user software optimally at different times.
    Type: Grant
    Filed: October 14, 2013
    Date of Patent: November 7, 2017
    Assignee: QuickLogic Corporation
    Inventors: Oleg Nikitovich Khainovski, Dan Aizenstros, Randy Ichiro Oyadomari, Timothy Saxe
  • Patent number: 9778932
    Abstract: A Vector Generate Mask instruction. For each element in the first operand, a bit mask is generated. The mask includes bits set to a selected value starting at a position specified by a first field of the instruction and ending at a position specified by a second field of the instruction.
    Type: Grant
    Filed: January 23, 2013
    Date of Patent: October 3, 2017
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Jonathan D. Bradbury, Robert F. Enenkel, Eric M. Schwarz, Timothy J. Slegel
  • Patent number: 9740482
    Abstract: A Vector Generate Mask instruction. For each element in the first operand, a bit mask is generated. The mask includes bits set to a selected value starting at a position specified by a first field of the instruction and ending at a position specified by a second field of the instruction.
    Type: Grant
    Filed: December 5, 2014
    Date of Patent: August 22, 2017
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Jonathan D. Bradbury, Robert F. Enenkel, Eric M. Schwarz, Timothy J. Slegel
  • Patent number: 9710350
    Abstract: An aspect includes performance profiling of an application. A processor executes an instruction stream of the application including instructions that are dynamically grouped at run-time. The processor monitors for an event associated with sampled instructions. A sampled instruction is associated with other events that include instruction grouping information. A number of the instructions in a group that includes the sampled instruction is determined as a group size. The monitored event is tracked as separate events with respect to each of the sampled instruction and one or more other instructions of the group. Subsequent monitored events are tracked as the separate events for each of the instructions from additional groups having various group sizes formed from a sequence of the instructions. An execution count for the sequence of the instructions is generated based on accumulating the separate events over a period of time.
    Type: Grant
    Filed: October 21, 2015
    Date of Patent: July 18, 2017
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Moshe Klausner, Nitzan Peleg
  • Patent number: 9710354
    Abstract: An aspect includes performance profiling of an application. A processor executes an instruction stream of the application including instructions that are dynamically grouped at run-time. The processor monitors for an event associated with sampled instructions. A sampled instruction is associated with other events that include instruction grouping information. A number of the instructions in a group that includes the sampled instruction is determined as a group size. The monitored event is tracked as separate events with respect to each of the sampled instruction and one or more other instructions of the group. Subsequent monitored events are tracked as the separate events for each of the instructions from additional groups having various group sizes formed from a sequence of the instructions. An execution count for the sequence of the instructions is generated based on accumulating the separate events over a period of time.
    Type: Grant
    Filed: August 31, 2015
    Date of Patent: July 18, 2017
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Moshe Klausner, Nitzan Peleg
  • Patent number: 9696998
    Abstract: The apparatuses, systems, and methods in accordance with the embodiments disclosed herein may facilitate modifying post silicon instruction behavior. Embodiments herein may provide registers in predetermined locations in an integrated circuit. These registers may be mapped to generic instructions, which can modify an operation of the integrated circuit. In some embodiments, these registers may be used to implement a patch routine to change the behavior of at least a portion of the integrated circuit. In this manner, the original design of the integrated circuit may be altered.
    Type: Grant
    Filed: August 29, 2013
    Date of Patent: July 4, 2017
    Assignee: Advanced Micro Devices, Inc.
    Inventor: Frank C Galloway
  • Patent number: 9645866
    Abstract: This disclosure describes communication techniques that may be used within a multiple-processor computing platform. The techniques may, in some examples, provide software interfaces that may be used to support message passing within a multiple-processor computing platform that initiates tasks using command queues. The techniques may, in additional examples, provide software interfaces that may be used for shared memory inter-processor communication within a multiple-processor computing platform. In further examples, the techniques may provide a graphics processing unit (GPU) that includes hardware for supporting message passing and/or shared memory communication between the GPU and a host CPU.
    Type: Grant
    Filed: September 16, 2011
    Date of Patent: May 9, 2017
    Assignee: QUALCOMM Incorporated
    Inventors: Alexei V. Bourd, Colin Christopher Sharp, David Rigel Garcia Garcia, Chihong Zhang
  • Patent number: 9632779
    Abstract: A method and circuit arrangement for selectively predicating instructions in an instruction stream based upon a predication filter criteria defined by a predication filter, which describes types or patterns of instructions that should be predicated. Predication logic compares a respective instruction of an instruction stream to predication filter criteria to determine whether the respective instruction matches the predication filter criteria, and the respective instruction is selectively predicated based on whether the respective instruction matches the predication filter criteria.
    Type: Grant
    Filed: December 19, 2011
    Date of Patent: April 25, 2017
    Assignee: International Business Machines Corporation
    Inventors: Adam J. Muff, Paul E. Schardt, Robert A. Shearer, Matthew R. Tubbs
  • Patent number: 9606806
    Abstract: A method includes selecting for execution in a processor a load instruction having at least one dependent instruction. Responsive to selecting the load instruction, the at least one dependent instruction is selectively awakened based on a status of a store instruction associated with the load instruction to indicate that the at least one dependent instruction is eligible for execution. A processor includes an instruction pipeline having an execution unit to execute instructions, a scheduler, and a controller. The scheduler selects for execution in the execution unit a load instruction having at least one dependent instruction. The controller, responsive to the scheduler selecting the load instruction, selectively awakens the at least one dependent instruction based on a status of a store instruction associated with the load instruction to indicate that the at least one dependent instruction is eligible for execution by the execution unit.
    Type: Grant
    Filed: June 25, 2013
    Date of Patent: March 28, 2017
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Gregory W. Smaus, Michael Achenbach, Christopher J. Burke, Francesco Spadini
  • Patent number: 9600282
    Abstract: Embodiments relate to vector processors. An aspect includes endian-mode-sensitive memory instructions for a vector processor. One embodiment includes a computer-implemented method for copying data between a vector register that includes byte elements 0 to S and a memory that is byte addressable. The computer-implemented method includes obtaining a vector instruction by a processor in a computer. The processor determines that the vector instruction is a memory access instruction specifying the vector register and a memory address. In response to the determination that is instruction is a memory access instruction and independent of a current global endian mode setting that is selectable in the processor, the processor executes the memory access instruction by copying the byte data between the memory and the vector register so that the byte element n of the vector register corresponds to the memory address+n for n=0 to S.
    Type: Grant
    Filed: May 29, 2015
    Date of Patent: March 21, 2017
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Michael K. Gschwind, Brett Olsson
  • Patent number: 9519324
    Abstract: Technologies for local power gate (LPG) interfaces for power-aware operations are described. A processor includes locally-gated circuitry of a core, main core circuitry of the core, the main core, and local power gate (LPG) hardware. The LPG hardware is to power gate the locally-gated circuitry according to local power states of the LPG hardware. The main core decodes a first instruction of a set of instructions to perform a first power-aware operation of a specified length, including computing an execution code path for execution. The main core monitors a current local power state of the LPG hardware, selects one of the code paths based on the current local power state, the specified length, and a specified threshold, and issues a hint to the LPG hardware to power up the locally-gated circuitry and continues execution of the first power-aware operation without waiting for the locally-gated circuitry to be powered up.
    Type: Grant
    Filed: March 26, 2014
    Date of Patent: December 13, 2016
    Assignee: Intel Corporation
    Inventors: Michael Mishaeli, Ron Gabor, Robert C. Valentine, Alex Gerber, Zeev Sperber
  • Patent number: 9436467
    Abstract: A Vector Floating Point Test Data Class Immediate instruction is provided that determines whether one or more elements of a vector specified in the instruction are of one or more selected classes and signs. If a vector element is of a selected class and sign, an element in an operand of the instruction corresponding to the vector element is set to a first defined value, and if the vector element is not of the selected class and sign, the operand element corresponding to the vector element is set to a second defined value.
    Type: Grant
    Filed: December 5, 2014
    Date of Patent: September 6, 2016
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Jonathan D. Bradbury, Eric M. Schwarz
  • Patent number: 9424040
    Abstract: An LSI includes an address decoder in which combinations of IP cores and control registers simultaneously accessed according to an operation mode signal are set in advance, so that the plurality of control registers can be accessed with a single system address signal. Therefore, it is unnecessary that the CPU is provided with selection signals whose number is equal to that of the combinations of the control registers. This reduces coding work for operating CPU, reducing work in developing a program of the CPU.
    Type: Grant
    Filed: July 4, 2013
    Date of Patent: August 23, 2016
    Assignee: Mitsubishi Electric Corporation
    Inventors: Yusuke Shimai, Osamu Toyama, Yoshihiro Ogawa
  • Patent number: 9405534
    Abstract: A processor system includes a multichannel memory operable to store data values and a program memory operable to store Compound CISC (CCISC) instructions. The processor system also includes a processor operable to execute a computer program assembled with at least a portion of the compound CCISC instructions, to retrieve a CCISC instruction from the program memory, to access at least two data values in the multichannel memory based on the executed computer program, and to operate on the at least two data values in the multichannel memory based on the CCISC instruction. The processor retrieves the CCISC instruction, accesses the at least two data values, and operates on the at least two data values during a same clock cycle.
    Type: Grant
    Filed: January 21, 2013
    Date of Patent: August 2, 2016
    Inventor: Tom Yap
  • Patent number: 9389939
    Abstract: An information processing apparatus according to one aspect of the present disclosure includes a communication control portion, an error code storage portion, an acquiring portion, and a determination portion. Communication control portion communicates with storage device based on interface communication standard, to perform data transfer therewith. Error code storage portion stores one or a plurality of selected error codes selected from a plurality of error codes defined by interface communication standard. Acquiring portion acquires error information outputted from storage device. Determination portion determines whether or not error code indicated by error information coincides with selected error code. When determination portion determines that error code coincides with selected error code, communication control portion communicates again with storage device to perform data transfer therewith.
    Type: Grant
    Filed: March 24, 2014
    Date of Patent: July 12, 2016
    Assignee: KYOCERA Document Solutions Inc.
    Inventors: Naruyuki Miyamoto, Tomoyuki Kikuta, Takashi Inoue, Tetsuya Matsusaka
  • Patent number: 9348723
    Abstract: A method for retrieving trace data from a target device is proposed. The target device comprises a program memory, a processor, a trace unit, and a trace buffer. The processor is operable to retrieve instructions from the program memory and to execute them. The trace buffer may contain trace data generated by the trace unit in response to the processor retrieving or executing instructions from the program memory. One or more patch instructions are written to the program memory. The processor executes said one or more patch instructions. The target device, in response to the processor executing said one or more patch instructions, performs a data transfer operation for copying the trace data from the trace buffer to a second memory outside the target device.
    Type: Grant
    Filed: January 21, 2011
    Date of Patent: May 24, 2016
    Assignee: Freescale Semiconductor, Inc.
    Inventors: Razvan Ionescu, Ionut-Valentin Vicovan
  • Patent number: 9342397
    Abstract: A transactional memory system salvages a hardware transaction. A processor of the transactional memory system executes a salvage indicator instruction, such execution including obtaining a salvage indication information specified by the salvage indicator instruction, and saving the salvage indication information comprising a salvage indication. Based on a pending point of failure being detected, the processor uses the saved salvage indication information to avoid aborting a hardware transaction, wherein absent salvage indication information, the pending point of failure causes a hardware transaction to abort. The processor detects the point of failure, and based on the detecting, determines whether the salvage indication has been recorded. Based on determining that the salvage indication has been recorded, the processor executes an about-to-fail handler, and based on determining that the salvage indication has not been recorded, the processor aborts the transactional execution of the code region.
    Type: Grant
    Filed: September 16, 2015
    Date of Patent: May 17, 2016
    Assignee: International Business Machines Corporation
    Inventors: Fadi Y. Busaba, Harold W. Cain, III, Maged M. Michael, Valentina Salapura, Eric M. Schwarz
  • Patent number: 9336097
    Abstract: A transactional memory system salvages a partially executed hardware transaction. A processor of the transactional memory system determines information about an about-to-fail handler for transactional execution of a code region of a hardware transaction. The processor saves state information of the hardware transaction, the state information usable to determine whether the hardware transaction is to be salvaged or to be aborted. The processor detects an about-to-fail condition during the transactional execution of the hardware transaction. The processor, based on the detecting, executes the about-to-fail handler using the information about the about-to-fail handler, the about-to-fail handler determining whether the hardware transaction is to be salvaged or to be aborted.
    Type: Grant
    Filed: February 27, 2014
    Date of Patent: May 10, 2016
    Assignee: International Business Machines Corporation
    Inventors: Harold W. Cain, III, Michael Karl Gschwind, Maged M. Michael, Valentina Salapura, Eric M. Schwarz
  • Patent number: 9338149
    Abstract: A process for converting a DTCP-IP transport stream into HLS format, comprising receiving an encrypted DTCP-IP transport stream comprising DTCP frames at a secondary device from a source device, with each of the plurality of DTCP frames comprising encrypted 16-byte portions, forming chunks from the DTCP frames by grouping encrypted 16-byte portions into a chunk, adding HLS padding bytes to the end of each chunk and encrypting the HLS padding bytes to form an encrypted chunk, loading each of the encrypted chunks and a playlist to a media proxy server at the secondary device, loading a DTCP key onto a security proxy server, and providing the playlist, each of the encrypted chunks, and the DTCP key to a native media player on the secondary device, such that the native media player follows the playlist to decrypt the encrypted chunks using the DTCP key and plays back the chunks.
    Type: Grant
    Filed: March 17, 2014
    Date of Patent: May 10, 2016
    Assignee: ARRIS Enterprises, Inc.
    Inventor: Paul Moroney
  • Patent number: 9329946
    Abstract: A transactional memory system salvages a partially executed hardware transaction. A processor of the transactional memory system saves state information in a first code region of a first hardware transaction, the state information useable to determine whether the first hardware transaction is to be salvaged or to be aborted. The processor detects an about to fail condition in the first code region of the first hardware transaction. The processor, based on the detecting, executes an about-to-fail handler, the about-to-fail handler using the saved state information to determine whether the first hardware transaction is to be salvaged or to be aborted. The processor executing the about-to-fail handler, based on the transaction being to be salvaged, uses the saved state information to determine what portion of the first hardware transaction to salvage.
    Type: Grant
    Filed: February 27, 2014
    Date of Patent: May 3, 2016
    Assignee: International Business Machines Corporation
    Inventors: Harold W. Cain, III, Michael Karl Gschwind, Maged M. Michael, Valentina Salapura, Eric M. Schwarz
  • Patent number: 9317263
    Abstract: Hardware compilation and/or translation with fault detection and roll back functionality are disclosed. Compilation and/or translation logic receives programs encoded in one language, and encodes the programs into a second language including instructions to support processor features not encoded into the original language encoding of the programs. In one embodiment, an execution unit executes instructions of the second language including an operation-check instruction to perform a first operation and record the first operation result for a comparison, and an operation-test instruction to perform a second operation and a fault detection operation by comparing the second operation result to the recorded first operation result.
    Type: Grant
    Filed: October 14, 2014
    Date of Patent: April 19, 2016
    Assignee: Intel Corporation
    Inventors: Nicholas Cheng Hwa Chee, Tryggve Fossum, William C. Hasenplaugh
  • Patent number: 9311178
    Abstract: A transactional memory system salvages a hardware transaction. A processor of the transactional memory system executes a salvage indicator instruction, such execution including obtaining a salvage indication information specified by the salvage indicator instruction, and saving the salvage indication information comprising a salvage indication. Based on a pending point of failure being detected, the processor uses the saved salvage indication information to avoid aborting a hardware transaction, wherein absent salvage indication information, the pending point of failure causes a hardware transaction to abort. The processor detects the point of failure, and based on the detecting, determines whether the salvage indication has been recorded. Based on determining that the salvage indication has been recorded, the processor executes an about-to-fail handler, and based on determining that the salvage indication has not been recorded, the processor aborts the transactional execution of the code region.
    Type: Grant
    Filed: February 27, 2014
    Date of Patent: April 12, 2016
    Assignee: International Business Machines Corporation
    Inventors: Fadi Y. Busaba, Harold W. Cain, III, Maged M. Michael, Valentina Salapura, Eric M. Schwarz
  • Patent number: 9305164
    Abstract: The effects on networking systems of attacks on vulnerabilities, such as vulnerable modules in a webserver, SYN flooding, etc, can be devastating to a network environment. In various embodiments, a first, quick, or inexpensive analysis is performed on incoming network flows. If an intrusion issue or other problem is suspected based on the first, rapid, or an inexpensive analysis, then the flow can be flagged for redirection to another process, virtual machine, or physical computer module that will perform a deeper, more expensive analysis on the network flow. If there are no issues detected in the second, deeper analysis, then the network flow can be forwarded to its intended recipient. If an issue is detected in the second, deeper analysis, then the network flow can be throttled, quarantined, ignored, sent to an un-trusted portion of the system, sent for more analysis, or otherwise handled or flagged.
    Type: Grant
    Filed: August 12, 2013
    Date of Patent: April 5, 2016
    Assignee: Amazon Technologies, Inc.
    Inventors: Eric Jason Brandwine, Swaminathan Sivasubramanian, Bradley E. Marshall, Tate Andrew Certain
  • Patent number: 9292290
    Abstract: A circuit arrangement decodes instructions based in part on one or more decode-related attributes stored in a memory address translation data structure such as an Effective To Real Translation (ERAT) or Translation Lookaside Buffer (TLB). A memory address translation data structure may be accessed, for example, in connection with a decode of an instruction stored in a page of memory, such that one or more attributes associated with the page in the data structure may be used to control how that instruction is decoded.
    Type: Grant
    Filed: July 23, 2013
    Date of Patent: March 22, 2016
    Assignee: International Business Machines Corporation
    Inventors: Adam J. Muff, Paul E. Schardt, Robert A. Shearer, Matthew R. Tubbs
  • Patent number: 9286071
    Abstract: A method decodes instructions based in part on one or more decode-related attributes stored in a memory address translation data structure such as an Effective To Real Translation (ERAT) or Translation Lookaside Buffer (TLB). A memory address translation data structure may be accessed, for example, in connection with a decode of an instruction stored in a page of memory, such that one or more attributes associated with the page in the data structure may be used to control how that instruction is decoded.
    Type: Grant
    Filed: August 28, 2015
    Date of Patent: March 15, 2016
    Assignee: International Business Machines Corporation
    Inventors: Adam J. Muff, Paul E. Schardt, Robert A. Shearer, Matthew R. Tubbs
  • Patent number: 9280352
    Abstract: An apparatus and method for avoiding bubbles and maintaining a maximum instruction throughput rate when cracking microcode instructions. A lookahead pointer scans the newest entries of a dispatch queue for microcode instructions. A detected microcode instruction is conveyed to a microcode engine to be cracked into a sequence of micro-ops. Then, the sequence of micro-ops is placed in a queue, and when the original microcode instruction entry in the dispatch queue is selected for dispatch, the sequence of micro-ops is dispatched to the next stage of the processor pipeline.
    Type: Grant
    Filed: November 30, 2011
    Date of Patent: March 8, 2016
    Assignee: Apple Inc.
    Inventors: Ramesh B. Gunna, Peter J. Bannon, Rajat Goel
  • Patent number: 9268567
    Abstract: Instructions and logic provide extended vector suffix comparisons for Boyer-Moore searches. Some embodiments, responsive to an instruction specifying: a pattern source operand and a target source operand, compare each of m data elements of the pattern operand with each data element of the target operand. A first and second equal ordered aggregation operation are performed from the comparisons according to the m data elements of the pattern source operand. A result of the first and second aggregation operations indicating whether or not a possible match exists between the m data elements of the pattern source operand and d data element positions relative to data elements of the target source operand is stored. Ordering of the data elements of the pattern and the target operands may be reversed for the second aggregation operation, and d may be a sum of m?1 and the quantity of target operand elements in some embodiments.
    Type: Grant
    Filed: September 30, 2012
    Date of Patent: February 23, 2016
    Assignee: Intel Corporation
    Inventor: Shih J. Kuo