Instruction Decoding (e.g., By Microinstruction, Start Address Generator, Hardwired) Patents (Class 712/208)
  • Patent number: 11132633
    Abstract: The disclosed embodiments illustrate a method and a system for controlling KPI parameters of a transportation system. The method includes extracting historical commuting characteristics of one or more commuters, from a database server over a communication network. The method further includes generating a predictive model based on the extracted historical commuting characteristics. The method further includes generating a service schedule of one or more transportation services of the transportation system. The service schedule of the one or more transportation services may be generated by use of the generated predictive model, based on defined criteria of the transportation system. The method further includes controlling a KPI parameter of the transportation system to attain a desired KPI parameter of the KPI parameter, based on the generated service schedule, when the one or more transportation services are deployed at one or more time stamps.
    Type: Grant
    Filed: December 16, 2016
    Date of Patent: September 28, 2021
    Assignee: Conduent Business Services, LLC
    Inventors: Theja Tulabandhula, Asim Anand, Deeksha Sinha
  • Patent number: 11132599
    Abstract: Processors and methods for neural network processing are provided. A method in a processor including a pipeline having a matrix vector unit (MVU), a first multifunction unit connected to receive an input from the MVU, a second multifunction unit connected to receive an output from the first multifunction unit, and a third multifunction unit connected to receive an output from the second multifunction unit is provided. The method includes decoding instructions including a first type of instruction for processing by only the MVU and a second type of instruction for processing by only one of the multifunction units. The method includes mapping a first instruction for processing by the matrix vector unit or to any one of the first multifunction unit, the second multifunction unit, or the third multifunction unit depending on whether the first instruction is the first type of instruction or the second type of instruction.
    Type: Grant
    Filed: June 29, 2017
    Date of Patent: September 28, 2021
    Assignee: Microsoft Technology Licensing, LLC
    Inventors: Eric S. Chung, Douglas C. Burger, Jeremy Fowers
  • Patent number: 11128443
    Abstract: A processor includes a decode unit to decode an SM3 two round state word update instruction. The instruction is to indicate one or more source packed data operands. The source packed data operand(s) are to have eight 32-bit state words Aj, Bj, Cj, Dj, Ej, Fj, Gj, and Hj that are to correspond to a round (j) of an SM3 hash algorithm. The source packed data operand(s) are also to have a set of messages sufficient to evaluate two rounds of the SM3 hash algorithm. An execution unit coupled with the decode unit is operable, in response to the instruction, to store one or more result packed data operands, in one or more destination storage locations. The result packed data operand(s) are to have at least four two-round updated 32-bit state words Aj+2, Bj+2, Ej+2, and Fj+2, which are to correspond to a round (j+2) of the SM3 hash algorithm.
    Type: Grant
    Filed: November 6, 2020
    Date of Patent: September 21, 2021
    Assignee: Intel Corporation
    Inventors: Shay Gueron, Vlad Krasnov
  • Patent number: 11113065
    Abstract: A technique for speculatively executing load-dependent instructions includes detecting that a memory ordering consistency queue is full for a completed load instruction. The technique also includes storing data loaded by the completed load instruction into a storage location for storing data when the memory ordering consistency queue is full. The technique further includes speculatively executing instructions that are dependent on the completed load instruction. The technique also includes in response to a slot becoming available in the memory ordering consistency queue, replaying the load instruction. The technique further includes in response to receiving loaded data for the replayed load instruction, testing for a data mis-speculation by comparing the loaded data for the replayed load instruction with the data loaded by the completed load instruction that is stored in the storage location.
    Type: Grant
    Filed: October 31, 2019
    Date of Patent: September 7, 2021
    Assignee: Advanced Micro Devices, Inc.
    Inventors: John Kalamatianos, Susumu Mashimo, Krishnan V. Ramani, Scott Thomas Bingham
  • Patent number: 11113053
    Abstract: A processor includes a decode unit to decode an instruction that is to indicate a first source packed data operand that is to include at least four data elements, to indicate a second source packed data operand that is to include at least four data elements, and to indicate one or more destination storage locations. The execution unit, in response to the instruction, is to store at least one result mask operand in the destination storage location(s). The at least one result mask operand is to include a different mask element for each corresponding data element in one of the first and second source packed data operands in a same relative position. Each mask element is to indicate whether the corresponding data element in said one of the source packed data operands equals any of the data elements in the other of the source packed data operands.
    Type: Grant
    Filed: September 23, 2019
    Date of Patent: September 7, 2021
    Assignee: Intel Corporation
    Inventors: Asit K. Mishra, Edward T. Grochowski, Jonathan D. Pearce, Deborah T. Marr, Ehud Cohen, Elmoustapha Ould-Ahmed-Vall, Jesus Corbal San Adrian, Robert Valentine, Mark J. Charney, Christopher J. Hughes, Milind B. Girkar
  • Patent number: 11080813
    Abstract: An apparatus to facilitate compute optimization is disclosed. The apparatus includes a mixed precision core to perform a mixed precision multi-dimensional matrix multiply and accumulate operation on 8-bit and/or 32 bit signed or unsigned integer elements.
    Type: Grant
    Filed: September 26, 2019
    Date of Patent: August 3, 2021
    Assignee: Intel Corporation
    Inventors: Abhishek R. Appu, Altug Koker, Linda L. Hurd, Dukhwan Kim, Mike B. Macpherson, John C. Weast, Feng Chen, Farshad Akhbari, Narayan Srinivasa, Nadathur Rajagopalan Satish, Joydeep Ray, Ping T. Tang, Michael S. Strickland, Xiaoming Chen, Anbang Yao, Tatiana Shpeisman
  • Patent number: 11080811
    Abstract: An apparatus to facilitate compute optimization is disclosed. The apparatus includes a mixed precision core to perform a mixed precision multi-dimensional matrix multiply and accumulate operation on 16-bit and/or 32 bit floating-point elements.
    Type: Grant
    Filed: June 19, 2019
    Date of Patent: August 3, 2021
    Assignee: Intel Corporation
    Inventors: Abhishek R. Appu, Altug Koker, Linda L. Hurd, Dukhwan Kim, Mike B. Macpherson, John C. Weast, Feng Chen, Farshad Akhbari, Narayan Srinivasa, Nadathur Rajagopalan Satish, Joydeep Ray, Ping T. Tang, Michael S. Strickland, Xiaoming Chen, Anbang Yao, Tatiana Shpeisman
  • Patent number: 11075746
    Abstract: A processor includes a decode unit to decode an SM3 two round state word update instruction. The instruction is to indicate one or more source packed data operands. The source packed data operand(s) are to have eight 32-bit state words Aj, Bj, Cj, Dj, Ej, Fj, Gj, and Hj that are to correspond to a round (j) of an SM3 hash algorithm. The source packed data operand(s) are also to have a set of messages sufficient to evaluate two rounds of the SM3 hash algorithm. An execution unit coupled with the decode unit is operable, in response to the instruction, to store one or more result packed data operands, in one or more destination storage locations. The result packed data operand(s) are to have at least four two-round updated 32-bit state words Aj+2, Bj+2, Ej+2, and Fj+2, which are to correspond to a round (j+2) of the SM3 hash algorithm.
    Type: Grant
    Filed: April 13, 2020
    Date of Patent: July 27, 2021
    Assignee: Intel Corporation
    Inventors: Shay Gueron, Vlad Krasnov
  • Patent number: 11062065
    Abstract: A matching method for multiple reaction chambers includes selecting at least one factor, setting an adjustment coefficient for the factor corresponding to each of the reaction chambers, and obtaining an input value of the factor to enter into each reaction chamber based on the target value of the factor and the adjustment coefficient corresponding to each of the reaction chambers. The processing factor has a target value and a real value corresponding to each of the reaction chamber. The adjustment coefficient is based on the real value and the target value of the factor being within a preset accuracy range when the corresponding chamber operates a process.
    Type: Grant
    Filed: May 26, 2020
    Date of Patent: July 13, 2021
    Assignee: BEIJING NAURA MICROELECTRONICS EQUIPMENT CO., LTD.
    Inventors: Jihong Zhang, Jinsheng Fu
  • Patent number: 11061682
    Abstract: The invention relates to a method for processing instructions out-of-order on a processor comprising an arrangement of execution units. The inventive method comprises looking up operand sources in a Register Positioning Table and setting operand input references of the instruction to be issued accordingly, checking for an Execution Unit (EXU) available for receiving a new instruction, and issuing the instruction to the available Execution Unit and entering a reference of the result register addressed by the instruction to be issued to the Execution Unit into the Register Positioning Table (RPT).
    Type: Grant
    Filed: December 13, 2015
    Date of Patent: July 13, 2021
    Inventor: Martin Vorbach
  • Patent number: 11054890
    Abstract: Techniques to control power and processing among a plurality of asymmetric processing elements are disclosed. In one embodiment, one or more asymmetric processing elements are power managed to migrate processes or threads among a plurality of processing elements according to the performance and power needs of the system.
    Type: Grant
    Filed: July 31, 2013
    Date of Patent: July 6, 2021
    Assignee: Intel Corporation
    Inventors: Herbert Hum, Eric Sprangle, Doug Carmean, Rajesh Kumar
  • Patent number: 11055094
    Abstract: Disclosed embodiments relate to improved heterogeneous CPUID spoofing for remote processors. In one example, a system includes multiple processors, including a first processor including configuration circuitry to enable remote processor identification (ID) spoofing; fetch circuitry to fetch an instruction; decode circuitry to decode the instruction having fields to specify an opcode and a context, the opcode indicating execution circuitry is to: when remote processor ID spoofing is enabled, access a processor ID spoofing data structure storing processor ID information for each of the plurality of processors, and report processor ID information for a processor identified by the context; and, when remote processor ID spoofing is not enabled, report processor ID information for the first processor; and execution circuitry to execute the instruction as per the opcode.
    Type: Grant
    Filed: June 26, 2019
    Date of Patent: July 6, 2021
    Assignee: Intel Corporation
    Inventors: Toby Opferman, Russell C. Arnold, Vedvyas Shanbhogue, Michael W. Chynoweth
  • Patent number: 11051047
    Abstract: A better compromise between encoding complexity and achievable rate distortion ratio, and/or to achieve a better rate distortion ratio is achieved by using multitree sub-divisioning not only in order to subdivide a continuous area, namely the sample array, into leaf regions, but using the intermediate regions also to share coding parameters among the corresponding collocated leaf blocks. By this measure, coding procedures performed in tiles—leaf regions—locally, may be associated with coding parameters individually without having to, however, explicitly transmit the whole coding parameters for each leaf region separately. Rather, similarities may effectively exploited by using the multitree subdivision.
    Type: Grant
    Filed: October 9, 2020
    Date of Patent: June 29, 2021
    Assignee: GE Video Compression, LLC
    Inventors: Philipp Helle, Detlev Marpe, Simon Oudin, Thomas Wiegand
  • Patent number: 11036500
    Abstract: Processing circuitry performs processing operations specified by program instructions. An instruction decoder decodes an atomic-add-with-carry instruction AADDC to control the processing circuitry to perform an atomic operation of an add of an addend operand value and a data value stored in a memory to generate a result value stored in the memory and a carry value indicative of whether or not the add generated a carry out. The atomic-add-with-carry instructions may be used within systems which accumulate a local sum value prior to a data value being returned into a local cache memory at which time the local sum value is added to the return data value. The atomic-add-with-carry instructions may also be used in embodiments comprising a coalescing tree of respective processing apparatus where the carry out values generated from local sums produced at each node are returned early to higher nodes within the hierarchy thereby releasing them to commence other processing.
    Type: Grant
    Filed: October 23, 2019
    Date of Patent: June 15, 2021
    Assignee: Arm Limited
    Inventor: Andreas Due Engh-Halstvedt
  • Patent number: 11005503
    Abstract: Memory controllers, decoders and methods execute a hybrid decoding scheme. An initial iteration of decoding of a codeword is performed using a bit-flipping (BF) decoder or a min-sum (MS) decoder depending on whether or not an unsatisfied check (USC) count of the codeword is less than a threshold. For this initial iteration, the BF decoder is used when the USC count is less than the threshold, and MS decoder when the USC count is greater than or equal to the threshold. When decoding of the codeword is initially performed with the BF decoder, decoding continues with the BF decoder until a first set of conditions is satisfied or the codeword is successfully decoded. When decoding of the codeword is performed with the MS decoder, decoding continues with the MS decoder until a second set of conditions is satisfied.
    Type: Grant
    Filed: March 8, 2019
    Date of Patent: May 11, 2021
    Assignee: SK hynix Inc.
    Inventors: Naveen Kumar, Aman Bhatia, Abhiram Prabhakar, Chenrong Xiong, Fan Zhang
  • Patent number: 10977185
    Abstract: Initializing a data structure for use in predicting table of contents (TOC) pointer values. A request to load a module is obtained. Based on the loaded module, a pointer value for a reference data structure is determined. The pointer value is stored in a reference data structure tracking structure, and used to access a variable value for a variable of the module.
    Type: Grant
    Filed: November 17, 2017
    Date of Patent: April 13, 2021
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Michael K. Gschwind, Valentina Salapura
  • Patent number: 10977361
    Abstract: Systems and methods for controlling privileged operations. The system and method may comprise the steps of: providing a kernel module having a kernel authorization subsystem, the kernel module being loadable to a client computer system and configured to intercept file operations, wherein the kernel authorization subsystem may manage authorization of the one or more file operations; registering a listener for the kernel authorization subsystem; monitoring the file operations for a file access, and calling the registered listener by the kernel authorization subsystem when the kernel authorization subsystem detects the file access; calling a privileged daemon by the kernel module, when identifying the file access; and checking a policy, by the privileged daemon, and determining, based on the policy, whether at least one applied rule is applicable. If the at least one applied rule is applicable, the privileged daemon may initialize a launcher module, which may launch the target application.
    Type: Grant
    Filed: May 16, 2017
    Date of Patent: April 13, 2021
    Inventor: Andrey Kolishchak
  • Patent number: 10936316
    Abstract: Apparatus and methods are disclosed for controlling execution of memory access instructions in a block-based processor architecture using an instruction decoder that decodes instructions having variable numbers of target operands. In one example of the disclosed technology, a block-based processor core includes an instruction decoder configured to decode target operands for an instruction in an instruction block, the instruction being encoded to allow for a variable number of target operands and a control unit configured to send data for at least one of the decoded target operands for an operation performed by the at least one of the cores. In some examples, the instruction indicates target instructions with a vector encoding. In other examples, a variable length format allows for the indication of one or more targets.
    Type: Grant
    Filed: February 2, 2016
    Date of Patent: March 2, 2021
    Assignee: Microsoft Technology Licensing, LLC
    Inventors: Douglas C. Burger, Aaron L. Smith
  • Patent number: 10931301
    Abstract: A code decompression engine reads compressed code from a memory containing a series of code parts and a dictionary part. The code parts each have a bit indicating compressed or uncompressed. When the code part is compressed, it has a value indicating the number of segments, followed by the segments, followed by an index into the dictionary part. The decompressed instruction is the dictionary value specified by the index, which is modified by the segments. Each segment describes the modification to the dictionary part specified by the index by a mask type, a mask offset, and a mask.
    Type: Grant
    Filed: December 16, 2019
    Date of Patent: February 23, 2021
    Assignee: Redpine Signals, Inc.
    Inventors: Subba Reddy Kallam, Sriram Mudulodu
  • Patent number: 10917269
    Abstract: An electric system comprising communication link between a signal transmitting end and a signal receiving end, wherein, at the signal transmitting end, a number of data bits are integrated into a low frequency signal to form an integrated signal. Each data bit is transmitted as part of a symbol. Each symbol comprises a predefined number of bits encoding at least one data bit, the state of some of the bits of each symbol being dependent on the state of the low frequency symbol.
    Type: Grant
    Filed: January 17, 2017
    Date of Patent: February 9, 2021
    Assignee: VACON OY
    Inventors: Petri Ylirinne, Trygve Björkgren, Stefan Strandberg
  • Patent number: 10909259
    Abstract: An apparatus is described that includes an execution unit to execute a first instruction and a second instruction. The execution unit includes input register space to store a first data structure to be replicated when executing the first instruction and to store a second data structure to be replicated when executing the second instruction. The first and second data structures are both packed data structures. Data values of the first packed data structure are twice as large as data values of the second packed data structure. The execution unit also includes replication logic circuitry to replicate the first data structure when executing the first instruction to create a first replication data structure, and, to replicate the second data structure when executing the second data instruction to create a second replication data structure.
    Type: Grant
    Filed: September 25, 2018
    Date of Patent: February 2, 2021
    Assignee: INTEL CORPORATION
    Inventors: Elmoustapha Ould-Ahmed-Vall, Robert Valentine, Jesus Corbal, Bret L. Toll, Mark J. Charney
  • Patent number: 10884930
    Abstract: A Set Table of Contents (TOC) Register instruction. An instruction to provide a pointer to a reference data structure, such as a TOC, is obtained by a processor and executed. The executing includes determining a value for the pointer to the reference data structure, and storing the value in a location (e.g., a register) specified by the instruction.
    Type: Grant
    Filed: November 27, 2017
    Date of Patent: January 5, 2021
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Michael K. Gschwind, Valentina Salapura
  • Patent number: 10884736
    Abstract: An approach is described for a method and apparatus for a low energy programmable vector processing unit for use in processing such as for example neural network backend processing. According to some embodiments, this approach provides a pooling/vector processing unit for performing backend processing that implements a single issue multiple data (SIMD) datapath that performs various backend processing functions using only a single instruction. For instance, the present approach provides an apparatus and method for execution of operations in parallel using a single issued instruction to a plurality of processing cells. In some embodiments, there are multiple groups of processing cells for performing different operations—e.g. pooling, permute, sigmoid/tanh, and element wise operations.
    Type: Grant
    Filed: March 15, 2019
    Date of Patent: January 5, 2021
    Assignee: Cadence Design Systems, Inc.
    Inventor: Aamir Alam Farooqui
  • Patent number: 10880581
    Abstract: A better compromise between encoding complexity and achievable rate distortion ratio, and/or to achieve a better rate distortion ratio is achieved by using multitree sub-divisioning not only in order to subdivide a continuous area, namely the sample array, into leaf regions, but using the intermediate regions also to share coding parameters among the corresponding collocated leaf blocks. By this measure, coding procedures performed in tiles—leaf regions—locally, may be associated with coding parameters individually without having to, however, explicitly transmit the whole coding parameters for each leaf region separately. Rather, similarities may effectively exploited by using the multitree subdivision.
    Type: Grant
    Filed: February 27, 2020
    Date of Patent: December 29, 2020
    Assignee: GE VIDEO COMPRESSION, LLC
    Inventors: Philipp Helle, Detlev Marpe, Simon Oudin, Thomas Wiegand
  • Patent number: 10880580
    Abstract: A better compromise between encoding complexity and achievable rate distortion ratio, and/or to achieve a better rate distortion ratio is achieved by using multitree sub-divisioning not only in order to subdivide a continuous area, namely the sample array, into leaf regions, but using the intermediate regions also to share coding parameters among the corresponding collocated leaf blocks. By this measure, coding procedures performed in tiles—leaf regions—locally, may be associated with coding parameters individually without having to, however, explicitly transmit the whole coding parameters for each leaf region separately. Rather, similarities may effectively exploited by using the multitree subdivision.
    Type: Grant
    Filed: October 25, 2019
    Date of Patent: December 29, 2020
    Assignee: GE VIDEO COMPRESSION, LLC
    Inventors: Philipp Helle, Detlev Marpe, Simon Oudin, Thomas Wiegand
  • Patent number: 10863208
    Abstract: A better compromise between encoding complexity and achievable rate distortion ratio, and/or to achieve a better rate distortion ratio is achieved by using multitree sub-divisioning not only in order to subdivide a continuous area, namely the sample array, into leaf regions, but using the intermediate regions also to share coding parameters among the corresponding collocated leaf blocks. By this measure, coding procedures performed in tiles—leaf regions—locally, may be associated with coding parameters individually without having to, however, explicitly transmit the whole coding parameters for each leaf region separately. Rather, similarities may effectively exploited by using the multitree subdivision.
    Type: Grant
    Filed: June 22, 2020
    Date of Patent: December 8, 2020
    Assignee: GE VIDEO COMPRESSION, LLC
    Inventors: Philipp Helle, Detlev Marpe, Simon Oudin, Thomas Wiegand
  • Patent number: 10838720
    Abstract: Systems, methods, and apparatuses relating to multiple source blend operations are described. In one embodiment, a processor is to execute an instruction to: receive a first input operand of a first input vector, a second input operand of a second input vector, and a third input operand of a third input vector, compare each element from the first input vector to each corresponding element of the second input vector to produce a first comparison vector, compare each element from the first input vector to each corresponding element of the third input vector to produce a second comparison vector, compare each element from the second input vector to each corresponding element of the third input vector to produce a third comparison vector, determine a middle value for each element position of the input vectors from the comparison vectors, and output the middle values into same element positions in an output vector.
    Type: Grant
    Filed: September 23, 2016
    Date of Patent: November 17, 2020
    Assignee: Intel Corporation
    Inventors: Mikhail Plotnikov, Igor Ermolaev
  • Patent number: 10838866
    Abstract: A Set Table of Contents (TOC) Register instruction. An instruction to provide a pointer to a reference data structure, such as a TOC, is obtained by a processor and executed. The executing includes determining a value for the pointer to the reference data structure, and storing the value in a location (e.g., a register) specified by the instruction.
    Type: Grant
    Filed: November 27, 2017
    Date of Patent: November 17, 2020
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Michael K. Gschwind, Valentina Salapura
  • Patent number: 10812605
    Abstract: Method, and corresponding system, for establishing data communications with, and instructing, industrial machines in multiple locations. The method includes generating, using a first application, one or more machine communication messages. Each machine communication message contains data produced by one of a plurality of machines located at a first location. An instance of the first application runs on a processor of each of the plurality of machines. The method further includes sending the machine communication messages to a first message queue via a local area network. The method further includes retrieving, using a first server at a remote location connected via a network, the machine communication messages from the first message queue; and extracting from the messages, at the remote location, the data produced by the plurality of machines. The sending of the machine communication messages and the retrieving of the machine communication messages are done asynchronously.
    Type: Grant
    Filed: February 10, 2017
    Date of Patent: October 20, 2020
    Assignee: General Electric Company
    Inventors: Vrinda Rajiv, Mark Mitchell Kornfein, Christina Ann Leber
  • Patent number: 10776690
    Abstract: A neural network unit includes a register programmable with a control value, a plurality of neural processing units (NPU), and a plurality of activation function units (AFU). Each NPU includes an arithmetic logic unit (ALU) that performs arithmetic and logical operations on a sequence of operands to generate a sequence of results and an accumulator into which the ALU accumulates the sequence of results as an accumulated value. Each AFU includes a first module that performs a first function on the accumulated value to generate a first output, a second module that performs a second function on the accumulated value to generate a second output, the first function is distinct from the second function, and a multiplexer that receives the first and second outputs and selects one of the two outputs based on the control value programmed into the register.
    Type: Grant
    Filed: April 5, 2016
    Date of Patent: September 15, 2020
    Assignee: VIA ALLIANCE SEMICONDUCTOR CO., LTD.
    Inventors: G. Glenn Henry, Terry Parks
  • Patent number: 10768934
    Abstract: A data processing system supports a predicated-loop instruction that controls vectorised execution of a program loop body in respect of a plurality of vector elements. When the number of elements to be processed is not a whole number multiple of the number of lanes of processing supported for that element size, then the predicated-loop instruction controls suppression of processing in one or more lanes not required.
    Type: Grant
    Filed: March 21, 2017
    Date of Patent: September 8, 2020
    Assignee: ARM Limited
    Inventor: Thomas Christopher Grocutt
  • Patent number: 10740099
    Abstract: A machine instruction is provided that has associated therewith a result location to be used for a set operation, a first source, a second source, and an operation select field configured to specify a plurality of selectable operations. The machine instruction is executed, which includes obtaining the first source, the second source, and a selected operation, and performing the selected operation on the first source and the second source to obtain a result in one data type. That result is quantized to a value in a different data type, and the value is placed in the result location.
    Type: Grant
    Filed: November 14, 2015
    Date of Patent: August 11, 2020
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Michael K. Gschwind, Brett Olsson
  • Patent number: 10721496
    Abstract: A better compromise between encoding complexity and achievable rate distortion ratio, and/or to achieve a better rate distortion ratio is achieved by using multitree sub-divisioning not only in order to subdivide a continuous area, namely the sample array, into leaf regions, but using the intermediate regions also to share coding parameters among the corresponding collocated leaf blocks. By this measure, coding procedures performed in tiles—leaf regions—locally, may be associated with coding parameters individually without having to, however, explicitly transmit the whole coding parameters for each leaf region separately. Rather, similarities may effectively exploited by using the multitree subdivision.
    Type: Grant
    Filed: September 23, 2019
    Date of Patent: July 21, 2020
    Assignee: GE VIDEO COMPRESSION, LLC
    Inventors: Philipp Helle, Detlev Marpe, Simon Oudin, Thomas Wiegand
  • Patent number: 10687088
    Abstract: A better compromise between encoding complexity and achievable rate distortion ratio, and/or to achieve a better rate distortion ratio is achieved by using multitree sub-divisioning not only in order to subdivide a continuous area, namely the sample array, into leaf regions, but using the intermediate regions also to share coding parameters among the corresponding collocated leaf blocks. By this measure, coding procedures performed in tiles—leaf regions—locally, may be associated with coding parameters individually without having to, however, explicitly transmit the whole coding parameters for each leaf region separately. Rather, similarities may effectively exploited by using the multitree subdivision.
    Type: Grant
    Filed: September 23, 2019
    Date of Patent: June 16, 2020
    Assignee: GE VIDEO COMPRESSION, LLC
    Inventors: Philipp Helle, Detlev Marpe, Simon Oudin, Thomas Wiegand
  • Patent number: 10678864
    Abstract: An analysis model execution unit executing a part of an analysis model, an analysis model partial execution unit partially executing the analysis model based on intermediate data generated during execution of the analysis model, external storage storing the intermediate data and mapping information which is corresponding relationship between the intermediate data and the analysis model, and an analysis model general processing unit generating the mapping information by associating the intermediate data with the analysis model and reading the intermediate data associated with the analysis model from the external storage based on the mapping information are provided.
    Type: Grant
    Filed: September 19, 2018
    Date of Patent: June 9, 2020
    Assignee: HITACHI, LTD.
    Inventors: Takaya Ide, Hiroshi Nasu, Yuki Naganuma, Toshio Nishida, Hideki Nakamura
  • Patent number: 10671390
    Abstract: A conditional instruction end facility is provided that allows completion of an instruction to be delayed. In executing the machine instruction, an operand is obtained, and a determination is made as to whether the operand has a predetermined relationship with respect to a value. Based on determining that the operand does not have the predetermined relationship with respect to the value, the obtaining and the determining are repeated. Based on determining that the operand has the predetermined relationship with respect to the value, execution of the instruction is completed.
    Type: Grant
    Filed: January 13, 2017
    Date of Patent: June 2, 2020
    Assignee: INTERNATIONAL BUSINESS MACHINES
    Inventors: Dan F. Greiner, Christian Jacobi, Marcel Mitran, Donald W. Schmidt, Timothy J. Slegel
  • Patent number: 10664273
    Abstract: An apparatus and method for processing efficient multicast operation.
    Type: Grant
    Filed: March 30, 2018
    Date of Patent: May 26, 2020
    Assignee: Intel Corporation
    Inventors: Christopher J. Hughes, Dan Baum
  • Patent number: 10666288
    Abstract: Detailed herein are embodiments of systems, methods, and apparatuses for decompression using hardware and software. In hardware, an input buffer stores incoming input records from a compressed stream. A plurality of decoders decode at least one input record from the input buffer out output an intermediate record from the decoded data and a subset of the plurality of decoders to output a stream of literals. Finally, a reformat circuit formats an intermediate record into one of two types of tokens.
    Type: Grant
    Filed: November 20, 2018
    Date of Patent: May 26, 2020
    Assignee: Intel Corporation
    Inventors: Vinodh Gopal, James D. Guilford, Sean M. Gulley, Kirk S. Yap
  • Patent number: 10606797
    Abstract: A system and method for automated data propagation and automated data processing within an integrated circuit includes an intelligence processing integrated circuit comprising at least one intelligence processing pipeline, wherein the at least one intelligence processing pipeline includes: a main data buffer that stores input data; a plurality of distinct intelligence processing tiles, wherein each distinct intelligence processing tile includes a computing circuit and a local data buffer; a token-based governance module, the token-based governance module implementing: a first token-based control data structure; a second token-based control data structure, wherein the first token-based control data structure and the second-token based control data operate in cooperation to control an automated flow of the input data and/or an automated processing of the input data through the at least one intelligence processing pipeline.
    Type: Grant
    Filed: July 1, 2019
    Date of Patent: March 31, 2020
    Assignee: Mythic, Inc.
    Inventors: David Fick, Malav Parikh, Paul Toth, Adam Caughron, Vimal Reddy, Erik Schlanger, Sergio Schuler, Zainab Nasreen Zaidi, Alex Dang-Tran, Raul Garibay, Bryant Sorensen
  • Patent number: 10592468
    Abstract: Techniques are described to perform a shuffle operation. Rather than using an all-lane to all-lane cross bar, a shuffler circuit having a smaller cross bar is described. The shuffler circuit performs the shuffle operation piecewise by reordering data received from processing lanes and outputting the reordered data.
    Type: Grant
    Filed: July 13, 2016
    Date of Patent: March 17, 2020
    Assignee: QUALCOMM Incorporated
    Inventors: Liang Han, Xiangdong Jin, Lin Chen, Yun Du, Alexei Vladimirovich Bourd
  • Patent number: 10579124
    Abstract: A method for controlling powering of a mobile platform comprising a first Finite State Machine (FSM) and a second FSM. The method comprises synchronizing the first FSM with the second FSM, wherein the first FSM is arranged on a first Integrated Circuit (IC) comprised in the mobile platform and configured to control a first Power Management Unit (PMU) arranged on the first IC, and wherein the second FSM is arranged on a second IC comprised in the mobile platform and configured to control a second PMU arranged on the second IC, whereby the first PMU and the second PMU are synchronized to operate simultaneously during rank-up and rank-down, thereby providing power control of the mobile platform.
    Type: Grant
    Filed: February 22, 2018
    Date of Patent: March 3, 2020
    Assignee: TELEFONAKTIEBOLAGET LM ERICSSON (PUBL)
    Inventors: Olli Varkki, Harri Eksymä, Marko Pessa
  • Patent number: 10521582
    Abstract: An access management robot facilitation system facilitates a robot to execute access management tasks on a target system.
    Type: Grant
    Filed: October 19, 2017
    Date of Patent: December 31, 2019
    Assignee: ACCENTURE GLOBAL SOLUTIONS LIMITED
    Inventors: Sanjeev Shukla, Gaurav Tandon, Rexall E. Thexton, Neha Joshi, David Michael Parker, Avinash Ramesh, Krishna M. Dasari, Parvathy Ramakrishnan
  • Patent number: 10521239
    Abstract: A method for accelerating code optimization a microprocessor. The method includes fetching an incoming microinstruction sequence using an instruction fetch component and transferring the fetched macroinstructions to a decoding component for decoding into microinstructions. Optimization processing is performed by reordering the microinstruction sequence into an optimized microinstruction sequence comprising a plurality of dependent code groups. The optimized microinstruction sequence is output to a microprocessor pipeline for execution. A copy of the optimized microinstruction sequence is stored into a sequence cache for subsequent use upon a subsequent hit optimized microinstruction sequence.
    Type: Grant
    Filed: October 3, 2016
    Date of Patent: December 31, 2019
    Assignee: INTEL CORPORATION
    Inventor: Mohammad Abdallah
  • Patent number: 10447823
    Abstract: A packet parsing engine comprises a DMEM configured to store packet data; one or more registers configured to store parsing instructions or parse results; and one or more arithmetic logic units configured to parse the packet data based on the parsing instructions and to derive the parse results. The engine may be one engine of a plurality of engines configured to access a shared memory, and the engine may be configured to receive data from the shared memory or to send data to the shared memory. The DMEM may be divided into subsections, and at least one of the one or more registers may be divided into subsections, and the subsections may be configured such that while a DMEM subsection and its corresponding register subsection is parsing packet data for a first packet, one or more other subsections load packed data or unload parse results for a second packet.
    Type: Grant
    Filed: January 8, 2014
    Date of Patent: October 15, 2019
    Assignee: Marvell Semiconductor, Inc.
    Inventors: Wilson Parkhurst Snyder, II, Daniel Adam Katz, Varada Ramesh Ogale
  • Patent number: 10416912
    Abstract: A chip select training mode (CSTM) enables a memory subsystem to train a chip select signal separately from command bus training. A memory device and a memory controller can connect via a command bus including a chip select signal line. Instead of training the chip select along with other signal lines of the command bus, a CSTM mode enables the memory subsystem to more accurately train the chip select. The memory device can be triggered for CSTM mode with a command, and then train voltage margining for the CS signal line to align chip select signaling with the memory subsystem clock signal.
    Type: Grant
    Filed: September 29, 2017
    Date of Patent: September 17, 2019
    Assignee: Intel Corporation
    Inventors: Tonia G. Morris, Christopher P. Mozak, Christopher E. Cox
  • Patent number: 10409815
    Abstract: A system comprises generation of a parse tree comprising a plurality of query parse nodes, each of the plurality of query parse nodes corresponding to a respective one of a plurality of portions of a script definition, generation of a first intermediate representation tree comprising an intermediate representation node corresponding to a respective one of each of the plurality of query parse nodes, wherein an intermediate representation node represents a logical operation corresponding to the portion of the script definition of the query parse node which corresponds to the intermediate representation node, definition of links between each of the plurality of query parse nodes and its corresponding the intermediate representation node, determination of a second intermediate representation tree, the second intermediate representation tree resulting from an optimizer transformation executed on the first intermediate representation tree, generation of an intermediate representation node corresponding to a transfo
    Type: Grant
    Filed: June 14, 2017
    Date of Patent: September 10, 2019
    Assignee: SAP SE
    Inventors: Chanho Jeong, Jaeha Lee
  • Patent number: 10303525
    Abstract: Systems, methods, and apparatuses for data speculation execution (DSX) are described. In some embodiments, a hardware apparatus for performing DSX comprises a hardware decoder to decode an instruction, the instruction to include an opcode and an operand to store a portion of a fallback address, execution hardware to execute the decoded instruction to initiate a data speculative execution (DSX) region by activating DSX tracking hardware to track speculative memory accesses and detect ordering violations in the DSX region, and storing the fallback address.
    Type: Grant
    Filed: December 24, 2014
    Date of Patent: May 28, 2019
    Assignee: Intel Corporation
    Inventors: Elmoustapha Ould-Ahmed-Vall, Christopher J. Hughes, Robert Valentine, Milind B. Girkar, Hideki Ido, Youfeng Wu, Cheng Wang
  • Patent number: 10296489
    Abstract: A processor including a first vector register for storing a plurality of source data elements, a second vector register for storing a plurality of control elements, and a vector bit shuffle logic. Each of the control elements in the first vector register corresponds to a different source data element and includes a plurality of bit fields. Each of the bit fields is associated with a single corresponding bit position in a destination mask register and identifies a single bit from the corresponding source data element to be copied to the single corresponding bit position in the destination mask register. The vector bit shuffle logic is to read the bit fields from the second vector register and, for each bit field, to identify a single bit from a single corresponding source data element and copy it to a single corresponding bit position in the destination mask register.
    Type: Grant
    Filed: December 27, 2014
    Date of Patent: May 21, 2019
    Assignee: Intel Corporation
    Inventors: Elmoustapha Ould-Ahmed-Vall, Jesus Corbal San Adrian, Robert Valentine, Mark J. Charney, Guillem Sole, Roger Espasa
  • Patent number: 10235174
    Abstract: A conditional instruction end facility is provided that allows completion of an instruction to be delayed. In executing the machine instruction, an operand is obtained, and a determination is made as to whether the operand has a predetermined relationship with respect to a value. Based on determining that the operand does not have the predetermined relationship with respect to the value, the obtaining and the determining are repeated. Based on determining that the operand has the predetermined relationship with respect to the value, execution of the instruction is completed.
    Type: Grant
    Filed: January 30, 2017
    Date of Patent: March 19, 2019
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Dan F. Greiner, Christian Jacobi, Marcel Mitran, Donald W. Schmidt, Timothy J. Slegel
  • Patent number: 10201760
    Abstract: A system and method are described below for encoding interactive low-latency video using interframe coding. For example, one embodiment of a computer-implemented method for performing video compression comprises: logically subdividing each of a sequence of images into a plurality of tiles, each of the tiles having a defined position within each of the sequence of images, the defined position remaining the same between successive images; detecting motion within the sequence of images occurring at each of the positions of each of the tiles; and encoding each tile within each image of the sequence of images using a first compression format or a second compression format, wherein the frequency at which a particular tile is encoded according to the first compression format across the sequence of images is based on the detected amount of motion at the position of that tile across the sequence of images.
    Type: Grant
    Filed: January 23, 2009
    Date of Patent: February 12, 2019
    Assignee: Sony Interactive Entertainment America LLC
    Inventors: Roger van der Laan, Stephen G. Perlman