Abstract: A method for controlling communication. The method sends a first instruction from a first processor to a first device via a processor bus in electrical communication with a first bus, sends a control signal from the first processor to a selector, the selector switching electrical communication at least one signal line of the processor bus from the first bus to a second bus, sends a second instruction from the first processor to a second device, sends a control signal from the first processor to the selector, the selector switching electrical communication of the at least one signal line of the processor bus from the second bus to the first bus, and sends data from the first device to the first processor.

Abstract: A static schedule is selected from a set of static schedules for an application dependent on the state of the application. A scheduling system stores a set of pre-defined static schedules for each state of the application. A scheduling system learns the costs of predefined schedules for each state of the application on-line as the application executes. Upon the detection of a state change in the application during run-time, the scheduling system selects a new static schedule for the application. The new static schedule is determined based on schedule costs and exploration criteria.

Abstract: A processor having select-free scheduling separates the wakeup and select logic into two loops. A wakeup loop holds scheduler instructions including unexecuted instructions, and indicates which of the unexecuted instructions may be ready to be executed. At least one of the unexecuted instructions is to wakeup and notify at least another of the unexecuted instructions to speculatively wakeup. A select loop selects at least one of the indicated ready instructions for execution.

Abstract: An apparatus and method in a microprocessor having two unaligned functional unit pipelines which enables an instruction queue for the second pipeline to be placed at an intermediate pipeline stage rather than after the stage in the first pipeline that retires instructions. The apparatus maintains coherency between the status of each instruction in the queue relative to its status in the first pipeline. The status comprises an age of the instruction and a valid bit. The age specifies the stage in the first pipeline in which the instruction resides. The apparatus includes logic for updating the age and valid bit based on whether the first pipeline is stalled, on valid bits from the first pipeline, and on whether the queue is downshifting. The microprocessor selectively updates its user-visible state with the instruction execution results from the second functional unit based on the instruction age and valid bit.

Abstract: A high-performance, superscalar-based computer system with out-of-order instruction execution for enhanced resource utilization and performance throughput. The computer system fetches a plurality of fixed length instructions with a specified, sequential program order (in-order). The computer system includes an instruction execution unit including a register file, a plurality of functional units, and an instruction control unit for examining the instructions and scheduling the instructions for out-of-order execution by the functional units. The register file includes a set of temporary data registers that are utilized by the instruction execution control unit to receive data results generated by the functional units. The data results of each executed instruction are stored in the temporary data registers until all prior instructions have been executed, thereby retiring the executed instruction in-order.

Abstract: After an instruction loads data into a register at a first time, the register is monitored to see if it is read in a next clock cycle. When the data is not read in the next clock cycle, the instruction is classified as a slowable instruction. An instruction address associated with the instruction is used to update a history table. The history table stores information to indicate if an instruction is a slowable instruction or a non-slowable instruction. When the instruction address of the instruction is encountered at a second time, the history table is used to determine if the instruction is slowable or non-slowable.

Abstract: An integrated circuit that uses a functional unit that outputs one set of values when in a power saving mode is provided. The functional unit, generally pipelined, is capable of being in the power saving mode dependent on an instruction decode/issue unit, and when in the power saving mode, the functional unit, using power saving mode circuitry, outputs one set of values as seen by components external to the functional unit regardless of the state the functional unit is in when the functional unit is initially put in the power saving mode.

Abstract: A system and method of managing processor instructions provides enhanced performance. The system and method provide for decoding a first instruction into a plurality of operations with a decoder. A first copy of the operations is passed from the decoder to a build engine associated with a trace cache. The system and method further provide for passing a second copy of the operation from the decoder directly to a back end allocation module such that the operations bypass the build engine and the allocation module is in a decoder reading state.

Abstract: A functional unit of a processor may be configured to operate on instructions as either a single, wide functional unit or as multiple, independent narrower units. For example, an execution unit may be scheduled to execute an instruction as a single double-wide execution unit or as two independently schedulable single-wide execution units. Functional unit portions may be independently schedulable for execution of instructions operating on a first data type (e.g. SISD instructions). For single-wide instructions, functional unit portions may be scheduled independently. An issue lock mechanism may lock functional unit portions together so that they form a single multi-wide functional unit. For certain multi-wide instructions (e.g. certain SIMD instructions), an instruction operating on a multi-wide or vector data type may be scheduled so that the full multi-wide operation is performed concurrently by functional unit portions locked together as a one wide functional unit.

Abstract: A modified AV/C command set includes status inquiry, notify inquiry and control inquiry commands. The status inquiry, notify inquiry and control inquiry commands include an opcode and any number of operands. Thus, the status inquiry, notify inquiry and control inquiry commands can include only an opcode. The status inquiry, notify inquiry and control inquiry commands are sent from a controller to a target device to determine if the target device supports a particular status, notify or control command, respectively. In response to a status inquiry, notify inquiry or control inquiry command, a target device sends a response to the controller notifying the controller as to whether or not the target device supports the particular command.

Abstract: One embodiment of the present invention provides a system that reduces the time required to access registers from a register file within a processor. During operation, the system receives an instruction to be executed, wherein the instruction identifies at least one operand to be accessed from the register file. Next, the system looks up the operands in a register pane, wherein the register pane is smaller and faster than the register file and contains copies of a subset of registers from the register file. If the lookup is successful, the system retrieves the operands from the register pane to execute the instruction. Otherwise, if the lookup is not successful, the system retrieves the operands from the register file, and stores the operands into the register pane. This triggers the system to reissue the instruction to be executed again, so that the re-issued instruction retrieves the operands from the register pane.

Abstract: A method and apparatus to execute data speculative instructions in a processor comprising at least one source register, each source register comprising a bit to indicate validity of data in the at least one source register. A data validity circuit coupled to the one or more source registers to determine the validity of the data in the source registers, and to indicate the validity of the data in a destination register based upon the validity bit in the at least one source register. The processor optionally comprising a checker unit to retire those instructions from the execution unit which write valid data to the destination register, and to re-schedules those instructions for execution which write invalid data to the destination register.

Abstract: A method of processing data relating to graphical primitives to be displayed on a display device using region-based SIMD multiprocessor architecture, has the shading and blending operations deferred until rasterization of the available graphical primitive data is completed.

Abstract: A system and method of processing a predicated instruction is disclosed. A consumer instruction and a predicated instruction are received in an reservation station of an out-order processor. The consumer instruction depends on a result of the predicated instruction. The predicated instruction is dispatched to an execution unit for execution. The executed predicate instruction is stored in a re-order buffer.

Abstract: A microprocessor to reduce wasteful power consumption of the floating-point unit. An instruction invalidation logic circuit is utilized to substitute the instruction not-to-use-the-floating-point unit, in the instruction string supplied from the instruction cache, with an invalidating instruction, hold that invalidating instruction in the floating-point register, and supply that invalidating instruction to a floating-point decoder in the floating-point unit. In cases when the invalidating instruction was continuous, the power consumption in the floating-point data path as well as the in the floating-point decoder and floating-point register is reduced.

Abstract: Rescheduling multiple micro-operations in a processor using a replay queue. The processor comprises a replay queue to receive a plurality of instructions and an execution unit to execute the plurality of instructions. A scheduler is coupled between the replay queue and the execution unit. The scheduler speculatively schedules instructions for execution and dispatches each instruction to the execution unit. A checker is coupled to the execution unit to determine whether each instruction has executed successfully. The checker is also coupled to the replay queue to communicate to the replay queue each instruction that has not executed successfully.

Abstract: A processing system that executes multiple instruction contexts includes an instruction memory for storing instructions that are executed by the system, a processor unit executing the instructions in a pipelined fashion, a plurality of context registers for storing instructions and instruction addresses for contexts to be executed and fetch logic for selecting an address from one of the context registers and for selecting an instruction from a second of the context registers for execution substantially simultaneously for each cycle of execution of processor unit.

Abstract: A system may include a scheduler and an execution core. The scheduler includes an entry allocated to an operation. The entry includes a non-speculative tag and a speculative tag, and both the non-speculative tag and the speculative tag are associated with a first operand of the operation. The scheduler is configured to issue the operation in response to a data value identified by the speculative tag being available. The execution core may be configured to execute the operation using the data value identified by the speculative tag. The scheduler may be configured to reissue the operation if the non-speculative tag appears on a result bus.

Abstract: A multiprocessor data processing system includes first and second processors coupled to an interconnect and to a global promotion facility containing a plurality of promotion bit fields. The first processor executes a single acquisition instruction to concurrently acquire a plurality of promotion bit fields exclusive of at least the second processor. In response to execution of the acquisition instruction, the first processor receives an indication of success or failure of the acquisition instruction, wherein the indication indicates success of the acquisition instruction if all of the plurality of promotion bit fields were concurrently acquired by the first processor and indicates failure of the acquisition instruction if fewer than all of the plurality of promotion bit fields were acquired by the first processor.

Abstract: A method and apparatus for improving instruction level parallelism across VLIW traces. Traces are statically grouped into VLIWs and dependency timing data is determined. VLIW traces are compared dynamically to determine data dependencies between consecutive traces. The dynamic comparison of dependency data determines the timing of execution for subsequent traces to maximize parallel execution of consecutive traces.

Abstract: A command processing device includes first and second storing circuits, a decode circuit and a generating circuit. The first storing circuit stores a command. The decode circuit decodes the command from the first storing circuit and outputs a decoded command and a control signal. The generating circuit receives the command from the first storing circuit, generates a new command in response to the control signal, and outputs the new command to the first generating circuit. The second storing circuit stores an original command. The generating circuit receives the original command from the second storing circuit and outputs the original command to the first storing circuit.

Abstract: An apparatus is described comprising a signal indicative of which of a plurality of data structures stored in a queue desire to issue from the queue. The apparatus also has a content addressable memory having a plurality of cells, where each of the cells is configured to store one of the data structures. The apparatus also has an output from at least one of the cells that is indicative of whether the data structure within the at least one of the cells has issued from the queue. The apparatus also has an input to the at least one of the cells coupled to the signal.

Abstract: A system and method for improved branch performance in pipelined computer architectures is presented. Priority bits are set during code execution that corresponds to an upcoming branch instruction. A priority bit may be associated with a register, a resource, or a microsequencer. An instruction selector compares one or more priority bits with each of a plurality of instructions in order to identify particular instructions to execute that make registers and resources available for an upcoming branch instruction. The instruction selector then prioritizes the identified instructions and the pipeline executes in instructions in the prioritized order.

Abstract: A branch control apparatus in a microprocessor. The branch control apparatus includes an instruction buffer having a plurality of stages that buffer cache lines of instruction bytes received from an instruction cache. A multiplexer selects one of the bottom three stages in the instruction buffer to provide to instruction format logic. The multiplexer selects a stage based on a branch indicator, an instruction wrap indicator, and a carry indicator. The branch indicator indicates whether the processor previously branched to a target address provided by a branch target address cache. The branch indicator and target address are previously stored in association with the stage containing the branch instruction for which the target address is cached. The wrap indicator indicates whether the currently formatted instruction wraps across two cache lines. The carry indicator indicates whether the current instruction being formatted occupies the last byte of the currently formatted instruction buffer stage.

Abstract: An integrated circuit having a plurality of execution units each of which has a corresponding parallel execution unit. Each one of the parallel execution units has substantially the same functionality as its corresponding execution unit. Each parallel execution unit has greater latency but uses less power than its corresponding execution unit.

Abstract: For use in an instruction queue having a plurality of instruction slots, a mechanism for queueing and retiring instructions. In one embodiment, the mechanism includes a plurality of tag fields corresponding to the plurality of instruction slots, and control logic, coupled to the tag fields, that assigns tags to the tag fields to denote an order of instructions in the instruction slots. In addition, the mechanism includes a tag multiplexer, coupled to the control logic, that changes the order by reassigning only the tags.

Abstract: According to some embodiments, stall optimization is provided for a processor pipeline.

Abstract: A data processing control system has a controller wherein the controller (1) sends every received instruction to the plurality of data processing devices until the number of instructions being executed or waiting to be executed by the plurality of data processing devices reaches a predetermined number, (2) does not send any received instructions to the plurality of data processing devices but holds the received instructions in a queue once the number of instructions being executed or waiting to be executed by the plurality of data processing devices has reached the predetermined number, and (3) when the number of instructions being executed or waiting to be executed by the plurality of data processing devices has become zero by completing the execution thereof, starts sending the queued instructions in sequence to the plurality of data processing devices, and continues to send the queued instructions or every newly received instruction to the plurality of data processing devices until the number of instructio

Abstract: A unified buffer, comprising a shifting queue, receives instructions to be tracked by receiving units in a computer architecture. The receiving units search the unified buffer from the oldest entry to the most recent entry. Status bits in each entry indicate which of the receiving unit(s) the entry is destined for. Existing entries in the unified buffer shift down when a new entry is inserted at the top. Entries may be passed to different receiving units by updating the status bits; and an entry expires after it has been accepted by its final receiving unit.

Abstract: The present application describes a method and a system for facilitating atomicity of complex instructions in processor execution of helper instruction. Atomic complex instructions are handled by stalling the fetching of instruction upon recognizing atomic instruction in a group of fetched instructions. Complex atomic instructions are expanded into helper instructions before execution (e.g., in the integer, floating point, graphics and memory units or the like). Stalling the fetching facilitates the execution and completion of corresponding helper instructions and maintains the atomicity of the complex instruction.

Abstract: Methods and systems are disclosed for indicating microprocessor resources are limited. One method subtracts a current value of a pointer from a maximum value of the pointer and compares to a desired value. A stall is asserted when the desired value is achieved. Another method advances instructions along a pipeline, with the pipeline having a minimum amount of open space. The minimum amount of open space is subtracted from a current amount of open space within the pipeline, and this result is compared to a desired value. A stall is asserted when the desired value is achieved.

Abstract: A multi-issue microprocessor selectively assigns, with particular emphasis on an particular type of instruction, in a plurality of instructions to various pipelines. The microprocessor maintains counts of the number of instructions assigned to a first pipeline and a second pipeline. Depending on these counts, the processor assigns instructions of the particular type in the plurality of instructions to the first and second pipelines.

Abstract: A shared memory type vector processing system in which CPUs are connected by a bus for transferring a vector processing instruction generated from any of the CPUs to each of the CPUs, and the respective CPUs are grouped into a master CPU which issues a vector processing instruction to other CPUs and slave CPUs operating as a multi-vector pipeline in synchronization with a vector processing unit in the master CPU, the master CPU including a memory access control unit for issuing said vector processing instruction with issuing source CPU information attached for identifying an issuing source CPU, and transferring said instruction to all the CPUs including its own CPU through a bus, and the master CPU and the slave CPU including a vector processing instruction control unit for comparing issuing source CPU information contained in a vector processing instruction and master CPU information set at its own CPU and conducting instruction issuance based on the vector processing instruction when the information accord

Abstract: A method and apparatus to allow program steps in an issue queue to be sent to the execution queue in a non program order provides reduced stall by allowing out of program order steps to be executed as needed resources become available. The method uses a modulus operation to preassign locations in the execution queues, and keep the entries in proper program order. The method employs an additional bit to represent the modules result (value) and may also utilize a load store number mapping memory to increase execution speed. With such an arrangement a computer system may decrease the lost performance due to waiting for required resource (i.e., memory or bus) availability for the current instruction, by issuing instructions for which the memory or bus resource is available even though the instruction is not the next one in the original program order. Thus the present invention allows memory reference instructions to issue as resources are available.

Abstract: In each processor of a plurality of processors provided in one chip, an instruction to be executed by an instruction code inputted thereto is to be determined uniquely, based on input history of the instruction codes, from the plural instructions assigned to the instruction codes by an decoder circuit. Accordingly, every instruction can be expressed by a short instruction code length, with one instruction code corresponding to the plural instructions, as well as different kinds of instructions can be executed, based on the input history of the instruction codes, by the same instruction code.

Abstract: The present invention relates to an instruction control device, and more particularly to an instruction control device which has achieved a high speed operational processing, such as a reduction in the amount of components, so as to enable an out-of-order instruction execution to thereby execute an instruction processing at high speed in an information processor.

Abstract: The present invention relates to an instruction control device, and more particularly to an instruction control device which has achieved a high speed operational processing, such as a reduction in the amount of components, so as to enable an out-of-order instruction execution to thereby execute an instruction processing at high speed in an information processor.

Abstract: A system for handling a plurality of single precision floating point instructions and a plurality of double precision floating point instructions that both index a same set of registers is provided. The system comprises a decode unit arranged to decode, stall, and forward at least one of the plurality of single precision and at least one of the plurality of double precision floating point instructions in a fetch group. The decode unit includes a first counter arranged to increment for each of the plurality of single precision floating point instructions forwarded down a pipeline; a second counter arranged to increment for each of the plurality of double precision floating point instructions forwarded down the pipeline; a first mask register and a second mask register. The first mask register is updated by each of the single precision floating point instructions forwarded and the second mask register is updated by each of the double precision floating point instructions forwarded.

Abstract: An apparatus, system and method for quickly determining an oldest instruction in a non-moving instruction queue of a processor are provided. Particularly, instructions are stored, one at a time at a clock cycle, in the non-moving queue. At every clock cycle, a present status of the instructions in the queue is recorded. Using the present status of the instructions in the queue in conjunction with previously recorded statuses of the instructions, the oldest instruction in the queue is determined. The status of the instructions in the queue includes whether or not the instruction has been issued for execution as well as whether or not it is known that the issued instruction has been accepted for execution.

Abstract: A “data verified”, or DV, bit is included in an instruction to indicate if the instruction or a dependent instruction may be associated with the retrieved data as soon as the data is available or should instead be associated with the data after verification. If the DV bit is in a first state, e.g., not set, the system may issue instructions that use associated data as soon as the data is available. If the DV bit is in a second state, e.g., set, the system does not issue the instructions that use the data until the data is verified. The system or user sets the DV bit based on an analysis of an instruction set that includes the instruction and/or accumulated profile data from previous use or uses of the software. The DV bit is set in a LOAD instruction if the dependent user instruction is close enough in the instruction set that the user instruction is likely to issue before the data is verified and/or if the LOAD instruction is part of a relatively long chain of instructions.

Abstract: An instruction issuing device comprises a plurality of issue controlling circuits which run in parallel, and perform a control for preferentially issuing an instruction to a particular arithmetic unit. An optimum issue controlling circuit is selected according to the empty quantity of instruction slots for each arithmetic unit or a result of learning of the number of previously issued instructions, and an issue destination is determined based on the direction of the selected circuit.

Abstract: A system and method of allocating register file read ports provides for mapping different-sized register file read ports to a plurality of micro-operation (uop) source fields. One approach involves mapping a first read port of a register file to a first uop source field for a particular read cycle. A second read port is mapped to a second uop source field for the read cycle, where the first and second read ports have a first size. A third read port is mapped to a third uop source field for the read cycle, where the third read port has a second size. Mapping the third read port accommodates for the use of fused uops, which have data relating to multiple operations. Furthermore, the second size can be less than the first size in order to minimize the impact on die area and circuit speed paths.

Abstract: A method and apparatus are provided for providing ready information to a scheduler. Dependence information is maintained in a relatively small map table, with potential loss of information when dependence information exceeds available space in the map table. Ready instructions are maintained, as space allows, in a select queue. Tags for scheduled instructions are maintained in a lookup queue, and dependency information for the scheduled instruction is maintained in an update queue, as space allows. Ready information for instructions in a scheduling window is updated based upon the information in the update queue. Loss of instruction information may occur, due to space limitations, at the map table, lookup queue, update queue, and/or select queue. Scheduling of lost instructions is handled by a lossy instruction handler.

Abstract: A method and apparatus for the elimination of prolog and epilog instructions in a vector processor. To eliminate the prolog, a functional unit of the vector processor has at least one input for receiving an input data value tagged with a data validity tag and an output for outputting an intermediate result tagged with a data validity tag. The data validity tags indicate the validity of the data. Before a loop is executed, the data validity tags are set to indicate that the associated data values are invalid. During execution of the loop body a functional unit checks the validity of input data. If all of the input data values are valid the functional operation is performed, the corresponding data validity tag set to indicate that the result is valid. If any of the input data values is invalid, the data validity tag of the result is set to indicate that the result is invalid. To eliminate the epilog, an iteration counter is associated with each sink unit of the vector processor.

Abstract: Mapping circuitry (40) comprises a first candidate output value producing unit (42) which produces a first candidate output value (C1) that differs by a first offset value (x) from a received input value (r). During operation of the first candidate output value producing unit (42) a second candidate output value producing unit (44) produces a second candidate output value (C2) that differs by a second offset value (y) from the received input value (r). One of the first and second candidate output values is within a preselected range of allowable output values and the other is outside that range. An in-range value determining unit (46) determines which one of the first and second candidate output values is within the range, and an output value selection unit (48) selects this value as the output value (p) corresponding to the received input value (r).

Abstract: Disclosed is a processor, which reduces issuing of unnecessary barrier operations during instruction processing. The processor comprises an instruction sequencing unit and a load store unit (LSU) that issues a group of memory access requests that precede a barrier instruction in an instruction sequence. The processor also includes a controller, which in response to a determination that all of the memory access requests hit in a cache affiliated with the processor, withholds issuing on an interconnect a barrier operation associated with the barrier instruction. The controller further directs the load store unit to ignore the barrier instruction and complete processing of a next group of memory access requests following the barrier instruction in the instruction sequence without receiving an acknowledgment.

Abstract: A computer system has a communication link that includes a control signal and data lines. A first control packet having a-plurality of bytes is transferred over the data lines from a first to a second node on the communication link. The control line is asserted to indicate transfer of a control packet. After transfer of the first control packet, a first portion of a multi-byte data packet associated with the first control packet is transferred with the control line deasserted. During transfer of the data packet the control line is asserted and transfer of the data packet is suspended. A second control packet is then transferred over the data lines. Subsequent to transferring the second control packet, the remainder of the data packet is transferred with the control line deasserted.

Abstract: An instruction pipeline in a microprocessor, comprising a plurality of pipeline units with each of the pipeline units processing instructions. At least one of the plurality of pipeline units receives the instructions from another of the pipeline units, stores the instructions and reissues at least one of the instructions after a stall occurs in the instruction pipeline.

Abstract: A method of compacting an instruction queue in an out of order processor includes determining the number of invalid instructions below and including each row in the queue, by counting invalid bits or validity indicators associated with rows below and up to the current row. For each row, multiplexor select signals are generated from the flat vector counts for the N rows above and including the present row, and from the validity indicators associated with the N rows, where N is a predetermined value. A multiplexor associated with a particular row selects one of the N rows according to the select value, and moves or passes the instruction held in the selected row to the present row. A row's select value is determined by forming a diagonal from the N count vectors corresponding to the N rows above and including the present row, and logically ANDing, each diagonal bit with the valid bit associated with the same row. Each row's count vector is determined in two stages.

Abstract: A method and apparatus to allow program steps in an issue queue to be sent to the execution queue in a non program order provides reduced stall by allowing out of program order steps to be executed as needed resources become available. The method uses a modulus operation to preassign locations in the execution queues, and keep the entries in proper program order. The method employs an additional bit to represent the modules result (valve) and may also utilize a load store number mapping memory to increase execution speed. With such an arrangement a computer system may decrease the lost performance due to waiting for required resource (i.e., memory or bus) availability for the current instruction, by issuing instructions for which the memory or bus resource is available even though the instruction is not the next one in the original program order. Thus the present invention allows memory reference instructions to issue as resources are available.