Abstract: A system and method for determining an age function by performing a logical function on each entry residing within a queue, determining when a particular one of the entries residing in the queue was stored in the queue relative to the other entries, and determining an oldest or youngest entry residing in the queue relative to the logical functions performed on each of the instructions. In one embodiment of the present invention, the entries are instructions temporarily stored within a queue in the processor. The logical function performed may determine which of the instructions is valid. The queue may be cyclical.

Abstract: Instruction issue logic is disclosed that assesses register availability. The issue logic comprises register scoreboard logic that includes destination register storage elements to identify destination registers of instructions queued for issue. An arbiter selects instructions for issue during a machine cycle from the queued instructions. Register-clean wires associated with each register are driven in response to the corresponding destination storage elements and the arbiter. These wires are used to identify the read-availability of registers. Specifically, such a logic system is capable of reflecting freed registers on the subsequent machine cycle so that previously issued instructions do not hinder queuing of new instructions, unless they require multiple cycles to complete. To increase speed of operation, single NMOS devices bridge the register-clean wires and the issue signal from the arbiter.

Abstract: An event notification system for a network including a managed device that includes one or more management agents that detect one or more management events of a plurality of possible management events. The managed device further includes event notification logic that generates an event notification message (ENM) which includes event related information. The ENM is written using a markup language, such as XML, to encode the event related information based on the management event. The ENM may include executable code written in a scripting language or the like, that when executed, causes at least one action to be performed. A management server is provided that includes an event processor that executes the code to perform the desired actions in response to the particular management event. The event related information may further include a URL to locate one or more information files in the network that provides further information about the management event.

Abstract: A microprocessor detects a floating point exchange instruction followed by a floating point instruction and dispatches the two instructions to the floating point unit as one combined instruction. The predecode unit marks the two instructions as a single instruction. A start bit is asserted for the first byte of the floating point exchange instruction and an end bit is asserted for the last byte of the floating point instruction. The combined instruction is dispatched into the instruction execution pipeline. A decode unit decodes the opcodes of the two instructions and passes the opcode of the floating point instruction to the floating point unit and passes exchange register information to the floating point unit The exchange register information includes a sufficient number of bits to specify a floating point register and a valid bit.

Abstract: A method of instruction dispatch is provided in which a directly-decoded instruction and a microcode instruction are concurrently dispatched ("packed"). The instruction which is second in program order is retained until the succeeding clock cycle. During the succeeding clock cycle, a microcode unit determines if the microcode instruction and the directly-decoded instruction, when taken together, occupy less than or equal to the total number of issue positions available in the microprocessor. If the microcode unit determines that less than or equal to the total number of issue positions are occupied, then the packing is successful. If the microcode unit determines that greater than the total number of issue positions are occupied, then the packing is unsuccessful and the retained instruction is redispatched. Additionally, instruction dispatch selection is performed in two phases. First, a number of instructions are selected as potentially dispatchable instructions.

Abstract: A superscalar processor includes a central scheduler for multiple execution units. The scheduler presumes operations issued to a particular execution unit all have the same latency, e.g., one clock cycle, even though some of the operations have longer latencies, e.g., two clock cycles. The execution unit that executes the operations having with longer than expected latencies, includes scheduling circuitry that holds up particular operation pipelines when operands required for the pipelines will not be valid when the scheduler presumes. Accordingly, the design of the scheduler can be simplified and can accommodate longer latency operations without being significantly redesigned for the longer latency operations.

Abstract: A distributed memory computer architecture associates separate memory blocks with their own processors, each of which executes the same program. A processor fetching data or instructions from its local memory also broadcasts that fetched data or instruction to the other processors to cut the time required for them to request this data. Runs of instruction and data local to one processor providing improved performance that is captured by the system as a whole by the ability of the other processors not executing local data or instructions to execute instructions out of order and return to find the data ready in buffer for rapid use.

Abstract: An information processor having a control unit in which a plurality of instructions to simultaneously be executed are decoded by a decoder section, an executing unit to be dispatched of a plurality of executing units is selected by an index selecting section according to a result of the decoding, and dispatch to any of the plurality of executing units is inhibited by a dispatch inhibiting section according to a result of the decoding by the decoder section as well as to a result of the selection by the index selecting section.

Abstract: A microprocessor comprises a plurality of instruction pipelines having a plurality of stages for processing a stream of instructions, circuitry for simultaneously issuing instructions into two or more of the pipelines without regard to whether one of the simultaneously issued instructions has a data dependency on other of the simultaneously issued instructions, detecting circuitry for detecting dependencies between instructions in the pipelines and circuitry for controlling the flow of instructions through the pipelines such that an instruction is not delayed due to a data dependency on another instruction unless the data dependency must be resolved for proper processing of the instruction in its current stage.

Abstract: A reorder buffer is configured into multiple lines of storage, wherein a line of storage includes sufficient storage for instruction results regarding a predefined maximum number of concurrently dispatchable instructions. A line of storage is allocated whenever one or more instructions are dispatched. A microprocessor employing the reorder buffer is also configured with fixed, symmetrical issue positions. The symmetrical nature of the issue positions may increase the average number of instructions to be concurrently dispatched and executed by the microprocessor. The average number of unused locations within the line decreases as the average number of concurrently dispatched instructions increases. One particular implementation of the reorder buffer includes a future file. The future file comprises a storage location corresponding to each register within the microprocessor.

Abstract: Herein disclosed is a microcomputer MCU adopting the general purpose register method. The microcomputer is enabled to have a small program capacity or a high program memory using efficiency and a low system cost, while enjoying the advantage of simplification of the instruction decoding as in the RISC machine having a fixed length instruction format of the prior art, by adopting a fixed length instruction format having a power of 2 but a smaller bit number than that of the maximum data word length fed to instruction execution means. And, the control of the coded division is executed by noting the code bits.

Abstract: An instruction queue is physically divided into two (or more) instruction queues. Each instruction queue is configured to store a dependency vector for each instruction operation stored in that instruction queue. The dependency vector is evaluated to determine if the corresponding instruction operation may be scheduled for execution. Instruction scheduling logic in each physical queue may schedule instruction operations based on the instruction operations stored in that physical queue independent of the scheduling logic in other queues. The instruction queues evaluate the dependency vector in portions, during different phases of the clock. During a first phase, a first instruction queue evaluates a first portion of the dependency vectors and generates a set of intermediate scheduling request signals. During a second phase, the first instruction queue evaluates a second portion of the dependency vector and the intermediate scheduling request signal to generate a scheduling request signal.

Abstract: An apparatus for supplying instructions to a processor has an instruction cache (1) and a branch target buffer (33). The branch target buffer stores instructions in order of execution achievable if a branch instruction is taken. The instructions in the branch target buffer are arranged before a branch predictor (35) makes a prediction whether or not the branch instruction is taken. If the prediction tells that the branch instruction will be taken, the instructions in the branch target buffer are supplied to an instruction decoder (9). If the prediction tells that the branch instruction will not be taken, instructions in the instruction cache are supplied to the instruction decoder.

Abstract: An execution unit that executes multiple instructions as a single instruction group during a single processing cycle is provided. The execution unit handles problem causing instruction groups by trapping the problem causing instruction group using the trap logic of a processing unit. The reissue logic circuits restores the program state of the execution unit prior to issuance of the trapped instruction group. The reissue logic circuit then forces each instruction of the instruction group to be issued as a separate instruction. Specifically, the reissue logic inhibits folding of instructions into instruction groups by an instruction-folding unit. After the instructions of the trapped instruction group are executed, the reissue logic re-enables folding by the instruction-folding unit.

Abstract: A method for merging binary translated basic blocks of instructions. The method is for use in a computer system having in a memory a first set of instructions including blocks of instructions, and a translator for translating instructions executable on a source instruction set architecture into instructions executable on a target instruction set architecture. The method includes a first step of determining, by the translator, an order of execution from a first block of instructions to a second block of instructions. A second step of the method includes generating, by the translator, a hyperblock of instructions representing the first and second block of instructions translated and placed adjacent in a memory location in the order of execution.

Abstract: An apparatus having a stack-top updating unit for processing an exchange instruction and a load instruction in parallel in a pipe-lined processor having a stack register file. Based on an information signal representing a modification of the stack-top after the current instruction is executed in a first pipe-line, a control signal indicating that a load instruction is executed by one of the first and second pipe-lines, and a second pipe-line enable signal, the stack-top updating unit generates a new stack-top signal and a current stack-top signal. The first pipe-line, in response to the current stack-top signal and operands, executes the operands, and the second pipe-line, in response to the new stack-top signal and the control signal, performs the load instruction or an exchange instruction. As a result, the load instruction or the Fload instruction can be simultaneously executed with another instruction or operand in the pipe-lined processor in an effective manner.

Abstract: A microprocessor comprises one or more instruction pipelines having a plurality of stages for processing a stream of instructions, with one or more of said instructions referencing a set of logical registers. A plurality of physical registers are allocated to store data associated with the logical registers by register translation circuitry. The register translation circuitry is selectively controlled by the microcode or by hardware signals generated by one or more of the stages.

Abstract: One aspect of the invention relates to a method for operating a processor. In one version of the invention, the method includes the steps of dispatching an instruction; determining a presently architected RMAP entry for the architectural register targeted by the dispatched instruction; selecting the RMAP entries which are associated with physical registers that contain operands for the dispatched instruction; updating a use indicator in the selected RMAP entries; determining whether the dispatched instruction is interruptible; and updating an architectural indicator and a historical indicator in the presently architected RMAP entry if the dispatched instruction is uninterruptible.

Abstract: A system, apparatus and method for ensuring program correctness in an out-of-order processor spite of younger load instructions being boosted past an older store utilizing a memory disambiguation buffer ("MDB"). The memory disambiguation buffer stores all memory operations that have not yet been retired. Each entry has several fields amongst which are the data and the addresses of the memory operations. An incoming load checks its address against the addresses of all the stores. If there is a match against an older store, then the load must have received old data from the data cache and the load operation is replayed to seek data from the memory disambiguation buffer on the replay. If on the other hand, there were no matches on any older store, the load is assumed to have received the right data from the data cache (assuming a data cache hit). An incoming store checks its address against the addresses of all younger loads.

Abstract: An instruction pipeline in a microprocessor is provided. The instruction pipeline includes a plurality of pipeline units, each of the pipeline units processing a plurality of instructions including branch instructions. The instruction pipeline further includes a plurality of storage device which store a respective branch information data. Each of the storage devices are associated with at least one of pipeline units. Each respective branch information data is determined as a function of at least one of the branch instructions processed. Two of the pipeline units include branch prediction circuitry for predicting branch direction as a function of the stored branch information data.

Abstract: A method for scheduling a flag generating instruction and a subsequent instruction. The subsequent instruction has a data dependency on the flag generating instruction. The flag generating instruction is translated into first and second instructions. The subsequent instruction is translated into at least a third instruction. The first instruction, when executed, generates a result and intermediate flag generation data. The second instruction, when executed, generates a plurality of flags. The first instruction is scheduled to execute before the second and third instructions. The second instruction is scheduled to execute before the third instruction if the third instruction has a data dependency on the second instruction, otherwise the third instruction may be scheduled to execute before the second instruction.

Abstract: A processor which includes separate instruction and data caches and which executes instructions according to a new instruction set architecture efficiently executes software code by providing the processor with a grouper circuit which receives software code instructions from a secondary memory and groups these instructions based upon the content of the instructions and provides these grouped instructions to the instruction cache of the processor. In this processor, the old instruction software code conforms to an old instruction set which is a subset of the new instruction set.

Abstract: Scan logic which tracks the relative age of stores with respect to a particular load (or of loads with respect to a particular store) allows at processor to hold younger stores until the completion of older loads (or to hold younger loads until completion of older stores). Embodiments of propagate-kill style lookahead scan logic or of tree-structured, hierarchically-organized scan logic constructed in accordance with the present invention provide store older and load older indications with very few gate delays, even in processor embodiments adapted to concurrently evaluate large numbers of operations. Operating in conjunction with the scan logic, address matching logic allows the processor to more precisely tailor its avoidance of load-store (or store-load) dependencies.

Abstract: A computer system including a microprocessor employing a reorder buffer is provided which stores a last in buffer (LIB) indication corresponding to each instruction. The last in buffer indication indicates whether or not the corresponding instruction is last, in program order, of the instructions within the buffer to update the storage location defined as the destination of that instruction. The LIB indication is included in the dependency checking comparisons. A dependency is indicated for a given source operand and a destination operand within the reorder buffer if the operand specifiers match and the corresponding LIB indication indicates that the instruction corresponding to the destination operand is last to update the corresponding storage location. At most one of the dependency comparisons for a given source operand can indicate dependency. According to one embodiment, the reorder buffer employs a line-oriented configuration.

Abstract: A method and system for providing direct execution of a serializing instruction in a processor is disclosed. The processor has the serializing instruction and a nonserializing instruction. The processor includes execution logic having a pipeline for executing the nonserializing instruction. The processor also includes logic separate from the execution logic for executing the serializing instruction. The method and system include recognizing the serializing instruction, recognizing the nonserializing instruction, providing the nonserializing instruction to the execution logic, and providing the serializing instruction to the separate logic. The serializing instruction is executed without providing the serializing instruction to the pipeline.

Abstract: An apparatus and method reorder portions of a computer program in a way that achieves both enhanced performance and maintainability of the computer program. A global call graph is initially constructed that includes profile data. From the information in the global call graph, an intramodular call graph is generated for each module. Reordering techniques are used to reorder the procedures in each module according to the profile data in each intramodular call graph. An intermodular call graph is generated from the information in the global call graph. Reordering techniques are used to reorder the modules in the computer program. By reordering procedures within modules, then reordering the modules, enhanced performance is achieved without reordering procedures across module boundaries.

Abstract: A reorder buffer is configured into multiple lines of storage, wherein a line of storage includes sufficient storage for instruction results regarding a predefined maximum number of concurrently dispatchable instructions. A line of storage is allocated whenever one or more instructions are dispatched. A microprocessor employing the reorder buffer is also configured with fixed, symmetrical issue positions. The symmetrical nature of the issue positions may increase the average number of instructions to be concurrently dispatched and executed by the microprocessor. The average number of unused locations within the line decreases as the average number of concurrently dispatched instructions increases. One particular implementation of the reorder buffer includes a future file. The future file comprises a storage location corresponding to each register within the microprocessor.

Abstract: In a microprocessor, an Instruction scheduler 30 includes a dependency matrix 36 and a waiting buffer 34. A dependency determination unit 32 receives instructions to be executed, forwards the instructions to the waiting buffer 34, determines if any dependency exists between the instructions, and forwards the dependency information to the dependency matrix 36 in the form of a dependency vector 40. Dependency matrix 36 periodically determines whether any of the instructions contained in the waiting buffer 34 are ready to be executed, that is, no dependencies exist for that instruction. All identified instructions are then assigned to a current wave to be dispatched. The identified instructions are then dispatched for execution as execution resources become available. As each instruction is dispatched for execution in the waiting buffer 34, the dependency vector 40 for all dependent instructions is cleared for subsequent execution.

Abstract: A new instruction that ensures that the effects of a control register write will be observed at a well defined time is introduced. Specifically, the present invention introduces the concept of a serialization fence instruction. The serialization fence instruction ensures that after a control register in a computer has been modified, all subsequent instructions will observe the effects of the control register modification. Two different serialization fence instructions are illustrated: a data memory reference serialization fence instruction (SRLZ.d) and an instruction fetch serialization fence instruction (SRLZ.i). The data memory reference serialization fence instruction ensures that subsequent instruction executions and data memory references will observe the effects of the control register write. The instruction fetch serialization fence instruction ensures that the entire machine pipeline, starting at the initial instruction fetch stage, will observe the effects of the control register write.

Abstract: A method for guaranteeing minimum variable scheduling distance between instructions in a processor includes receiving a plurality of instructions and determining the post-ready latency of each instruction. Each instruction is then scheduled for execution so that the instruction follows an earlier instruction by an amount of time at least equal to the post-ready latency of the instruction.

Abstract: A processor that executes coded instructions using an instruction scheduling unit receiving the coded instructions and issuing an instruction for execution. A replay signaling device generates a signal indicating when the instruction failed to execute properly within a predetermined time. A replay device within the instruction scheduling unit responsive to the signaling device then reissues the instruction for execution.

Abstract: An unpacking circuit and operating method in a very long instruction word (VLIW) processor provides for parallel handling of a packed wide instruction in which a packed wide instruction is divided into groups of syllables. An unpacked instruction representation includes a plurality of syllables, which generally correspond to operations for execution by an execution unit. The syllables in the unpacked instruction representation are assigned to groups. The packed instruction word includes a sequence of syllables and a header. The header includes a descriptor for each group. The descriptor includes a mask and may include a displacement designator. The multiple groups are handled in parallel as the displacement designator identifies a starting syllable. The mask designates the syllables which are transferred from the packed instruction to the unpacked representation and identifies the position of NOPs in the unpacked representation.

Abstract: A method and system for increased instruction dispatch efficiency in a superscalar processor system having an instruction queue for receiving a group of instructions in an application specified sequential order and an instruction dispatch unit for dispatching instructions from an associated instruction buffer to multiple execution units on an opportunistic basis. The dispatch status of instructions within the associated instruction buffer is periodically determined and, in response to a dispatch of the instructions at the beginning of the instruction buffer, the remaining instructions are shifted within the instruction buffer in the application specified sequential order and a partial group of instructions are loaded into the instruction buffer from the instruction queue utilizing a selectively controlled multiplex circuit. In this manner additional instructions may be dispatched to available execution units without requiring a previous group of instructions to be dispatched completely.

Abstract: A microprocessor is provided which detects an escape instruction. The escape instruction indicates that subsequent instructions belong to an alternate instruction set. In one embodiment, the number of subsequent instructions which belong to the alternate instruction set is encoded in the escape instruction. The subsequent instructions are routed to an execution unit or a separate processor for execution. Each instruction sequence within a program may be coded using the instruction set which most efficiently executes the function corresponding to the instruction sequence. In one embodiment, the microprocessor executes the x86 instruction set and the alternate instruction set is the ADSP 2171 instruction set. The escape instruction is defined using a previously undefined opcode within the x86 instruction set. Complex mathematical functions (which are more efficiently executed within a DSP) may be performed more efficiently than previously achievable using the x86 instruction set alone.

Abstract: An information processing apparatus includes an instruction storage for storing a plurality of instructions and a central processing unit for fetching the instructions from the instruction storage device so as to execute the instructions. The central processing unit executes a process to perform operations which require at least two machine cycles of the central processing unit by separately executing a first instruction for setting first data required for operations and a second instruction for fetching second data obtained by the operations. The machine cycle is a time unit for executing an instruction by the central processing unit. The central processing unit executes at least one third instruction after executing the first instruction and before executing the second instruction, the third instruction not requiring the second data.

Abstract: A CPU (central processing unit) of a computer. The CPU comprises a dispatch controller, a pipeline, a working register file, and an architectural register file. The dispatch controller dispatches instructions for execution and determines whether the dispatched instructions are valid or invalid. The pipeline executes the dispatched instructions using selected operands in the pipeline and generates operands in response. The working register file stores the generated operands before the executed instructions are determined to be valid or invalid by the dispatch controller such that the stored operands may be subsequently selected for use in executing an instruction in the pipeline. The architectural register file stores the generated operands for those of the executed instructions that are determined to be valid by the dispatch controller and transfer operands currently stored therein when one of the executed instructions is determined to be invalid by the dispatch logic.

Abstract: A method for handling dynamic structural hazards and exceptions by using post-ready latency, including: receiving a plurality of instructions; selecting a first instruction whose execution can cause an exception; assigning a post-ready latency to a second instruction that follows the first instruction; and scheduling for execution the first instruction and the second instruction separated from the first instruction by an amount of time at least equal to the post-ready latency of the second instruction.

Abstract: The present invention solves the problems associated with the prior art by providing a latency prediction bit (LPB) to indicate the latency with which an instruction should be executed, implicitly indicating whether a data dependency is likely to exist and the likelihood of that dependency causing a hazard. In a processor according to the present invention, an instruction dependent upon a given LDI instruction is issued a given number of machine cycles after that LDI instruction, the number of machine cycles being based on the value of the LPB associated with that LDI instruction. The LPB's value, in turn, depends on whether data will need to be forwarded to the functional unit involved during the execution of LDI instruction. The ability to predict such hazards is important in maintaining a pipeline's throughput and avoiding unnecessary recirculations.

Abstract: An apparatus and several methods provide for a more optimized computer program that will have a faster execution time than was possible using the prior art reordering technique that adds to a trace until it finds no more predecessors or successors to add. The apparatus and methods disclosed herein use a variety of methods to reorder the program portions in a more intelligent manner that will improve its run-time performance. Each of these methods involves constructing traces in the control flow graph of the computer program. In a first embodiment, a basic block is only added to a trace if it is not negligible within predetermined limits. This negligibility test results in traces that are not extended for infrequently executed basic blocks. In a second embodiment, a basic block is only added to a trace if it is a perfect partner with the last basic block added to the trace. The concept of a "perfect partner" helps to match basic blocks together in a trace that have the greatest affinity for each other.

Abstract: A microprocessor including a context file configured to store multiple contexts is provided. The microprocessor may execute multiple threads, each thread having its own context within the microprocessor. In one embodiment, the present microprocessor is capable of executing at least two threads concurrently: a task and an interrupt service routine. Interrupt service routines may be executed without disturbing a task's context and without performing a context save operation. Instead, the interrupt service routine accesses a context which is independent of the context of the task. In another embodiment, the context file includes multiple interrupt service routine contexts. Multiple ISR context storages allow for nested interrupts to be performed concurrently. In yet another embodiment, the microprocessor is configured to execute multiple tasks and multiple interrupt service routines concurrently.

Abstract: In a superscalar processor for fetching a prescribed peak number of instructions in parallel in each period until such instructions are fetched to a predetermined peak number, such as ten, an instruction parallel issue and execution administrating device comprises a forward map buffer for a forward map indicative of a result of each instruction for use as an operand by which one of other instructions of the predetermined peak number. The forward map is developed before the result is actually produced and is used, after the actual production, to indicate which one of such results should be used as the operand by the above-mentiond one of the other instructions.

Abstract: A method for executing instructions out-of-order to improve performance of a processor includes compiling the instructions of a program into separate queues along with encoded dependencies between instructions in the different queues. The processor then issues instructions from each of these queues independently, except that it enforces the encoded dependencies among instructions from different queues. If an instruction is dependent on instructions in other queues, the processor waits to issue it until the instructions on which it depends are issued. The processor includes a stall unit, comprised of a number of instruction counters for each queue, that enforces the dependencies between instructions in different queues.

Abstract: The present invention solves the problems associated with the prior art by decoupling the issuing of instructions from their dispatch into their respective pipeline. This permits the determination of whether a particular instruction can safely be issued from an instruction queue to the next stage of the pipeline by providing such information at a point early in the machine cycle.