Abstract: A method for a prediction correlation between a first group of branch instructions in a bunch of instructions and a second group of branch instructions in a bunch of instructions is disclosed. The method includes indicating a direction of a plurality of branch instructions in a bunch of instructions. More particularly, the method includes building an address composed of an instruction fetch address and bits in a history register. The method accesses a bunch of instructions using the fetch address and accesses a prediction bits set from a branch history table using the composed address. The accessed bunch of instructions are processed. Further, the history register and the branch history table are updated to correlate a first group of a branch instructions in the accessed bunch of instructions to a second group of branch instructions in a next group of branch instructions in the bunch of instructions.

Abstract: A method for operating a processor that executes coded instructions using an instruction scheduling unit receiving the coded instructions and issuing an instruction for execution. A replay signaling device generates a signal indicating when the instruction failed to execute properly within a predetermined time. A replay device within the instruction scheduling unit responsive to the signaling device then reissues the instruction for execution.

Abstract: A method for scheduling a flag generating instruction and a subsequent instruction. The subsequent instruction has a data dependency on the flag generating instruction. The flag generating instruction is translated into first and second instructions. The subsequent instruction is translated into at least a third instruction. The first instruction, when executed, generates a result and intermediate flag generation data. The second instruction, when executed, generates a plurality of flags. The first instruction is scheduled to execute before the second and third instructions. The second instruction is scheduled to execute before the third instruction if the third instruction has a data dependency on the second instruction, otherwise the third instruction may be scheduled to execute before the second instruction.

Abstract: A system and method for improving microprocessor computer system out of order support via register management with synchronization of multiple pipelines and providing for processing a sequential stream of instructions in a computer system having a first and a second processing element, each of the processing elements having its own state determined by a setting of its own general purpose and control registers. When at any point in the processing of said sequential stream of instructions by said first processing element it becomes beneficial to have the second processing element begin continued processing of the same sequential instruction stream then the first and second processing elements process the sequential stream of instructions and may be executing the very same instruction but only one of said processing elements is permitted to change the overall architectural state of said computer system which is determined by a combination of the states of said first and second processing elements.

Abstract: A processor which includes separate instruction and data caches and which executes instructions according to a new instruction set architecture efficiently executes software code by providing the processor with a grouper circuit which receives software code instructions from a secondary memory and groups these instructions based upon the content of the instructions and provides these grouped instructions to the instruction cache of the processor. In this processor, the old instruction software code conforms to an old instruction set which is a subset of the new instruction set.

Abstract: User commands and command parameters in a graphical user interface are logged in a command log. Repeating patterns of commands and command parameters are automatically detected. This detection is invisible to the user. The user is then prompted to see if a shortcut script should be created for a given repeating pattern of commands and command parameters that has been detected. If the user responds affirmatively, a shortcut script is created that will execute that repeating pattern of commands and command parameters. The user may also be given the option of editing the commands and command parameters before they are made into a shortcut script.

Abstract: Cost/performance of VLIW architecture is improved by reducing the number of slots in the instruction issue register.

Abstract: Each small instruction in a VLIW instruction (long instruction) is added with the number of NOP instructions which succeed the small instruction, and these NOP instructions are deleted from the succeeding long instruction. A plurality of long instructions are therefore time-compressed. Thereafter, a plurality of small instructions in each long instruction are divided into a plurality of groups, and a combination of operation codes (OP codes) of small instructions in each group is replaced by a group code to generate a compressed, grouped instruction. Each long instruction is therefore space-compressed. An instruction expanding unit has an instruction expanding circuit for each grouped instruction. Each instruction expanding circuit expands one grouped instruction in a long instruction, generates a group of small instructions represented by the grouped instruction, and supplies the group of generated small instructions to respective function units via a decode unit.

Abstract: A microprocessor configured to predict the length of variable length instructions for decoding purposes by detecting patterns of instruction lengths that have been previously decoded. The microprocessor has a cache, an instruction length calculation unit, and a pattern detector. The instruction length calculation unit receives instruction bytes from the cache and generates an instruction length corresponding thereto. The pattern detector stores a plurality of instruction length sequences, each comprising an initial sequence and a final sequence. The pattern detector is configured to receive instruction lengths from the length calculation unit and compare them with the stored initial sequences. If the pattern detector finds a match, it outputs the corresponding final sequence for use as predicted instruction lengths. A method for using instruction length pattern detection for decoding is also disclosed.

Abstract: Scan logic which tracks the relative age of stores with respect to a particular load (or of loads with respect to a particular store) allows at processor to hold younger stores until the completion of older loads (or to hold younger loads until completion of older stores). Embodiments of propagate-kill style lookahead scan logic or of tree-structured, hierarchically-organized scan logic constructed in accordance with the present invention provide store older and load older indications with very few gate delays, even in processor embodiments adapted to concurrently evaluate large numbers of operations. Operating in conjunction with the scan logic, address matching logic allows the processor to more precisely tailor its avoidance of load-store (or store-load) dependencies.

Abstract: There is disclosed a multi-processor system arranged, in one embodiment, as an image and graphics processor. The processor is structured with several individual processors all having communication links to several memories. The individual processors can, on a cycle by cycle basis, be grouped in any configuration to run in synchronism (but from different instruction streams) with the other processors in that group. More than one such synchronized group can be formed concurrently. A crossbar switch serves to establish the processor memory links and the entire image processor, including the individual processors, the crossbar switch and the memories are contained on a single silicon chip.

Abstract: A microprocessor capable of processing at least two program instructions at the same time and capable of issuing the two program instructions to two symmetrical multifunctional program execution units. The microprocessor includes a plurality of registers which store a plurality of operands and an instruction issue control which controls issuance of program instructions to the two symmetrical multifunctional program execution units. The instruction issue control issues the two program instructions (e.g. first and second) without decoding them in order to determine the processing functions required to be performed in response to the two program instructions.

Abstract: An apparatus includes a clock to produce pulses and an electronic hardware structure having a plurality of rows and one or more ports. Each row is adapted to record a separate latency vector written through one of the ports. The latency vector recorded therein is responsive to the clock. A method of dispatching instructions in a processor includes updating a plurality of expected latencies to a portion of rows of a register latency table, and decreasing the expected latencies remaining in other of the rows in response to a clock pulse. The rows of the portion correspond to particular registers.

Abstract: A computer system including a microprocessor employing a reorder buffer is provided which stores a last in buffer (LIB) indication corresponding to each instruction. The last in buffer indication indicates whether or not the corresponding instruction is last, in program order, of the instructions within the buffer to update the storage location defined as the destination of that instruction. The LIB indication is included in the dependency checking comparisons. A dependency is indicated for a given source operand and a destination operand within the reorder buffer if the operand specifiers match and the corresponding LIB indication indicates that the instruction corresponding to the destination operand is last to update the corresponding storage location. At most one of the dependency comparisons for a given source operand can indicate dependency. According to one embodiment, the reorder buffer employs a line-oriented configuration.

Abstract: A superscalar microprocessor implements a repeated string instruction by putting the microcode unit in a continuous loop. The microcode sequence that implements the repeated string operation includes a conditional-exit instruction rather than a conditional branch and decrement microcode instruction. A conditional-exit instruction decrements a loop count value and conveys a termination signal to a microcode unit when a termination condition is detected. Because several iterations of the instructions that implement the string instruction may be dispatched before the conditional-exit instruction is evaluated, the additional iterations of the microcode loop are canceled. By eliminating the conditional branch and decrement microcode instruction, a loop iteration may be executed in a single clock cycle by three functional units.

Abstract: The present invention features a computer with a mechanism for implementing precise interrupts for statically speculated instructions. One or more assumptions are generated, and all instructions in each assumption are tagged identically and statically scheduled on a speculative basis. An instruction is then modified or inserted at one or more decision points prior to the point at which the instruction was speculated. The decision points may be positive ones (the instructions scheduled under that assumption have succeeded) or negative ones (the instructions scheduled under that assumption have failed), or both. A decision point may be positive for one assumption and negative for another assumption. Static speculation may be performed down both sides of branches and may be performed simultaneously for multiple, independent paths. Efficient restart can also be effected.

Abstract: A system and method is provided for use in register-based CPUs for simultaneously processing data in a series of CPU register banks while concurrently loading and unloading data into additional register banks. The register banks then sequentially shared between arithmetic processors connected to the CPU datapath. Each register bank, after being loaded with data, is connected to a plurality of data processors in sequence and the data in each register bank is processed. The data is not moved between register banks within the datapath, except when it is loaded and unloaded from the datapath. The invention takes advantage of the shorter time required to move control signals, as compared with moving data.

Abstract: A digital computer system capable of processing two or more computer instructions in parallel and having a cache storage unit for temporarily storing machine-level computer instructions in their journey from a higher-level storage unit of the computer system to the functional units which process the instructions. The computer system includes an instruction compounding unit located intermediate to the higher-level storage unit and the cache storage unit for analyzing the instructions and generating for to each instruction a compounding information which indicates whether or not that instruction may be processed in parallel with one or more neighboring instructions in the instruction stream. These tagged instructions are then stored in the cache unit with the compounding information. The computer system further includes a plurality of functional instruction processing units which operate in parallel with one another. The instructions supplied to these functional units are obtained from the cache storage unit.

Abstract: A processing architecture includes a first CPU core portion coupled to a second embedded dynamic random access memory (DRAM) portion. These architectural components jointly implement a single processor and instruction set. Advantageously, the embedded logic on the DRAM chip implements the memory intensive processing tasks, thus reducing the amount of traffic that needs to be bussed back and forth between the CPU core and the embedded DRAM chips. The embedded DRAM logic monitors and manipulates the instruction stream into the CPU core. The architecture of the instruction set, data paths, addressing, control, caching, and interfaces are developed to allow the system to operate using a standard programming model. Specialized video and graphics processing systems are developed. Also, an extended very long instruction word (VLIW) architecture implemented as a primary VLIW processor coupled to an embedded DRAM VLIW extension processor efficiently deals with memory intensive tasks.

Abstract: A CPU having a cluster VLIW architecture is shown which operates in both a high instruction level parallelism (ILP) mode and a low ILP mode. In high ILP mode, the CPU executes wide instruction words using all operational clusters of the CPU and all of a main instruction cache and main data cache of the CPU are accessible to a high ILP task. The CPU also includes a mini-instruction cache, a mini-instruction register and a mini-data cache which are inactive during high ILP mode. An instruction level controller in the CPU receives a low ILP signal, such as an interrupt or function call to a low ILP routine, and switches to low ILP mode. In low ILP mode, the main instruction cache and main data cache are deactivated to preserve their contents. At the same time, a predetermined cluster remains active while the remaining clusters are also deactivated. The low ILP task executes instructions from the mini-instruction cache which are input to the predetermined cluster through the mini-instruction register.

Abstract: A reorder buffer is configured into multiple lines of storage, wherein a line of storage includes sufficient storage for instruction results regarding a predefined maximum number of concurrently dispatchable instructions. A line of storage is allocated whenever one or more instructions are dispatched. A microprocessor employing the reorder buffer is also configured with fixed, symmetrical issue positions. The symmetrical nature of the issue positions may increase the average number of instructions to be concurrently dispatched and executed by the microprocessor. The average number of unused locations within the line decreases as the average number of concurrently dispatched instructions increases. One particular implementation of the reorder buffer includes a future file. The future file comprises a storage location corresponding to each register within the microprocessor.

Abstract: A 32-bit processor control unit receives from a memory an instruction. The control unit then determines whether the received instruction is intended for a 32-bit processor or for a 16-bit processor. If the received instruction is analyzed to be a 32-bit processor instruction, the control unit controls the 32-bit processor with the aid of two 16-bit instruction control units. If the received instruction is a 16-bit processor instruction, the 32-bit processor control unit sends a 16-bit processor mode signal to each of the 16-bit instruction control units. One of the two 16-bit instruction control units controls one of two 16-bit processors which are divisions of the 32-bit processor while the other 16-bit instruction control unit controls the other 16-bit processor. The present invention makes it possible to have a single, wide bitwidth processor serve as a plurality of narrow bitwidth processors depending upon the type of processing.

Abstract: A floating point unit capable of executing multiple instructions in a single clock cycle using a central window and a register map is disclosed. The floating point unit comprises: a plurality of translation units, a future file, a central window, a plurality of functional units, a result queue, and a plurality of physical registers. The floating point unit receives speculative instructions, decodes them, and then stores them in the central window. Speculative top of stack values are generated for each instruction during decoding. Top of stack relative operands are computed to physical registers using a register map. Register stack exchange operations are performed during decoding. Instructions are then stored in the central window, which selects the oldest stored instructions to be issued to each functional pipeline and issues them. Conversion units convert the instruction's operands to an internal format, and normalization units detect and normalize any denormal operands.

Abstract: A method of sending a plurality of commands to a remote device which executes the plurality of commands, the method including the steps of encapsulating the plurality of commands within a single command; and sending the single command to the remote device.

Abstract: A method and system in a superscalar data processing system are disclosed for the temporary designation and utilization of a plurality of physical registers as a stack. For each of the multiple instructions to be processed during a single clock cycle by the data processing system, a determination is made whether each of the instructions is a particular type of instruction. If a determination is made that an instruction is a particular type of instruction, a quantity of physical registers to be temporarily designated as a stack is determined utilizing the instruction. A second plurality of physical registers available to be utilized as a stack are determined whether the second plurality of the quantity. The second plurality of physical registers are then temporarily designated and utilized as a stack.

Abstract: An instruction alignment unit is provided which is capable of routing variable byte length instructions simultaneously to a plurality of decode units which form fixed issue positions within a superscalar microprocessor. The instruction alignment unit may be implemented with a relatively small number of cascaded levels of logic gates, thus accomodating very high frequencies of operation. In one embodiment, the superscalar microprocessor includes an instruction cache for storing a plurality of variable byte-length instructions and a predecode unit for generating predecode tags which identify the location of the start byte of each variable byte-length instruction. An instruction alignment unit is configured to channel a plurality of the variable byte-length instructions simultaneously to predetermined issue positions depending upon the locations of their corresponding start bytes in a cache line.

Abstract: The invention relates to the area of register renaming and allocation in superscalar computer systems. When a multitude of instructions in the instruction stream reads from or writes to a certain logical register, said logical register will have to be represented by a multitude of physical registers.Therefore, there have to exist several physical rename registers per logical register. The oldest one of said rename registers defines the architected state of the computer system, the in-order state.The invention provides a method for administration of the various register instances. Both the registers representing the in-order state and the various rename instances are kept in one common circular buffer. There exist two pointers per logical register: The first one, the in-order pointer, points to the register that represents the in-order state, the second one, the rename pointer, points to the most recent rename instance.

Abstract: A method for guaranteeing minimum variable scheduling distance between instructions in a processor includes receiving a plurality of instructions and determining the post-ready latency of each instruction. Each instruction is then scheduled for execution so that the instruction follows an earlier instruction by an amount of time at least equal to the post-ready latency of the instruction.

Abstract: An address translation memory stores a plurality of virtual address tags. The virtual address tags typically designate a portion of the virtual address space corresponding to a page of data stored in an intermediate storage device. A portion of an input virtual address is used to address the translation memory, and the resulting output virtual address tag is compared to a relevant portion of the input virtual address. If they match, then the requested data resides in the intermediate storage device, and an instruction issuing unit allows the instructions to continue issuing to an instruction pipeline as scheduled. However, if the virtual address tag does not match the relevant portion of the input virtual address, then it is assumed that a page fault might occur, and the instruction issuing unit inhibits the issuance of further instructions to the instruction pipeline.

Abstract: A processor that executes coded instructions using an instruction scheduling unit receiving the coded instructions and issuing an instruction for execution. A replay signaling device generates a signal indicating when the instruction failed to execute properly within a predetermined time. A replay device within the instruction scheduling unit responsive to the signaling device then reissues the instruction for execution.

Abstract: An FPSCR (Floating Point Status and Control Register) mechanism supports de-serialized floating point unit (FPU) instruction execution. The FPSCR mechanism provides for speculative execution of all FPU instructions. In particular, instructions that directly alter FPSCR data values may be executed speculatively. Instructions of this type which may be de-serialized include the move-from FPSCR instruction, the move-to-condition register from FPSCR instruction, the move-to FPSCR field immediate instruction, the move-to FPSCR field instruction, the move-to FPSCR bit 0 instruction, the move-to FPSCR bit 1 instruction, as well as FPU register-to-register instructions having a recording bit set. Speculative execution is implemented by providing an accurate working FPSCR at the time the speculatively executing instruction sources FPSCR data. Moreover, the FPSCR mechanism re-establishes the working FPSCR when exceptions occur, or speculative execution is cancelled.

Abstract: An unpacking circuit and operating method in a very long instruction word (VLIW) processor provides for parallel handling of a packed wide instruction in which a packed wide instruction is divided into groups of syllables. An unpacked instruction representation includes a plurality of syllables, which generally correspond to operations for execution by an execution unit. The syllables in the unpacked instruction representation are assigned to groups. The packed instruction word includes a sequence of syllables and a header. The header includes a descriptor for each group. The descriptor includes a mask and may include a displacement designator. The multiple groups are handled in parallel as the displacement designator identifies a starting syllable. The mask designates the syllables which are transferred from the packed instruction to the unpacked representation and identifies the position of NOPs in the unpacked representation.

Abstract: A system and method for extracting complex, variable length computer instructions from a stream of complex instructions each subdivided into a variable number of instructions bytes, and aligning instruction bytes of individual ones of the complex instructions. The system receives a portion of the stream of complex instructions and extracts a first set of instruction bytes starting with the first instruction bytes, using an extract shifter. The set of instruction bytes are then passed to an align latch where they are aligned and output to a next instruction detector. The next instruction detector determines the end of the first instruction based on said set of instruction bytes. An extract shifter is used to extract and provide the next set of instruction bytes to an align shifter which aligns and outputs the next instruction. The process is then repeated for the remaining instruction bytes in the stream of complex instructions.

Abstract: Computer system with multiple, out-of-order, instruction issuing system suitable for superscalar processors with a RISC organization, also has a Fast Dispatch Stack (FDS), a dynamic instruction scheduling system that may issue multiple, out-of-order, instructions each cycle to functional units as dependencies allow. The basic issuing mechanism supports a short cycle time and its capabilities are augmented. Condition code dependent instructions issue in multiples and out-of-order. A fast register renaming scheme is presented. An instruction squashing technique enables fast precise interrupts and branch prediction. Instructions preceding and following one or more predicted conditional branch instructions may issue out-of-order and concurrently. The effects of executed instructions following an incorrectly predicted branch instruction or an instruction that causes a precise interrupt are undone in one machine cycle.

Abstract: A method, system, and computer program product are provided for profiling virtual memory accesses by one or more threads. A virtual memory access thread profiling tool includes a histogram generator and a thread placement file generator. The histogram generator generates a histogram that indicates the relative frequency at which virtual memory addresses are accessed by each program thread. To generate the histogram, the histogram generator runs and interrupts each program thread to collect samples. When an interrupt is issued, a program counter is returned. A valid load or store instruction is determined for a thread in assembly code identified by the returned program counter. In one example, to determine a valid load or store instruction, the histogram generator walks forward or backward through the assembly code identified by the returned program counter until a valid load or store instruction is reached. A virtual memory address corresponding to a valid load or store instruction is then read.

Abstract: A computing system includes a main memory, an instruction cache and a processor. The processor includes memory interface means, predecoding means, interface means, a first arithmetic logic unit, a second arithmetic logic unit and steering means. The memory interface means is connected to the main memory and fetches instructions from the main memory. The predecoding means is connected to the memory interface means and predecodes the instructions to generate predecode bits. The predecode bits indicate whether and how the instructions may be bundled. The interface means is connected to the predecoding means and the instruction cache. The interface means stores the instructions and the predecode bits in the instruction cache and fetches the instructions from the instruction cache with the predecode bits. The steering means is connected to the interface means, the first arithmetic logic unit and the second arithmetic logic unit.

Abstract: A method and system in a data processing system of permitting concurrent processing of multiple conditional branch instructions are disclosed. A condition register is established within the processing system. First and second conditional branch instructions are dispatched during a single cycle of the processing system. Prior to speculatively executing the first conditional branch instruction, a first copy of the condition register is stored. Prior to speculatively executing the second conditional branch instruction, a second copy of the condition register is stored. Multiple copies of the condition register are concurrently maintained so that the first and second conditional branch instructions may be concurrently processed during a single cycle of the processing system.

Abstract: A register renaming system for out-of-order execution of a set of reduced instruction set computer instructions having addressable source and destination register fields, adapted for use in a computer having an instruction execution unit with a register file accessed by read address ports and for storing instruction operands. A data dependance check circuit is included for determining data dependencies between the instructions. A tag assignment circuit generates one of more tags to specify the location of operands, based on the data dependencies determined by the data dependance check circuit. A set of register file port multiplexers select the tags generated by the tag assignment circuit and pass the tags onto the read address ports of the register file for storing execution results.

Abstract: A technique for increasing the number of physical segment registers by renaming logical segment registers into a larger register space. The remapping of the segment registers allows for instructions accessing the segment registers to be executed non-serially. The renaming of segment registers is achieved by assigning a shadow register to a segment register name. Thus, a pair of registers are physically available for a specified logical register in an instruction set to be renamed. Two bits, designated as the PSEG and SPEC bits, are used to control the remapping.

Abstract: A very long instruction word (VLIW) architecture describes a processor comprising multiple functional units operating in parallel. A very long instruction word contains a plurality of fields or issue slots for specifying which operations are to be performed by the functional units. Execution of an operation can be inhibited by a guard value specified in the issue slot. Instructions are dispatched in such a guarded VLIW architecture by routing one of a plurality of fields issued for a common functional unit based on the guard value. Thus, an instruction word may contain a greater number of issue slots than there are functional units.

Abstract: A processor having multiple functional units. The processor is capable of executing multiple instructions concurrently. An instruction issuing unit is connected to a mechanism for handling an interrupt of the processor. The interrupt handler has an instruction window (IW), which includes a vector element number (VEN) field that indicates the uncompleted elements to be executed. Upon termination of the interrupt, normal processing of the instruction issuing unit continues.

Abstract: A CPU (central processing unit) of a computer. The CPU comprises a dispatch controller, a pipeline, a working register file, and an architectural register file. The dispatch controller dispatches instructions for execution and determines whether the dispatched instructions are valid or invalid. The pipeline executes the dispatched instructions using selected operands in the pipeline and generates operands in response. The working register file stores the generated operands before the executed instructions are determined to be valid or invalid by the dispatch controller such that the stored operands may be subsequently selected for use in executing an instruction in the pipeline. The architectural register file stores the generated operands for those of the executed instructions that are determined to be valid by the dispatch controller and transfer operands currently stored therein when one of the executed instructions is determined to be invalid by the dispatch logic.

Abstract: A queue structure includes a plurality of entries, a plurality of ports coupled to the entries, a plurality of enable lines coupled to the entries and the ports, and control logic. Each enable line is adapted to enable a selected port to communicate with a selected entry. The control logic is adapted to enable at least two enable lines and allow at least one of the ports to communicate with at least two of the entries concurrently. A method for storing data in a queue is provided. The queue includes a plurality of entries, a plurality of ports coupled to the entries, and a plurality of enable lines coupled to the entries and the ports. Each enable line is adapted to enable a selected port to communicate with a selected entry. The method includes receiving a first instruction on one of the ports. A first enable line is enabled to allow the port to communicate with a first entry. The first instruction is stored in the first entry.

Abstract: A processor processes a plurality of instructions according to a disclosed method. First, the method receives (32) an instruction from the plurality of instructions. Second, the method determines (34) whether the received instruction is preceded by an instruction path leading code. Third, the method passes (36 or 38) the received instruction along at least one instruction path in a plurality of instruction paths. Fourth, in response to determining that the received instruction is preceded by an instruction path leading code, the method executes a machine word corresponding to the received instruction and selected from one of the plurality of instruction paths. Specifically, the selected instruction path is selected in response to the instruction path leading code.

Abstract: A method for handling dynamic structural hazards and exceptions by using post-ready latency, including: receiving a plurality of instructions; selecting a first instruction whose execution can cause an exception; assigning a post-ready latency to a second instruction that follows the first instruction; and scheduling for execution the first instruction and the second instruction separated from the first instruction by an amount of time at least equal to the post-ready latency of the second instruction.

Abstract: A high-performance, superscalar-based computer system with out-of-order instruction execution for enhanced resource utilization and performance throughput. The computer system fetches a plurality of fixed length instructions with a specified, sequential program order (in-order). The computer system includes an instruction execution unit including a register file, a plurality of functional units, and an instruction control unit for examining the instructions and scheduling the instructions for out-of-order execution by the functional units. The register file includes a set of temporary data registers that are utilized by the instruction execution control unit to receive data results generated by the functional units. The data results of each executed instruction are stored in the temporary data registers until all prior instructions have been executed, thereby retiring the executed instructions in-order.

Abstract: A reorder buffer is configured into multiple lines of storage, wherein a line of storage includes sufficient storage for instruction results regarding a predefined maximum number of concurrently dispatchable instructions. A line of storage is allocated whenever one or more instructions are dispatched. A microprocessor employing the reorder buffer is also configured with fixed, symmetrical issue positions. The symmetrical nature of the issue positions may increase the average number of instructions to be concurrently dispatched and executed by the microprocessor. The average number of unused locations within the line decreases as the average number of concurrently dispatched instructions increases. One particular implementation of the reorder buffer includes a future file. The future file comprises a storage location corresponding to each register within the microprocessor.

Abstract: A method for controlling the execution of a microprocessor to cause it to execute a NOP instruction for a programmable number of sequential cycles. A NOP instruction is provided, that includes a predetermined OP code field identifying the NOP instruction as a programmably multiple NOP instruction. A predetermined count field is provided, representing the number of sequential cycles in which a NOP operation is to be performed by said microprocessor. The NOP instruction OP code field is read, as is the NOP instruction count field. In response thereto, a NOP operation is performed for the number of sequential cycles represented by said NOP instruction count field.

Abstract: A pipelined instruction dispatch or grouping circuit allows instruction dispatch decisions to be made over multiple processor cycles. In one embodiment, the grouping circuit performs resource allocation and data dependency checks on an instruction group, based on a state vector which includes representation of source and destination registers of instructions within said instruction group and corresponding state vectors for instruction groups of a number of preceding processor cycles.

Abstract: A microprocessor includes an instruction alignment unit for locating instructions and conveying the located instructions to a set of decode units. The instruction alignment unit includes dual instruction queues. The first instruction queue receives instruction blocks fetched from the instruction cache. The instruction alignment unit uses instruction identification information provided by the instruction cache to select instructions from the first instruction queue for conveyance to the second instruction queue. Additionally, the instruction alignment unit applies a predetermined selection criteria to the instructions within the second instruction queue in order to select instructions for dispatch to the decode units. Selection logic for the first instruction queue need not consider the type of instruction, etc., in selecting instructions for conveyance to the second instruction queue. Selection logic for the second instruction queue considers instruction type, etc.