Abstract: In a superscalar processor for fetching a prescribed peak number of instructions in parallel in each period until such instructions are fetched to a predetermined peak number, such as ten, an instruction parallel issue and execution administrating device comprises a forward map buffer for a forward map indicative of a result of each instruction for use as an operand by which one of other instructions of the predetermined peak number. The forward map is developed before the result is actually produced and is used, after the actual production, to indicate which one of such results should be used as the operand by the above-mentiond one of the other instructions.

Abstract: A microprocessor including a context file configured to store multiple contexts is provided. The microprocessor may execute multiple threads, each thread having its own context within the microprocessor. In one embodiment, the present microprocessor is capable of executing at least two threads concurrently: a task and an interrupt service routine. Interrupt service routines may be executed without disturbing a task's context and without performing a context save operation. Instead, the interrupt service routine accesses a context which is independent of the context of the task. In another embodiment, the context file includes multiple interrupt service routine contexts. Multiple ISR context storages allow for nested interrupts to be performed concurrently. In yet another embodiment, the microprocessor is configured to execute multiple tasks and multiple interrupt service routines concurrently.

Abstract: A process is provided for determining the beginning and ending of each instruction of a variable length instruction. Data lines are stored in a first memory area which illustratively is an instruction cache. Each data line comprises a sequence of data words that are stored at sequential address in a main memory. The data lines contain multiple encoded variable length instructions that are contiguously stored in the main memory. Multiple indicators are stored in a second memory area, including one indicator associated with each data word of the data lines stored in the first memory area. Each indicator indicates whether or not its associated data word is the initial data word of a variable length instruction. A sequence of data words may be fetched from the cache. The fetched sequence of data words includes a starting data word and at least the number of data words in the longest permissible instruction. Plural indicators (i.e.

Abstract: A performance monitor implementing a plurality of counters counts several events to provide an instruction fetch bandwidth analysis, a cycles per instruction (CPI) infinite and finite analysis, an operand fetch bandwidth analysis, an instruction parallelism analysis, and a trailing edge analysis. Such analyses are performed on the performance of a data processing system in order that the designer may develop an improved processor architecture.

Abstract: In a VLIW processor that has an instruction issue register, functional units, and a multiport register file, a portion or all of the read crossbar is eliminated.

Abstract: An image processing system having programmable keys for recording frequently used procedures is disclosed. The scanner comprises a scanning module for scanning an document, a plurality of programmable keys for recording frequently used procedures and a program key. The computer comprises a script file generation program for generating a script file of the programmable key. The script file is generated by using the following steps: (1) press the program key to generate a script file, (2) press a programmable key to relate the script file to the programmable key, (3) generate a plurality of control signals sequentially through various control keys of the scanner, (4) store the control signals in the script file, and (5) press the program key to complete the script file.

Abstract: An information processing apparatus in which instructions are processed one by one conceptually and results thereof are conceptually orderly written into a memory comprises an instruction control circuit capable of decoding M instructions and reading operands in parallel, N (N.gtoreq.M) execution circuits capable of executing a plurality of instructions mutually in parallel, a detection circuit for determining whether all of M execution circuits of the N execution circuits required by the M instructions decoded by the instruction control circuit are vacant or not, and a reserve circuit for reserving the execution of the M decoded instruction while the detection fails to detect sufficient vacancy.

Abstract: A method and system for constructing a program are provided. According to the method, each of a plurality of instructions are assigned to at least one of a plurality of threads. The plurality of threads include first, second, and third threads, where the third thread follows the first thread and precedes the second thread in a logical program order. A data structure associated with the first thread is then constructed. The data structure includes an indication that execution of the second thread is to be initiated prior to initiation of execution of the third thread. According to one embodiment, the indication within the data structure is a pointer that specifies a second data structure associated with the second thread.