Scoreboarding, Reservation Station, Or Aliasing Patents (Class 712/217)
  • Patent number: 10684858
    Abstract: Disclosed embodiments relate to an indirect memory fetch (IMF) unit. In one example, an apparatus includes circuitry to fetch and decode an instruction specifying a sparse operand array including N operands, and an index array including N contiguously-addressed indices. The apparatus further includes a processing engine associated with an IMF unit to respond to the decoded instruction by initializing the IMF unit to fetch the N operands in order, probing the IMF unit to determine that a fetched operand is ready to retrieve, retrieving the fetched operand from the IMF unit, and repeating the probing and retrieving until all N operands have been retrieved. The IMF unit, independent of the processing engine, is to fetch the N contiguously-addressed indices from the index array, use the N fetched indices to calculate memory addresses for the N operands, and issue a plurality of read requests to fetch the N operands in order.
    Type: Grant
    Filed: June 1, 2018
    Date of Patent: June 16, 2020
    Assignee: Intel Corporation
    Inventors: Stijn Eyerman, Wim Heirman, Kristof Du Bois, Ibrahim Hur, Joshua B. Fryman
  • Patent number: 10684861
    Abstract: The present disclosure relates to a method for instruction processing with a processor having multiple execution units. The processor includes a dependency cache containing instructions in association with respective execution unit indicators. The method includes: tracking the number of dependent instructions currently assigned to each execution unit of the processor respectively. In response to receiving an instruction of a dependency chain, the execution unit assigned to a previous instruction of the dependency chain on which depends the received instruction may be identified in the dependency cache. In case more than a predefined maximum number of dependent instructions of at least one dependency chain is currently assigned to the identified execution unit, another execution unit of the processor may be selected for scheduling the received instruction, otherwise the received instruction may be scheduled on the identified execution unit.
    Type: Grant
    Filed: September 25, 2017
    Date of Patent: June 16, 2020
    Assignee: International Business Machines Corporation
    Inventors: Peter Altevogt, Cédric Lichtenau, Thomas Pflueger
  • Patent number: 10664368
    Abstract: A method for modifying a configuration of a storage system. The method includes a computer processor querying a network-accessible computing system to obtain information associated with an executing application that utilizes a storage system for a process of data mirroring. The method further includes identifying a set of parameters associated with a copy program executing within a logical partition (LPAR) of the storage system based on the obtained information, where the set of parameters dictates a number of reader tasks utilized by the copy program, where the copy program is a program associated with the process for data mirroring from the network-accessible computing system to the storage system. The method further includes executing the dictated number of reader tasks for the process of mirroring data associated with the executing application, from the network-accessible computing system to the storage system.
    Type: Grant
    Filed: November 30, 2017
    Date of Patent: May 26, 2020
    Assignee: International Business Machines Corporation
    Inventors: Gregory E. McBride, Dash Miller, Miguel Perez, David C. Reed
  • Patent number: 10649781
    Abstract: The present disclosure relates to a method for instruction processing with a processor having multiple execution units. The processor includes a dependency cache containing instructions in association with respective execution unit indicators. The method includes: tracking the number of dependent instructions currently assigned to each execution unit of the processor respectively. In response to receiving an instruction of a dependency chain, the execution unit assigned to a previous instruction of the dependency chain on which depends the received instruction may be identified in the dependency cache. In case more than a predefined maximum number of dependent instructions of at least one dependency chain is currently assigned to the identified execution unit, another execution unit of the processor may be selected for scheduling the received instruction, otherwise the received instruction may be scheduled on the identified execution unit.
    Type: Grant
    Filed: December 15, 2017
    Date of Patent: May 12, 2020
    Assignee: International Business Machines Corporation
    Inventors: Peter Altevogt, Cédric Lichtenau, Thomas Pflueger
  • Patent number: 10628157
    Abstract: A processing pipeline has at least one front end stage for issuing micro-operations for execution in response to program instructions, and an execute stage for performing data processing in response to the micro-operations. At least one predicate register stores at least one predicate value. In response to a predicated vector instruction for triggering execution of two or more lanes of processing, the at least one front end stage issues at least one micro-operation to control the execute stage to mask an effect of a lane of processing indicated as disabled by a target predicate value. One of the front end stages may perform an early predicate lookup of the target predicate value to vary in dependence on the early predicate lookup, which micro-operations are issued to the execute store for a predicated vector instruction.
    Type: Grant
    Filed: April 21, 2017
    Date of Patent: April 21, 2020
    Assignee: ARM Limited
    Inventors: Alejandro Rico Carro, Lee Evan Eisen
  • Patent number: 10613868
    Abstract: Techniques disclosed herein describe a variable latency pipe for interleaving instruction tags in a processor. According to one embodiment presented herein, an instruction tag is associated with an instruction upon issue of the instruction from the issue queue. One of a plurality of positions in the latency pipe is determined. The pipe stores one or more instruction tags, each associated with a respective instruction. The pipe also stores the instruction tags in a respective position based on the latency of each respective instruction. The instruction tag is stored at the determined position in the pipe.
    Type: Grant
    Filed: June 30, 2015
    Date of Patent: April 7, 2020
    Assignee: International Business Machines Corporation
    Inventors: Salma Ayub, Josh Bowman, Sundeep Chadha, Dhivya Jeganathan, Cliff Kucharski, Dung Q. Nguyen
  • Patent number: 10599853
    Abstract: A pluggable trust architecture addresses the problem of establishing trust in hardware. The architecture has low impact on system performance and comprises a simple, user-supplied, and pluggable hardware element. The hardware element physically separates the untrusted components of a system from peripheral components that communicate with the external world. The invention only allows results of correct execution of software to be communicated externally.
    Type: Grant
    Filed: October 21, 2015
    Date of Patent: March 24, 2020
    Assignee: Princeton University
    Inventors: David I. August, Soumyadeep Ghosh, Jordan Fix
  • Patent number: 10565670
    Abstract: A processing apparatus is described. The apparatus includes a graphics processing unit (GPU), including a plurality of execution units to process graphics context data and a register file having a plurality of registers to store the graphics context data; and register renaming logic to facilitate dynamic renaming of the plurality of registers by logically partitioning the plurality of registers in the register file into a set of fixed registers and a set of shared registers.
    Type: Grant
    Filed: September 30, 2016
    Date of Patent: February 18, 2020
    Assignee: INTEL CORPORATION
    Inventors: Kaiyu Chen, Guei-Yuan Lueh, Subramaniam Maiyuran
  • Patent number: 10564975
    Abstract: A global front end scheduler to schedule instruction sequences to a plurality of virtual cores implemented via a plurality of partitionable engines. The global front end scheduler includes a thread allocation array to store a set of allocation thread pointers to point to a set of buckets in a bucket buffer in which execution blocks for respective threads are placed, a bucket buffer to provide a matrix of buckets, the bucket buffer including storage for the execution blocks, and a bucket retirement array to store a set of retirement thread pointers that track a next execution block to retire for a thread.
    Type: Grant
    Filed: January 30, 2018
    Date of Patent: February 18, 2020
    Assignee: INTEL CORPORATION
    Inventor: Mohammad Abdallah
  • Patent number: 10552164
    Abstract: Sharing snapshots between restoration and recovery. A snapshot to be used for recovery and restoration is obtained. The snapshot includes restoration state for a plurality of architected registers. The plurality of architected registers includes one or more architected registers associated with an instruction to alter an execution path and one or more architected registers associated with a save request. At least one architected register of the plurality of architected registers is restored, based on a request. The request is a recovery request to recover at least one architected register associated with the instruction to alter the execution path or a restoration request to restore at least one architected register associated with the save request.
    Type: Grant
    Filed: April 18, 2017
    Date of Patent: February 4, 2020
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Michael K. Gschwind, Valentina Salapura, Chung-Lung K. Shum, Timothy J. Slegel
  • Patent number: 10545763
    Abstract: Detecting data dependencies of instructions associated with threads in a simultaneous multithreading (SMT) scheme is disclosed, including: dividing a plurality of comparators of an SMT-enabled device into groups of comparators corresponding to respective ones of threads associated with the SMT-enabled device; simultaneously distributing a first set of instructions associated with a first thread of the plurality of threads to a corresponding first group of comparators from the plurality of groups of comparators and distributing a second set of instructions associated with a second thread of the plurality of threads to a corresponding second group of comparators from the plurality of groups of comparators; and simultaneously performing data dependency detection on the first set of instructions associated with the first thread using the corresponding first group of comparators and performing data dependency detection on the second set of instructions associated with the second thread using the corresponding seco
    Type: Grant
    Filed: May 6, 2015
    Date of Patent: January 28, 2020
    Assignee: Alibaba Group Holding Limited
    Inventors: Ling Ma, Sihai Yao, Lei Zhang
  • Patent number: 10545766
    Abstract: Register restoration using transactional memory register snapshots. An indication that a transaction is to be initiated is obtained. Based on obtaining the indication, a determination is made as to whether register restoration is in active use. Based on obtaining the indication and determining register restoration is in active use, register restoration is deactivated. To recover one or more architected registers of the transaction, a transactional rollback snapshot is created.
    Type: Grant
    Filed: April 18, 2017
    Date of Patent: January 28, 2020
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Michael K. Gschwind, Valentina Salapura
  • Patent number: 10528354
    Abstract: A processor with multiple execution units for instruction processing is provided. The processor comprises an instruction decode and issue logic and a control logic for resolving register access conflicts between subsequent instructions and a dependency cache, which comprises a receiving logic for receiving an execution unit indicator indicative of the execution unit the instruction is planned to be executed on, a storing logic responsive to the receiving logic for storing the received execution unit indicator, and a retrieving logic responsive to a request from the instruction decode and issue logic for providing the stored execution unit indicator for an instruction. The instruction decode and issue logic is adapted for requesting execution unit indicator for an instruction from the dependency cache and to assign the instruction to one respective of the execution units dependent on the execution unit indicator received from the dependency cache.
    Type: Grant
    Filed: March 10, 2016
    Date of Patent: January 7, 2020
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Peter Altevogt, Cedric Lichtenau, Thomas Pflueger
  • Patent number: 10514921
    Abstract: A method for speeding the re-use of Physical Register Names (PRNs), and hence the processor registers, in a processor. The method involves returning a PRN to a freelist for reuse when it is obsolete even when it is not complete, and blocking writes to the Processor Register File (PRF) by obsolete realms.
    Type: Grant
    Filed: September 5, 2017
    Date of Patent: December 24, 2019
    Assignee: Qualcomm Incorporated
    Inventors: Tejaswi Talluru, Rodney Smith, Yusuf Cagatay Tekmen, Kiran Seth, Daniel Higdon, Jeffery Michael Schottmiller, Andrew Irwin
  • Patent number: 10503505
    Abstract: A processor executes a mask update instruction to perform updates to a first mask register and a second mask register. A register file within the processor includes the first mask register and the second mask register. The processor includes execution circuitry to execute the mask update instruction. In response to the mask update instruction, the execution circuitry is to invert a given number of mask bits in the first mask register, and also to invert the given number of mask bits in the second mask register.
    Type: Grant
    Filed: April 2, 2018
    Date of Patent: December 10, 2019
    Assignee: Intel Corporation
    Inventors: Mikhail Plotnikov, Andrey Naraikin, Christopher J. Hughes
  • Patent number: 10503514
    Abstract: A method of managing a reduced size register view data structure in a processor, where the method includes receiving an incoming instruction sequence using a global front end, grouping instructions from the incoming instruction sequence to form instruction blocks, populating a register view data structure, wherein the register view data structure stores register information references by the instruction blocks as a set of register templates, generating a set of snapshots of the register templates to reduce a size of the register view data structure, and tracking a state of the processor to handle a branch miss-prediction using the register view data structure in accordance with execution of the instruction blocks.
    Type: Grant
    Filed: November 7, 2017
    Date of Patent: December 10, 2019
    Assignee: INTEL CORPORATION
    Inventor: Mohammad Abdallah
  • Patent number: 10488911
    Abstract: A method of allocating registers, includes for each of a plurality of live ranges of variables, calculating an energy saving value of each of the plurality of live ranges of the variables; classifying the plurality of live ranges of the variables into a plurality of queues according to the energy saving values of the plurality of live ranges of the variables; and assigning the plurality of live ranges of the variables in the plurality of queues into a plurality of registers.
    Type: Grant
    Filed: November 1, 2016
    Date of Patent: November 26, 2019
    Assignees: National Taiwan University, MEDIATEK INC.
    Inventors: Yuan-Shin Hwang, Jenq-Kuen Lee, Shao-CHung Wang, Li-Chen Kan
  • Patent number: 10417001
    Abstract: Embodiments of an invention for a physical register table for eliminating move instructions are disclosed. In one embodiment, a processor includes a physical register file, a register allocation table, and a physical register table. The register allocation table is to store mappings of logical registers to physical registers. The physical register table is to store entries including pointers to physical registers in the mappings. The number of entry locations in the physical register table is less than the number of physical registers in the physical register file.
    Type: Grant
    Filed: December 27, 2012
    Date of Patent: September 17, 2019
    Assignee: Intel Corporation
    Inventors: Jonathan D. Combs, Venkateswara R. Madduri
  • Patent number: 10394565
    Abstract: Managing an issue queue for fused instructions and paired instructions in a microprocessor including dispatching a fused instruction to a first entry in a double issue queue; dispatching two paired instructions to a second entry in the double issue queue; issuing the fused instruction during a single cycle to an execution unit in response to determining, by the issue queue logic, that the fused instruction is ready to issue; and issuing, by the issue queue logic, the first instruction of the two paired instructions to the execution unit in response to determining, by the issue queue logic, that the first instruction of the two paired instructions is ready to issue.
    Type: Grant
    Filed: October 27, 2017
    Date of Patent: August 27, 2019
    Assignee: International Business Machines Corporation
    Inventors: Michael J. Genden, Hung Q. Le, Dung Q. Nguyen, Brian W. Thompto
  • Patent number: 10387147
    Abstract: Managing an issue queue for fused instructions and paired instructions in a microprocessor including dispatching a fused instruction to a first entry in a double issue queue; dispatching two paired instructions to a second entry in the double issue queue; issuing the fused instruction during a single cycle to an execution unit in response to determining, by the issue queue logic, that the fused instruction is ready to issue; and issuing, by the issue queue logic, the first instruction of the two paired instructions to the execution unit in response to determining, by the issue queue logic, that the first instruction of the two paired instructions is ready to issue.
    Type: Grant
    Filed: August 2, 2017
    Date of Patent: August 20, 2019
    Assignee: International Business Machines Corporation
    Inventors: Michael J. Genden, Hung Q. Le, Dung Q. Nguyen, Brian W. Thompto
  • Patent number: 10374981
    Abstract: An interface circuit is disclosed for the transfer of data from a synchronous circuit, with multiple source elements, to an asynchronous circuit. Data from the synchronous circuit is received into a memory in the interface circuit. The data in the memory is then sent to the asynchronous circuit based on an instruction in a circular buffer that is part of the interface circuit. Processing elements within the interface circuit execute instructions contained within the circular buffer. The circular buffer rotates to provide new instructions to the processing elements. Flow control paces the data from the synchronous circuit to the asynchronous circuit.
    Type: Grant
    Filed: August 2, 2016
    Date of Patent: August 6, 2019
    Assignee: Wave Computing, Inc.
    Inventor: Christopher John Nicol
  • Patent number: 10365928
    Abstract: Embodiments of the invention are directed to methods for handling scratch registers in a processor. The method includes receiving a cracked instruction in an instruction dispatch unit of the processor. The method further includes decoding the cracked instruction into a group of micro-operations. Based on a determination that the instruction group uses a scratch register, determining if the scratch register is used in other groups of micro-operations. Based on a determination that the scratch register is not used in other instruction groups, allocating a physical register for use as the scratch register without creating a mapper entry for the scratch register.
    Type: Grant
    Filed: November 1, 2017
    Date of Patent: July 30, 2019
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Gregory W. Alexander, David S. Hutton, Christian Jacobi, Edward T. Malley, Anthony Saporito
  • Patent number: 10353680
    Abstract: A system for an agnostic runtime architecture. The system includes a system emulation/virtualization converter, an application code converter, and a converter wherein a system emulation/virtualization converter and an application code converter implement a system emulation process, and wherein the system converter implements a system and application conversion process for executing code from a guest image, wherein the system converter or the system emulator. The system further includes a run ahead run time guest such an conversion/decoding process, and a prefetching process where guest code is pre-fetched from the target of guest branches in an instruction sequence.
    Type: Grant
    Filed: July 23, 2015
    Date of Patent: July 16, 2019
    Assignee: Intel Corporation
    Inventor: Mohammad Abdallah
  • Patent number: 10346171
    Abstract: A processor of an aspect includes a plurality of physical storage locations, and a register rename unit. The register rename unit includes a first register rename storage structure that is to store a given physical storage location identifier, which is to identify a physical storage location of the plurality of physical storage locations, and that is to store a corresponding given one or more redundant bits. The register rename unit also includes a second register rename storage structure. The register rename unit also includes a first conductive path coupling the first and second register rename storage structures. The first conductive path is to convey the given one or more redundant bits end-to-end from the first register rename storage structure to the second register rename storage structure. Other processors are also disclosed, as well as methods and systems.
    Type: Grant
    Filed: January 10, 2017
    Date of Patent: July 9, 2019
    Assignee: Intel Corporation
    Inventors: Ron Gabor, Yiannakis Sazeides, Arkady Bramnik
  • Patent number: 10346173
    Abstract: An instruction buffer for a processor configured to execute multiple threads is disclosed. The instruction buffer is configured to receive instructions from a fetch unit and provide instructions to a selection unit. The instruction buffer includes one or more memory arrays comprising a plurality of entries configured to store instructions and/or other information (e.g., program counter addresses). One or more indicators are maintained by the processor and correspond to the plurality of threads. The one or more indicators are usable such that for instructions received by the instruction buffer, one or more of the plurality entries of a memory array can be determined as a write destination for the received instructions, and for instructions to be read from the instruction buffer (and sent to a selection unit), one or more entries can be determined as the correct source location from which to read.
    Type: Grant
    Filed: March 7, 2011
    Date of Patent: July 9, 2019
    Assignee: Oracle International Corporation
    Inventors: Jama I. Barreh, Robert T. Golla, Manish K. Shah
  • Patent number: 10331583
    Abstract: A processing device for executing distributed memory operations using spatial processing units (SPU) connected by distributed channels is disclosed. A distributed channel may or may not be associated with memory operations, such as load operations or store operations. Distributed channel information is obtained for an algorithm to be executed by a group of spatially distributed processing elements. The group of spatially distributed processing elements can be connected to a shared memory controller. For each distributed channel in the distributed channel information, one or more of the group of spatially distributed processing elements may be associated with the distributed channel based on the algorithm. By associating the spatially distributed processing elements to a distributed channel, the functionality of the processing element can vary depending on the algorithm mapped onto the SPU.
    Type: Grant
    Filed: September 26, 2013
    Date of Patent: June 25, 2019
    Assignee: Intel Corporation
    Inventors: Bushra Ahsan, Michael C. Adler, Neal C. Crago, Joel S. Emer, Aamer Jaleel, Angshuman Parashar, Michael I. Pellauer
  • Patent number: 10331361
    Abstract: Techniques are disclosed relating to self-addressing memory. In one embodiment, an apparatus includes a memory and addressing circuitry coupled to or comprised in the memory. In this embodiment, the addressing circuitry is configured to receive memory access requests corresponding to a specified sequence of memory accesses. In this embodiment, the memory access requests do not include address information. In this embodiment, the addressing circuitry is further configured to assign addresses to the memory access requests for the specified sequence of memory accesses. In some embodiments, the apparatus is configured to perform the memory access requests using the assigned addresses.
    Type: Grant
    Filed: January 3, 2017
    Date of Patent: June 25, 2019
    Assignee: National Instruments Corporation
    Inventors: Tai A. Ly, Swapnil D. Mhaske, Hojin Kee, Adam T. Arnesen, David C. Uliana, Newton G. Petersen
  • Patent number: 10324777
    Abstract: An example device may include processing circuitry and a management controller. The processing circuitry may include a communications interface that includes a first register and a second register. The first register may include a freshness bit and a number of first data bits. The second register may include a number of second data bits that correspond, respectively, to the first data bits. The processing circuitry may write variously to the first data bits in response to detected events, set the freshness bit in response to the management controller reading the first data bits, and reset the freshness bit if any of the first data bits are written to. The management controller may read the first data bits, perform predetermined processing based thereon, write to the second data bits based on the predetermined processing, and request a register transfer.
    Type: Grant
    Filed: October 27, 2016
    Date of Patent: June 18, 2019
    Assignee: HEWLETT PACKARD ENTERPRISE DEVELOPMENT LP
    Inventors: Christoph L. Schmitz, Thomas Donald Rhodes, Nicholas Mark Hawkins, Binh Nguyen, Wayne Hsu
  • Patent number: 10318289
    Abstract: A compute instruction to be executed is to use a memory operand in a computation. An address associated with the memory operand is to be used to locate a portion of memory from which data is to be obtained and placed in the memory operand. A determination is made as to whether the portion of memory extends across a specified memory boundary. Based on the portion of memory extending across the specified memory boundary, the portion of memory includes a plurality of memory units and a check is made as to whether at least one specified memory unit is accessible and whether at least one specified memory unit is inaccessible.
    Type: Grant
    Filed: November 14, 2015
    Date of Patent: June 11, 2019
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Michael K. Gschwind, Brett Olsson
  • Patent number: 10318432
    Abstract: A technique for operating a lower level cache memory of a data processing system includes receiving an operation that is associated with a first thread. Logical partition (LPAR) information for the operation is used to limit dependencies in a dependency data structure of a store queue of the lower level cache memory that are set and to remove dependencies that are otherwise unnecessary.
    Type: Grant
    Filed: July 9, 2018
    Date of Patent: June 11, 2019
    Assignee: International Business Machines Corporation
    Inventors: Guy L. Guthrie, Hugh Shen, Derek E. Williams
  • Patent number: 10303481
    Abstract: A processor with multiple execution units for instruction processing is provided. The processor comprises an instruction decode and issue logic and a control logic for resolving register access conflicts between subsequent instructions and a dependency cache, which comprises a receiving logic for receiving an execution unit indicator indicative of the execution unit the instruction is planned to be executed on, a storing logic responsive to the receiving logic for storing the received execution unit indicator, and a retrieving logic responsive to a request from the instruction decode and issue logic for providing the stored execution unit indicator for an instruction. The instruction decode and issue logic is adapted for requesting execution unit indicator for an instruction from the dependency cache and to assign the instruction to one respective of the execution units dependent on the execution unit indicator received from the dependency cache.
    Type: Grant
    Filed: December 2, 2015
    Date of Patent: May 28, 2019
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Peter Altevogt, Cedric Lichtenau, Thomas Pflueger
  • Patent number: 10296349
    Abstract: Data processing circuitry comprises allocation circuitry to allocate one or more source and destination processor registers, of a set of processor registers each defined by a respective register index, to a processor instruction for use in execution of that processor instruction and to associate, with the processor instruction, information to indicate the register index of the allocated source and destination processor registers; the avocation circuitry being selectively operable to allocate, to a processor instruction, a group of destination processor registers having a subset of their register indices in common and to associate, with the processor instruction, information to indicate the register index of one processor register of the group and identifying information to identify one or more bits of the register index which differ between the processor registers in the allocated group of processor registers.
    Type: Grant
    Filed: January 7, 2016
    Date of Patent: May 21, 2019
    Assignee: ARM Limited
    Inventors: Vladimir Vasekin, Antony John Penton, Chiloda Ashan Senarath Pathirane, Andrew James Antony Lees
  • Patent number: 10289469
    Abstract: Systems and methods for enhancing reliability are presented. In one embodiment, a system comprises a processor configured to execute program instructions and contemporaneously perform reliability enhancement operations (e.g., fault checking, error mitigation, etc.) incident to executing the program instructions. The fault checking can include: identifying functionality of a particular portion of the program instructions; speculatively executing multiple sets of operations contemporaneously; and comparing execution results from the multiple sets of operations. The multiple sets of operations are functional duplicates of the particular portion of the program instructions. If the execution results have a matching value, then the value can be made architecturally visible. If the execution results do not have a matching value, the system can be put in a safe mode. An error mitigation operation can be performed can include a corrective procedure. The corrective procedure can include rollback to a known valid state.
    Type: Grant
    Filed: October 28, 2016
    Date of Patent: May 14, 2019
    Assignee: Nvidia Corporation
    Inventors: Nick Fortino, Fred Gruner, Ben Hertzberg
  • Patent number: 10282224
    Abstract: A method, apparatus, and system for utilizing a register virtualization mapping to improve defense against return-oriented programming-based attacks is disclosed. A register virtualization mapping, which is bijection between nominal registers and physical registers, is generated for a subroutine call when the subroutine call is detected. The register virtualization mapping is applied to instructions within the subroutine call. The register virtualization mapping is stopped for the subroutine call at the return of the subroutine call.
    Type: Grant
    Filed: September 22, 2015
    Date of Patent: May 7, 2019
    Assignee: QUALCOMM Incorporated
    Inventors: Olivier Jean Benoit, Rosario Cammarota
  • Patent number: 10275255
    Abstract: A method for dependency broadcasting through a source organized source view data structure.
    Type: Grant
    Filed: March 14, 2014
    Date of Patent: April 30, 2019
    Assignee: Intel Corporation
    Inventor: Mohammad Abdallah
  • Patent number: 10255071
    Abstract: Method and system for managing a speculative transaction in a processing unit is provided. The speculative transaction is initiated by dispatching a first instruction indicating start of the speculative transaction. One or more register file (RF) entries are marked as pre-transaction memory (PTM), in response to the initiating. At least one second instruction targeting at least one of the marked RF entries is dispatched, while the transaction is active, wherein the at least one second instruction writes new result data into the at least one RF entry. Previous result data evicted from the at least one RF entry by the new result data, is saved into a history buffer (HB) entry. The HB entry is marked as PTM, in response to the saving, wherein the processing unit, upon detecting a trigger, is rolled back to a state before the initiating the transaction by restoring the previous result data to the at least one RF entry.
    Type: Grant
    Filed: October 14, 2015
    Date of Patent: April 9, 2019
    Assignee: International Business Machines Corporation
    Inventors: Salma Ayub, Susan E. Eisen, Glenn O. Kincaid, Cliff Kucharski, Christopher M. Mueller, Dung Q. Nguyen, David R. Terry
  • Patent number: 10248425
    Abstract: A processor including physical registers, a reorder buffer, a master free list, a slave free list, a master recycle circuit, and a slave recycle circuit. The reorder buffer includes instruction entries in which each entry stores physical register indexes for recycling physical registers. The reorder buffer retires up to N instructions in each processor cycle. Each master and slave free list includes N input ports and stores physical register indexes, in which the master free list stores indexes of physical registers to be allocated to instructions being issued. When an instruction is retired, the master recycle circuit routes a first physical register index stored in an instruction entry of the instruction to an input port of the master free list, and the slave recycle circuit routes a second physical register index stored in the instruction entry of the instruction to an input port of the slave free list.
    Type: Grant
    Filed: August 12, 2016
    Date of Patent: April 2, 2019
    Assignee: VIA ALLIANCE SEMICONDUCTOR CO., LTD.
    Inventor: Xiaolong Fei
  • Patent number: 10228948
    Abstract: A computer obtains invalidation information that shows ignorable data dependency relationships from among a plurality of data dependency relationships, and extracts a synchronous-dependent relationship from among the ignorable data dependency relationships that are shown as a write-write to the same data by the invalidation information. Then, the computer generates a parallel program for maximizing the number of parallelized macro tasks by ignoring other data dependency relationships other than the extracted synchronous-dependent relationship while preventing simultaneous write to the same data by two macro tasks having the synchronous-dependent relationship.
    Type: Grant
    Filed: June 6, 2017
    Date of Patent: March 12, 2019
    Assignee: DENSO CORPORATION
    Inventor: Kenichi Mineda
  • Patent number: 10198266
    Abstract: A method for populating a source view data structure by using register template snapshots. The method includes receiving an incoming instruction sequence using a global front end; grouping the instructions to form instruction blocks; using a plurality of register templates to track instruction destinations and instruction sources by populating the register template with block numbers corresponding to the instruction blocks, wherein the block numbers corresponding to the instruction blocks indicate interdependencies among the blocks of instructions; populating a source view data structure, wherein the source view data structure stores sources corresponding to the instruction blocks as recorded by the plurality of register templates; and determining which of the plurality of instruction blocks are ready for dispatch by using the populated source view data structure.
    Type: Grant
    Filed: January 17, 2017
    Date of Patent: February 5, 2019
    Assignee: Intel Corporation
    Inventor: Mohammad Abdallah
  • Patent number: 10191724
    Abstract: Methods and apparatus relating to techniques for compiler-based instruction scoreboarding. In an example, an apparatus comprises logic, at least partially comprising hardware logic, to remove unnecessary dependence edges from a data dependency graph, partition the data dependency graph into a plurality of sub-graphs, determine a live range for each of the plurality of sub-graphs, and assign a scoreboard entry to each of the plurality of sub-graphs, wherein sub-graphs which have interfering live ranges are assigned different scoreboard entries. Other embodiments are also disclosed and claimed.
    Type: Grant
    Filed: October 21, 2016
    Date of Patent: January 29, 2019
    Assignee: INTEL CORPORATION
    Inventors: Bu Qi Cheng, Wei-Yu Chen, Guei-Yuan Lueh
  • Patent number: 10169045
    Abstract: A method for dependency broadcasting through a source organized source view data structure is disclosed. The method comprises receiving an incoming instruction sequence using a global front end and grouping the instructions to form instruction blocks. Further, the method comprises populating the register template with block numbers corresponding to the instruction blocks, wherein the block numbers corresponding to the instruction blocks indicate interdependencies among the instruction blocks wherein an incoming instruction block writes its respective block number into fields of the register template corresponding to destination registers referred to by the incoming instruction block. The method also comprises populating a source organized source view data structure, wherein the source view data structure stores the instruction sources corresponding to the instruction blocks as read from the register template by incoming instruction blocks.
    Type: Grant
    Filed: January 17, 2017
    Date of Patent: January 1, 2019
    Assignee: Intel Corporation
    Inventor: Mohammad Abdallah
  • Patent number: 10140128
    Abstract: A parallelized multiple dispatch ordered queue including an ordered queue, qualify logic, ordered select logic, and dispatch logic. The ordered queue stores candidates in order from oldest to youngest into multiple entries. The ordered queue is divided into N groups in which an i'th group includes every i'th entry of every N entries of the ordered queue, wherein i is an integer less than or equal to N. The qualify logic determines whether any candidate is ready to be dispatched. The ordered select logic respectively determines the oldest candidate in each group that is ready to be dispatched. The dispatch logic dispatches the oldest ready candidates in parallel. The shift logic shifts the stored candidates in the ordered queue to fill any vacant entries between remaining ones of the stored candidates without changing an order of the remaining ones of the stored candidates in the ordered queue. The ordered queue may have any size or depth and N is any suitable integer determining the number of candidates (e.g.
    Type: Grant
    Filed: March 10, 2015
    Date of Patent: November 27, 2018
    Assignee: VIA ALLIANCE SEMICONDUCTOR CO., LTD.
    Inventors: Qianli Di, Jianbin Wang, Weili Li, Xiaoyuan Yu, Xin Yu Gao
  • Patent number: 10133620
    Abstract: A processor includes physical storage locations, and a register rename unit that includes a plurality of register rename storage structures. At a given time, each of a complete group of physical storage location identifiers is to be stored in one, but only one, of the plurality of register rename storage structures, unless there is an error. Each of the complete group of physical storage location identifiers is to identify a different one of the physical storage locations. The register rename unit is to detect an error when a first value, which is to be equal to an operation on the complete group of the physical storage location identifiers with no errors, is inconsistent with a second value. The second value is to represent the operation on all physical storage location identifiers that are to be stored in the plurality of register rename storage structures at the given time.
    Type: Grant
    Filed: January 10, 2017
    Date of Patent: November 20, 2018
    Assignee: Intel Corporation
    Inventors: Alex Gerber, Yiannakis Sazeides, Arkady Bramnik, Ron Gabor
  • Patent number: 10127098
    Abstract: An apparatus and method for recovering the functionality of central processing unit core are disclosed herein. The apparatus for recovering the functionality of a central processing unit (CPU) core includes a functionality recovery buffer and a functionality recovery module unit. The functionality recovery buffer temporarily stores a value, to be stored in a register storage unit, in response to a write operation. The functionality recovery module unit performs the recovery of functionality by controlling the functionality recovery buffer when receiving a signal, indicating that a failure has been detected, from the outside.
    Type: Grant
    Filed: January 27, 2016
    Date of Patent: November 13, 2018
    Assignee: ELECTRONICS AND TELECOMMUNICATIONS RESEARCH INSTITUTE
    Inventor: Young-Su Kwon
  • Patent number: 10055224
    Abstract: A method and apparatus for reconfiguring hardware structures to pipeline the execution of multiple special purpose hardware implemented functions, without saving intermediate results to memory, is provided. Pipelining functions in a program is typically performed by a first function saving its results (the “intermediate results”) to memory, and a second function subsequently accessing the memory to use the intermediate results as input. Saving and accessing intermediate results stored in memory incurs a heavy performance penalty, requires more power, consumes more memory bandwidth, and increases the memory footprint. Due to the ability to redirect the input and output of the hardware structures, intermediate results are passed directly from one special purpose hardware implemented function to another without storing the intermediate results in memory.
    Type: Grant
    Filed: December 10, 2015
    Date of Patent: August 21, 2018
    Assignee: Oracle International Corporation
    Inventors: Kathirgamar Aingaran, Garret F. Swart
  • Patent number: 10019374
    Abstract: A technique for operating a lower level cache memory of a data processing system includes receiving an operation that is associated with a first thread. Logical partition (LPAR) information for the operation is used to limit dependencies in a dependency data structure of a store queue of the lower level cache memory that are set and to remove dependencies that are otherwise unnecessary.
    Type: Grant
    Filed: April 28, 2016
    Date of Patent: July 10, 2018
    Assignee: International Business Machines Corporation
    Inventors: Guy L. Guthrie, Hugh Shen, Derek E. Williams
  • Patent number: 10002020
    Abstract: A data processing apparatus and method of data processing are provided, which relate to the operation of a processor which maintains a call stack in dependence on the data processing instructions executed. The processor is configured to operate in a transactional execution mode when the data processing instructions seek access to a stored data item which is shared with a further processor. When the processor enters its transactional execution mode it stores a copy of the current stack depth indication and thereafter, when operating in its transactional execution mode, further modifications to the call stack are compared to the copy of the stack depth indication stored. If the relative stacking position of the required modification is in a positive stack growth direction with respect to the copy stored, the modification to the call stack is labelled as non-speculative.
    Type: Grant
    Filed: June 9, 2015
    Date of Patent: June 19, 2018
    Assignee: ARM Limited
    Inventors: Matthew James Horsnell, Stephan Diestelhorst
  • Patent number: 9984430
    Abstract: A scoreboard may keep track of thread dependencies. A set of threads with a common characteristic may be grouped so that if that characteristic is changed, the group of threads can be accessed to account for that change. Examples for such a characteristic include various types of scoreboard address changes. When the characteristic is changed the group of threads are used to identify threads affected by the characteristic change.
    Type: Grant
    Filed: April 15, 2013
    Date of Patent: May 29, 2018
    Assignee: Intel Corporation
    Inventors: Prasoonkumar Surti, Thomas A. Piazza
  • Patent number: 9977683
    Abstract: In one embodiment, a first thread of execution on a computing device receives a user-interface input. The first thread of execution is associated with a user interface of the computing device. The first thread of execution identifies a second thread of execution on the computing device to process the user-interface input. The second thread of execution is associated with the user interface and is de-coupled from the first thread of execution. The first thread of execution sends the user-interface input to the second thread of execution. The second thread of execution also processes the user-interface input to generate a user-interface output associated with the user-interface input.
    Type: Grant
    Filed: December 14, 2012
    Date of Patent: May 22, 2018
    Assignee: Facebook, Inc.
    Inventor: Robert Douglas Arnold
  • Patent number: 9971604
    Abstract: An approach is provided in which a mapper control unit receives dispatch information corresponding to a dispatching instruction that targets some of the register fields in a register. The mapper control unit selects, in a history buffer, an available history buffer entry that includes multiple field sets, each including an itag field. In turn, the mapper control unit modifies some of the history buffer field sets, including the itag fields, based on the existing content stored in the targeted register fields.
    Type: Grant
    Filed: February 26, 2015
    Date of Patent: May 15, 2018
    Assignee: International Business Machines Corporation
    Inventors: Sundeep Chadha, Michael J. Genden, Dung Q. Nguyen, David R. Terry, Kenneth L. Ward