Dynamic Instruction Dependency Checking, Monitoring Or Conflict Resolution Patents (Class 712/216)
  • Patent number: 11934834
    Abstract: Instruction scheduling in a processor using operation source parent tracking. A source parent is a producer instruction whose execution generates a produced value consumed by a consumer instruction. The processor is configured to track identifying operation source parent information for instructions processed in a pipeline and providing such operation source parent information to a scheduling circuit along with the associated consumer instruction. The scheduling circuit is configured to perform instruction scheduling using operation source parent tracking on received instruction(s) to be scheduled for execution. The processor is configured to compare sources and destinations for each of the instructions to be scheduled based on the operation source parent information to determine instructions ready for scheduling for execution.
    Type: Grant
    Filed: October 19, 2021
    Date of Patent: March 19, 2024
    Assignee: Ampere Computing LLC
    Inventors: Sean Philip Mirkes, Jason Anthony Bessette
  • Patent number: 11926270
    Abstract: A display control device includes a cancellation detection unit that is configured to detect a cancellation regarding a program rewrite from first update data stored in the rewrite target ECU to second update data acquired from an external device, a write instruction unit that is configured to distribute the second update data to the rewrite target ECU and instruct the rewrite target ECU to write the second update data thereinto, and a notification instruction unit that is configured to give an instruction for notification of a progress regarding the program rewrite. The notification instruction unit is further configured to give the instruction to make the notification of the progress regarding the program rewrite in a first manner when the write instruction unit is distributing the second update data, and give the instruction to make the notification of the progress regarding the program rewrite in a second manner when the cancellation detection unit detects the cancellation.
    Type: Grant
    Filed: February 8, 2021
    Date of Patent: March 12, 2024
    Assignee: DENSO CORPORATION
    Inventors: Yuzo Harata, Kazuhiro Uehara, Masaaki Abe, Mitsuyoshi Natsume, Takuya Kawasaki
  • Patent number: 11914724
    Abstract: Disclosed herein are systems and method for adjusting data protection levels based on system metadata. A method may include monitoring a computing device for a cyberattack, wherein a kernel driver of the computing device is configured to allow access to kernel control paths and hash tables in accordance with a first protection level, and detecting that the cyberattack is in progress. While the cyberattack is in progress, the method may include identifying kernel control paths and hashes of software objects that will be affected by the cyberattack, and configuring the kernel driver to disable access to the identified kernel control paths and hashes of the software objects in accordance with a second protection level, wherein the second protection level includes greater access restrictions to the computing device than the first protection level.
    Type: Grant
    Filed: December 19, 2021
    Date of Patent: February 27, 2024
    Assignee: Acronis International GmbH
    Inventors: Nikolay Grebennikov, Candid Wüest, Serguei Beloussov, Stanislav Protasov
  • Patent number: 11907718
    Abstract: Various examples are directed to systems and methods for executing a loop in a reconfigurable compute fabric. A first flow controller may initiate a first thread at a first synchronous flow to execute a first portion of a first iteration of the loop. A second flow controller may receive a first asynchronous message instructing the second flow controller to initiate a first thread at a second synchronous flow to execute a second portion of the first iteration. The second flow controller may determine that the first iteration of the loop is the last iteration of the loop to be executed and initiate the first thread at the second synchronous flow with a last iteration flag set.
    Type: Grant
    Filed: August 18, 2021
    Date of Patent: February 20, 2024
    Assignee: Micron Technology, Inc.
    Inventors: Douglas Vanesko, Bryan Hornung, Patrick Estep
  • Patent number: 11875095
    Abstract: A method for performing automated detection of transaction latency for a processor design model running an application in a hardware simulation accelerator. The method includes loading the processor design model into the hardware simulation accelerator, loading the application into the processor design model running within the hardware simulation accelerator, simulating the processor design model running the application within the hardware simulation accelerator, and for each individual transaction of the application: establishing a first checkpoint at a start of an execution of the individual transaction by creating a breakpoint and resetting a counter, establishing a second checkpoint at a completion of the transaction by creating another breakpoint and obtaining latency information for the second checkpoint. The latencies of the individual transaction from the start to the completion are measured based on the latency information.
    Type: Grant
    Filed: July 1, 2020
    Date of Patent: January 16, 2024
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: John A. Schumann, Tharunachalam Pindicura, Shricharan Srivatsan, Vivek Britto, Madhumitha Venkataraman
  • Patent number: 11875495
    Abstract: A method, apparatus and storage medium for performing a video quality assessment (VQA) are provided. The method includes obtaining a plurality of images of a video, the plurality of images being divided into one or more groups; determining first images among the plurality of images to which a parametric-based VQA is to be applied, the first images being all of the plurality of images; determining a first score based on applying the parametric-based VQA to each of the first images; determining second images among the plurality of images to which a sample-based VQA is to be applied; determining a second score based on applying the sample-based VQA to each of the second images; and outputting a final score for at least one image based on the first score and the second score.
    Type: Grant
    Filed: June 29, 2021
    Date of Patent: January 16, 2024
    Assignee: TENCENT AMERICA LLC
    Inventors: Xiaozhong Xu, Xiang Li, Shan Liu
  • Patent number: 11868802
    Abstract: Application lifecycle management based on real-time resource usage. A first plurality of resource values that quantify real-time computing resources used by a first instance of an application is determined at a first point in time. Based on the first plurality of resource values, one or more utilization values are stored in a profile that corresponds to the application. Subsequent to storing the one or more utilization values in the profile, it is determined that a second instance of the application is to be initiated. The profile is accessed, and the second instance of the application is caused to be initiated on a first computing device utilizing the one or more utilization values identified in the profile.
    Type: Grant
    Filed: July 9, 2021
    Date of Patent: January 9, 2024
    Assignee: Red Hat, Inc.
    Inventors: Leigh Griffin, Pierre-Yves Chibon
  • Patent number: 11868805
    Abstract: Techniques of scheduling workload(s) on partitioned resources of host systems are described. The techniques can be used, for example, in a container-orchestration system. One technique includes retrieving information characterizing at least one schedulable partition and determining an availability and a suitability of one or more of the schedulable partition(s) for executing a workload in view of the information. Each of the schedulable partition(s) includes resources of one or more host systems. The technique also includes selecting one or more of the schedulable partition(s) to execute the workload in view of the availability and the suitability.
    Type: Grant
    Filed: April 13, 2021
    Date of Patent: January 9, 2024
    Assignee: Red Hat, Inc.
    Inventors: Marcel Apfelbaum, Swati Sehgal
  • Patent number: 11853755
    Abstract: Apparatuses, methods of data processing, complementary instructions and programs related to atomic range-compare-and-modify operations are disclosed. Data processing operations are performed in response to received instructions, wherein the data processing operations comprise an atomic range-compare-and-modify operation, which receives indications of a data value storage location, a range start, and a range size and, as an atomic set of steps, reads a base value stored at the data value storage location, determines an in-range condition to be true when the base value is within a request range having a lower bound being the range start and an upper bound being the range start plus the range size, and when the in-range condition is true, modify the base value to an updated base value. Reduced contention between processes accessing the same data value storage location and range of locations is thus supported.
    Type: Grant
    Filed: July 30, 2020
    Date of Patent: December 26, 2023
    Assignee: Arm Limited
    Inventor: Eric Ola Harald Liljedahl
  • Patent number: 11847462
    Abstract: A software-based instruction scoreboard indicates dependencies between closely-issued instructions issued to an arithmetic logic unit (ALU) pipeline. The software-based instruction scoreboard inserts one or more control words into the command stream between the dependent instructions, which is then executed by the ALU pipeline. The control words identify the instruction(s) upon which the dependent instructions depend (parent instructions) so that the GPU hardware can ensure that the ALU pipeline does not stall while the dependent instruction waits for results from the parent instruction.
    Type: Grant
    Filed: December 15, 2020
    Date of Patent: December 19, 2023
    Assignee: Advanced Micro Devices, Inc.
    Inventor: Brian Emberling
  • Patent number: 11847044
    Abstract: A method may include detecting a first sub-flow, by executing a local defect analysis on code starting at a sink instruction, to a load instruction performing reading a first value using a first variable. The first sub-flow may include a first label of a first defect. The method may further include detecting a second sub-flow, by executing the local defect analysis on the code starting at a store instruction, to a load instruction performing writing a second value using a second variable. The second sub-flow may include a second label of a second defect. The method may further include determining that the first variable and the second variable are potential aliases by determining that the first label matches the second label, and obtaining, based on determining that the first variable and the second variable are potential aliases, a nonlocal flow by connecting the first sub-flow and the second sub-flow.
    Type: Grant
    Filed: September 8, 2021
    Date of Patent: December 19, 2023
    Assignee: Oracle International Corporation
    Inventors: Padmanabhan Krishnan, Yang Zhao
  • Patent number: 11842230
    Abstract: A processing device is described that includes a processing cluster having a message management facility and a message processing facility. The message management facility has a first message queue, a second message queue and a queue controller. The message processing facility has a plurality of processing device elements with at least two input ports, and the message processing facility is configured to: receive the selected instruction messages from the message management facility, accept or reject the selected instruction messages, return rejected selected instruction messages as a bounced instruction message to the message management facility, retrieve operand data from an accepted selected instruction message for an input port of a processing device element identified by the selected instruction message, and perform an operation designated to a processing device element once each of its input ports have received operand data.
    Type: Grant
    Filed: July 15, 2020
    Date of Patent: December 12, 2023
    Assignee: GRAI MATTER LABS S.A.S.
    Inventors: Orlando Miguel Pires Dos Reis Moreira, Gokturk Cinserin
  • Patent number: 11803476
    Abstract: An apparatus to facilitate data prefetching is disclosed. The apparatus includes a cache, one or more execution units (EUs) to execute program code, prefetch logic to maintain tracking information of memory instructions in the program code that trigger a cache miss and compiler logic to receive the tracking information, insert one or more pre-fetch instructions in updated program code to prefetch data from a memory for execution of one or more of the memory instructions that triggered a cache miss and download the updated program code for execution by the one or more EUs.
    Type: Grant
    Filed: March 24, 2021
    Date of Patent: October 31, 2023
    Assignee: INTEL CORPORATION
    Inventors: Vasileios Porpodas, Guei-Yuan Lueh, Subramaniam Maiyuran, Wei-Yu Chen
  • Patent number: 11799857
    Abstract: Disclosed are methods, systems, and non-transitory computer-readable storage media for evaluating software posture as a condition of zero trust access. The present technology provides a client-side validation agent and a validation service which in tandem can capture and evaluate data representative of parameters associated with an application executing on a user device. The validation service can validate the application to a networked service, and in turn the networked service can permit communication to the application running on the user device.
    Type: Grant
    Filed: August 31, 2021
    Date of Patent: October 24, 2023
    Assignee: Cisco Technology, Inc.
    Inventors: Frank Michaud, Peshan Sampath Kalu Marakkala
  • Patent number: 11797306
    Abstract: In accordance with an embodiment, a method verifies contents of a plurality of registers having two first registers, where each of the plurality of registers is configured to store a data word and a verification bit. The method includes determining whether a value of the verification bit of each respective register of the plurality of registers corresponds to the data word of its respective register. The data words stored in the two first registers are selected so that the bits of a same rank of the two first registers include two complementary bits, each bit of a common binary word is associated with a respective register of the plurality of registers, and the value of the verification bit of each respective register depends on the data word of the respective register and the bit of the common binary word associated with the respective register.
    Type: Grant
    Filed: April 26, 2022
    Date of Patent: October 24, 2023
    Assignee: STMicroelectronics (Grenoble 2) SAS
    Inventors: Gregory Trunde, Denis Dutey
  • Patent number: 11782772
    Abstract: A computer-implemented method for execution of a service in a distributed environment, the method comprising performing a speculative execution of a service and storing a related result, wherein a decision whether the speculative execution of the service is performed is dependent on a dynamically changing score value and receiving a request for an execution of the service at a request proxy. Additionally, the method comprises upon determining that a valid result of the execution of the service is available from an earlier speculative execution of a comparable service, returning the valid result by the request proxy, and upon determining that a valid result of the execution of the service is not available from an earlier speculative execution of a comparable service, executing the service in a non-speculative manner, and returning a received non-speculative result by the request proxy.
    Type: Grant
    Filed: June 24, 2022
    Date of Patent: October 10, 2023
    Assignee: International Business Machines Corporation
    Inventors: Sugandha Agrawal, Timo Kussmaul, Harald Daur, Torsten Teich
  • Patent number: 11755732
    Abstract: A processor is disclosed that mitigates side channel attacks that exploit speculative store-to-load forwarding. The processor includes logic that conditions store-to-load forwarding of uncommitted store data in the store queue from an uncommitted store instruction to the load instruction upon circumstances associated with a translation context (TC) change or update. The TC comprises an address space identifier (ASID), a virtual machine identifier (VMID), a privilege mode (PM) or a combination of two or more of the ASID, VMID and PM or a derivative thereof. The logic is embedded or associated with any of several structures, such as a store queue (SQ), a memory dependence predictor (MDP), or a reorder buffer (ROB).
    Type: Grant
    Filed: February 25, 2021
    Date of Patent: September 12, 2023
    Assignee: Ventana Micro Systems Inc.
    Inventor: John G. Favor
  • Patent number: 11755731
    Abstract: A processor for mitigating side channel attacks includes units that perform fetch, decode, and execution of instructions and pipeline control logic. The processor performs speculative and out-of-order execution of the instructions. The units detect and notify the control unit of events that cause a change from a first translation context (TC) to a second TC. In response, the pipeline control logic prevents speculative execution of instructions that are dependent in their execution on the change to the second TC until all instructions that are dependent on the first TC have completed execution, which may involve stalling their dispatch until all first-TC-dependent instructions have at least completed execution, or by tagging them and dispatching them to execution schedulers but preventing them from starting execution until all first-TC-dependent instructions have at least completed execution.
    Type: Grant
    Filed: July 23, 2020
    Date of Patent: September 12, 2023
    Assignee: Ventana Micro Systems Inc.
    Inventors: John G. Favor, David S. Oliver
  • Patent number: 11755329
    Abstract: An arithmetic processing apparatus includes an instruction execution control circuit that outputs an instruction from an entry of entries, including an executable instruction information storage circuit storing executable instruction information indicating whether an instruction in each of the entries is executable, a priority information storage circuit including, for each entry, storage areas storing priority information indicating whether an instruction in an entry has higher priority on an entry-by-entry basis, an executable instruction information write circuit writing the executable instruction information in response to determining whether an instruction in each of the entries is executable, a priority information write circuit writing the priority information in response to determining whether an instruction in each of the entries has higher priority, and an output determination circuit selecting an entry from which an instruction is output on a basis of the executable instruction information and the
    Type: Grant
    Filed: December 3, 2019
    Date of Patent: September 12, 2023
    Assignee: FUJITSU LIMITED
    Inventors: Gen Oshiyama, Sota Sakashita
  • Patent number: 11740908
    Abstract: In a particular implementation, a method includes: receiving, at a computing device, first and second instructions of a plurality of instructions obtained from a memory, where the first instruction corresponds to a preceding instruction of a second instruction, and where the second instruction corresponds to a succeeding instruction of the first instruction; determining a dependency of the first and second instructions; sending the first and second instructions to an issue queue of the computing device; executing, at the computing device, the first and second instructions; and completing, at the computing device, the first and second instructions.
    Type: Grant
    Filed: December 21, 2020
    Date of Patent: August 29, 2023
    Assignee: Arm Limited
    Inventors: Wei Wang, Thomas Edward Shull
  • Patent number: 11740907
    Abstract: In a particular implementation, a method includes: receiving, at a central processing unit (CPU), first and second instructions of a plurality of instructions obtained from a memory, where the first instruction corresponds to a preceding instruction of a second instruction, and where the second instruction corresponds to a succeeding instruction of the first instruction; determining a dependency of the first and second instructions; sending the first and second instructions to an issue queue of the CPU; executing, at the CPU, the first and second instructions; and completing, at the CPU, the first and second instructions.
    Type: Grant
    Filed: March 16, 2020
    Date of Patent: August 29, 2023
    Assignee: Arm Limited
    Inventor: Thomas Edward Shull
  • Patent number: 11734010
    Abstract: An execution unit circuit for use in a processor core provides efficient use of area and energy by reducing the per-entry storage requirement of a load-store unit issue queue. The execution unit circuit includes a recirculation queue that stores the effective address of the load and store operations and the values to be stored by the store operations. A queue control logic controls the recirculation queue and issue queue so that that after the effective address of a load or store operation has been computed, the effective address of the load operation or the store operation is written to the recirculation queue and the operation is removed from the issue queue, so that address operands and other values that were in the issue queue entry no longer require storage. When a load or store operation is rejected by the cache unit, it is subsequently reissued from the recirculation queue.
    Type: Grant
    Filed: September 7, 2021
    Date of Patent: August 22, 2023
    Assignee: International Business Machines Corporation
    Inventors: Salma Ayub, Sundeep Chadha, Robert Allen Cordes, David Allen Hrusecky, Hung Qui Le, Dung Quoc Nguyen, Brian William Thompto
  • Patent number: 11709678
    Abstract: In one embodiment, a processor includes fetch logic to fetch instructions, decode logic to decode the fetched instructions, and execution logic to execute at least some of the instructions. The decode logic may determine whether a flag portion of a first instruction to be folded is to be performed, and if not, accumulate a first immediate value of the first instruction with a folded immediate value obtained from an entry of an immediate buffer.
    Type: Grant
    Filed: June 1, 2021
    Date of Patent: July 25, 2023
    Assignee: Intel Corporation
    Inventors: Zeev Sperber, Tomer Weiner, Amit Gradstein, Simon Rubanovich, Alex Gerber, Itai Ravid
  • Patent number: 11687337
    Abstract: A method for operation of a processor core is provided. A rejected first load instruction is received that has been rejected due to a false load-hit-store detection against a first store instruction. A warning label is generated on a basis of the false load-hit-store detection. The warning label is added to the received first load instruction to create a labeled first load instruction. The labeled first load instruction is issued such that the warning label causes the labeled first load instruction to bypass the first store instruction in the store reorder queue and thereby avoid another false load-hit-store detection against the first store instruction. A computer system and a processor core configured to operate according to the method are also disclosed herein.
    Type: Grant
    Filed: August 20, 2021
    Date of Patent: June 27, 2023
    Assignee: International Business Machines Corporation
    Inventors: Bryan Lloyd, Brian Chen, Kimberly M. Fernsler
  • Patent number: 11689424
    Abstract: Some embodiments of the invention provide a network forwarding element that can be dynamically reconfigured to adjust its data message processing to stay within a desired operating temperature or power consumption range. In some embodiments, the network forwarding element includes (1) a data-plane forwarding circuit (“data plane”) to process data tuples associated with data messages received by the IC, and (2) a control-plane circuit (“control plane”) for configuring the data plane forwarding circuit. The data plane includes several data processing stages to process the data tuples. The data plane also includes an idle-signal injecting circuit that receives from the control plane configuration data that the control plane generates based on the IC's temperature. Based on the received configuration data, the idle-signal injecting circuit generates idle control signals for the data processing stages.
    Type: Grant
    Filed: August 6, 2021
    Date of Patent: June 27, 2023
    Assignee: Intel Corporation
    Inventor: Remy Chang
  • Patent number: 11669626
    Abstract: In one aspect, the present disclosure relates to a method including: determining whether first data representative of a first string of content used by a user to access an application is present within the data structure having positions that contain values representative of strings of content; responsive to determination that the first data is not present within the data structure, retrieving a value from an index using a key associated with the user, the value being derived from positions in the data structure that contain values representative of a second string of content previously used by the user to access the application; decrementing the values of the positions in the data structure representative of the second string of content to remove second data representative of the second string of content from the data structure; and adding the first data representative of the first string of content to the data structure.
    Type: Grant
    Filed: March 18, 2021
    Date of Patent: June 6, 2023
    Inventor: Manbinder Pal Singh
  • Patent number: 11656876
    Abstract: Techniques are disclosed relating to an apparatus, including a data storage circuit having a plurality of entries, and a load-store pipeline configured to allocate an entry in the data storage circuit in response to a determination that a first instruction includes an access to an external memory circuit. The apparatus further includes an execution pipeline configured to make a determination, while performing a second instruction and using the entry in the data storage circuit, that the second instruction uses a result of the first instruction, and cease performance of the second instruction in response to the determination.
    Type: Grant
    Filed: February 10, 2021
    Date of Patent: May 23, 2023
    Assignee: Cadence Design Systems, Inc.
    Inventors: Robert T. Golla, Deepak Panwar
  • Patent number: 11650814
    Abstract: Generating customized documentation is disclosed, including: receiving a set of meta information describing an aspect of an application; and generating a document to provide guidance specific to the application based at least in part on at least a subset of the set of meta information.
    Type: Grant
    Filed: December 21, 2012
    Date of Patent: May 16, 2023
    Assignee: EMC IP Holding Company LLC
    Inventors: Vikas Wadhwa, Jeroen Van Rotterdam, Raman Walia
  • Patent number: 11609761
    Abstract: A method, computer readable medium, and processor are described herein for inline data inspection by using a decoder to decode a load instruction, including a signal to cause a circuit in a processor to indicate whether data loaded by a load instruction exceeds a threshold value. Moreover, an indication of whether data loaded by a load instruction exceeds a threshold value may be stored.
    Type: Grant
    Filed: December 9, 2019
    Date of Patent: March 21, 2023
    Assignee: NVIDIA CORPORATION
    Inventors: Jeffrey Michael Pool, Andrew Kerr, John Tran, Ming Y. Siu, Stuart Oberman
  • Patent number: 11604653
    Abstract: Provided are embodiments for a computer-implemented method, system and computer program product for identifying dependencies in a control sequence. Embodiments include receiving a control block that comprises a first error dependency (EDEP) level, maintaining the first EDEP level, and determining whether the received control block was successfully executed. Embodiments also include receiving a subsequent control block that comprises a second EDEP level, comparing the first EDEP level and the second EDEP level, and providing the subsequent control block for execution based at least in part on the successful execution of the received control block, and on the second EDEP level being less than or equal to the first EDEP level.
    Type: Grant
    Filed: December 11, 2020
    Date of Patent: March 14, 2023
    Assignee: International Business Machines Corporation
    Inventors: Scot Rider, Marcel Schaal
  • Patent number: 11593184
    Abstract: Methods, systems and apparatuses for graph processing are disclosed. One graph streaming processor includes a thread manager, wherein the thread manager is operative to dispatch operation of the plurality of threads of a plurality of thread processors before dependencies of the dependent threads have been resolved, maintain a scorecard of operation of the plurality of threads of the plurality of thread processors, and provide an indication to at least one of the plurality of thread processors when a dependency between the at least one of the plurality of threads that a request has or has not been satisfied. Further, a producer thread provides a response to the dependency when the dependency has been satisfied, and each of the plurality of thread processors is operative to provide processing updates to the thread manager, and provide queries to the thread manager upon reaching a dependency.
    Type: Grant
    Filed: August 11, 2021
    Date of Patent: February 28, 2023
    Assignee: Blaize, Inc.
    Inventors: Lokesh Agarwal, Sarvendra Govindammagari, Venkata Ganapathi Puppala, Satyaki Koneru
  • Patent number: 11586465
    Abstract: A device includes a hardware data processing node configured to execute a respective task, and a hardware thread scheduler including a hardware task scheduler. The hardware task scheduler is coupled to the hardware data processing node and has a producer socket, a consumer socket, and a spare socket. The spare socket is configured to provide data control signals also provided by a first socket of the producer and consumer sockets responsive to a memory-mapped register being a first value. The spare socket is configured to provide data control signals also provided by a second socket of the producer and consumer sockets responsive to the memory-mapped register being a second value.
    Type: Grant
    Filed: December 30, 2020
    Date of Patent: February 21, 2023
    Assignee: Texas Instruments Incorporated
    Inventors: Niraj Nandan, Mihir Mody
  • Patent number: 11561792
    Abstract: A transient load instruction for a processor may include a transient or temporary load instruction that is executed in parallel with a plurality of input operands. The temporary load instruction loads a memory value into a temporary location for use within the instruction packet. According to some examples, a VLIW based microprocessor architecture may include a temporary cache for use in writing/reading a temporary memory value during a single VLIW packet cycle. The temporary cache is different from the normal register bank that does not allow writing and then reading the value just written during the same VLIW packet cycle.
    Type: Grant
    Filed: June 8, 2015
    Date of Patent: January 24, 2023
    Assignee: Qualcomm Incorporated
    Inventors: Eric Mahurin, Jakub Pawel Golab
  • Patent number: 11544072
    Abstract: Various embodiments are disclosed of a multiprocessor system with processing elements optimized for high performance and low power dissipation and an associated method of programming the processing elements. Each processing element may comprise a fetch unit and a plurality of address generator units and a plurality of pipelined datapaths. The fetch unit may be configured to receive a multi-part instruction, wherein the multi-part instruction includes a plurality of fields. First and second address generator units may generate, based on different fields of the multi-part instruction, addresses from which to retrieve first and second data for use by an execution unit for the multi-part instruction or a subsequent multi-part instruction. The execution units may perform operations using a single pipeline or multiple pipelines based on third and fourth fields of the multi-part instruction.
    Type: Grant
    Filed: March 16, 2021
    Date of Patent: January 3, 2023
    Assignee: Coherent Logix, Inc.
    Inventors: Michael B. Doerr, Carl S. Dobbs, Michael B. Solka, Michael R. Trocino, Kenneth R. Faulkner, Keith M. Bindloss, Sumeer Arya, John Mark Beardslee, David A. Gibson
  • Patent number: 11531545
    Abstract: A method of activating scheduling instructions within a parallel processing unit is described. The method comprises decoding, in an instruction decoder, an instruction in a scheduled task in an active state and checking, by an instruction controller, if a swap flag is set in the decoded instruction. If the swap flag in the decoded instruction is set, a scheduler is triggered to de-activate the scheduled task by changing the scheduled task from the active state to a non-active state.
    Type: Grant
    Filed: December 1, 2020
    Date of Patent: December 20, 2022
    Assignee: Imagination Technologies Limited
    Inventors: Simon Nield, Yoong-Chert Foo, Adam de Grasse, Luca Iuliano
  • Patent number: 11526337
    Abstract: Described herein is a computer implemented method. The method comprises executing an application defining a feature flag, the execution of the application being associated with a user identifier. The method further comprises determining if version data associated with the feature flag and user identifier is stored in a local data store. In response determining that the version data associated with the feature flag and user identifier is stored in the local data store an evaluation request is generated that includes the version data and the user identifier. The evaluation request is then communicated to a feature flag evaluation service.
    Type: Grant
    Filed: February 26, 2021
    Date of Patent: December 13, 2022
    Assignees: ATLASSIAN PTY LTD., ATLASSIAN US, INC.
    Inventors: Francisco Javier Cano Munoz, Jimmy Li, Houda Chehab, Rob Sangster
  • Patent number: 11513959
    Abstract: A request to read data from a location associated with a memory component is received. The request is assigned a first tag, the first tag having a first identifier of a first buffer to store data read from the location. The request to read data is determined to collide with an earlier request to write data to the location. The earlier request is assigned a second tag, the second tag having a second identifier of a second buffer to store data to write to the location. An attempt to lock the second tag and the second buffer for the request to read data is made. The request to read data is fulfilled from the second buffer in response to a successful attempt to lock the second tag and the second buffer.
    Type: Grant
    Filed: February 25, 2021
    Date of Patent: November 29, 2022
    Assignee: MICRON TECHNOLOGY, INC.
    Inventors: Horia C. Simionescu, Lyle E. Adams, Yongcai Xu, Mark Ish
  • Patent number: 11507322
    Abstract: There are provided a memory controller and a storage device including the same. The memory controller includes: a command storage including a first read command queue and a second read command queue; a command generation controller configured to provide an erase command, a suspend command, a resume command, and output a scheduling event signal after the resume command is output; and a command schedule controller configured to: search for a first physical address group, reorder a output sequence of the first read command queue, and provide a command to perform the read command based on the second read command queue.
    Type: Grant
    Filed: July 1, 2021
    Date of Patent: November 22, 2022
    Assignee: SK hynix Inc.
    Inventor: Chung Un Na
  • Patent number: 11494624
    Abstract: Systems and methods for accelerating computation of an artificial neural network (ANN) are provided. An example method comprises receiving, by processing units coupled with arithmetic units and accumulation units, a first plurality of first values and a second plurality of second values associated with one or more neurons of the ANN, generating, by the processing units, a plurality of pairs, wherein each pair of the plurality of pairs has a first value of the first plurality and a second value of the second plurality and the first value and the second value satisfy criteria, performing, by the arithmetic units, mathematical operations on pairs of the plurality of pairs to obtain results; accumulating, by the accumulation units, the results to obtain accumulated results, and determining, by the processing units and based on the accumulated results, an output of the neurons.
    Type: Grant
    Filed: May 20, 2019
    Date of Patent: November 8, 2022
    Assignee: MIPSOLOGY SAS
    Inventors: Ludovic Larzul, Sebastien Delerse
  • Patent number: 11487593
    Abstract: A barrier synchronization system, a parallel information processing apparatus, and the like are described in the embodiments. In an example, provided is a solution to reduce latency time and improve processing speed in barrier synchronization.
    Type: Grant
    Filed: September 8, 2020
    Date of Patent: November 1, 2022
    Assignee: FUJITSU LIMITED
    Inventors: Kanae Nakagawa, Masaki Arai, Yasumoto Tomita
  • Patent number: 11487542
    Abstract: Instruction cache behavior and branch prediction are used to improve the functionality of a computing device by profiling branching instructions in an instruction cache to identify likelihoods of proceeding to a plurality of targets from the branching instructions; identifying a hot path in the instruction cache based on the identified likelihoods; and rearranging the plurality of targets relative to one another and associated branching instructions so that a first branching instruction that has a higher likelihood of proceeding to a first hot target than to a first cold target and that previously flowed to the first cold target and jumped to the first hot target instead flows to the first hot target and jumps to the first cold target.
    Type: Grant
    Filed: July 20, 2020
    Date of Patent: November 1, 2022
    Assignee: International Business Machines Corporation
    Inventors: Yang Liu, Ting Wang, Qi Li, Qing Zhang, Gui Haochen, Xiao Ping Guo, Xiao Hua Zeng, Yangming Wang, Yi Li, Hua Qing Li, Fei Fei
  • Patent number: 11474821
    Abstract: In an approach to processor dependency-aware instruction execution, responsive to a new instruction being issued to an instruction issue queue in a processor, a future dependency count is incremented for each instruction of a plurality of instructions in the instruction issue queue that has a dependency on the new instruction. The plurality of instructions in the instruction issue queue are prioritized based on the future dependency count. The highest priority instruction of the plurality of instructions in the instruction issue queue is issued.
    Type: Grant
    Filed: May 12, 2021
    Date of Patent: October 18, 2022
    Assignee: International Business Machines Corporation
    Inventors: Amir Turi, Avraham Ayzenfeld, Gilad Shimon Merran, Yanai Danan, Amit Shay, Yossi Shapira, Yair Fried, Oren Ben Gigi, Omri Rafaeli
  • Patent number: 11467841
    Abstract: A microprocessor that includes a shared functional unit, a first execution queue and a second execution queue is introduced. The first execution queue includes a plurality of entries, wherein each entry of the first execution queue includes a first count value which is decremented until the first count value reaches 0. The first execution queue dispatches the first-type instruction to the shared functional unit when the first count value reaches 0. The second execution queue include a plurality of entries, wherein each entry of the second execution queue comprises a second count value which is decremented until the second count value reaches 0. The second execution queue dispatches the second-type instruction to the shared functional unit when the second count value reaches 0.
    Type: Grant
    Filed: June 1, 2021
    Date of Patent: October 11, 2022
    Assignee: ANDES TECHNOLOGY CORPORATION
    Inventor: Thang Minh Tran
  • Patent number: 11467844
    Abstract: Embodiments of the present disclosure provide an instruction processing apparatus, comprising an instruction decoding circuitry configured to decode a set of instructions; a buffer comprising one or more buffer entries associated with the set of instructions, wherein the one or more buffer entries are configured to store information corresponding to at least one instruction of the set of instructions decoded by the instruction decoding circuitry; and an instruction executing circuitry configured to execute the at least one instruction, wherein a buffer entry storing the information corresponding to the at least one instruction is updated to indicate that the at least one instruction has been executed to enable retiring the set of instructions after the set of instructions have been executed.
    Type: Grant
    Filed: September 17, 2020
    Date of Patent: October 11, 2022
    Assignee: Alibaba Group Holding Limited
    Inventors: Chang Liu, Ruqin Zhang
  • Patent number: 11461143
    Abstract: A computing system is provided, including a processor configured to generate a directed weighted graph indicating a plurality of functions configured to be executed on a plurality of communicatively connected processing devices. For each of a plurality of pairs of the functions, the processor may determine a shortest path between the pair of functions. The processor may generate a second graph indicating the plurality of pairs of functions connected by the shortest paths. The processor may receive a pipeline directed acyclic graph (DAG) specifying a data pipeline of a plurality of processing stages. The processor may determine a subgraph isomorphism between the pipeline DAG and the second graph. The processor may convey, to one or more processing devices of the plurality of processing devices, instructions to execute the plurality of processing stages as specified by the subgraph isomorphism.
    Type: Grant
    Filed: September 8, 2020
    Date of Patent: October 4, 2022
    Assignee: MEGH COMPUTING, INC.
    Inventor: Jonathan Beare
  • Patent number: 11451241
    Abstract: A processor employs a set of bits to indicate values of portions of registers of a register file. In response to a specified instruction indicating an expected change of instruction types to be executed, the processor sets one or more of the bits and, for subsequent instructions, interprets corresponding portions of the registers as having a specified value (e.g., zero). By employing the set of bits to set the values of the register portions, rather than setting the individual portions of the registers to the specified value, the processor conserves processor resources (e.g., power) when the processor transitions between executing instructions of different types.
    Type: Grant
    Filed: December 14, 2017
    Date of Patent: September 20, 2022
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Erik Swanson, Sneha V. Desai, Michael Estlick
  • Patent number: 11442731
    Abstract: A data processor includes an execution unit that executes instructions to perform data processing operations, a register file operable to store data values for use by and produced by the execution unit, and a buffer intermediate between the register file for providing data values from the register file to the execution unit for use when executing an instruction, and to receive output data values from the execution unit for writing to the register file. Instructions to be executed by the execution unit of the data processor have associated buffer eviction priority indications representative of a priority for eviction from the buffer of an output data value that will be generated when executing the instruction. The buffer eviction priority indications are then used when selecting data values to evict from the buffer.
    Type: Grant
    Filed: October 17, 2019
    Date of Patent: September 13, 2022
    Assignee: Arm Limited
    Inventors: John David Robson, Sean Tristram LeGuay Ellis, William Robert Stoye
  • Patent number: 11416406
    Abstract: A microprocessor includes a store queue (SQ) and a physically-indexed physically-tagged second-level set-associative cache. Each cache entry is uniquely identified by a set index and a way number. Each SQ entry holds information for a store instruction. The information includes store data to be written to a store physical address, a portion of which is a store physical line address. The information also includes a store physical address proxy (PAP) for the store physical line address. The store PAP specifies the set index and the way number of the cache entry into which a cache line specified by the store physical line address is allocated. A load unit, during execution of a load instruction, uses the store PAP held in a SQ entry in making a decision whether to forward to the load instruction the store data held in the SQ entry.
    Type: Grant
    Filed: June 18, 2021
    Date of Patent: August 16, 2022
    Assignee: Ventana Micro Systems Inc.
    Inventors: John G. Favor, Srivatsan Srinivasan
  • Patent number: 11402822
    Abstract: To provide a numerical controller that can detect a position in a machining program at which a speed control abnormality is likely to occur due to an insufficient look-ahead blocks that are used to determine an acceleration/deceleration operation, and start a look-ahead processing function from the position in parallel with looking ahead at the machining program from the start of the machining program.
    Type: Grant
    Filed: October 25, 2019
    Date of Patent: August 2, 2022
    Assignee: FANUC CORPORATION
    Inventors: Daisuke Uenishi, Chikara Tango
  • Patent number: 11392380
    Abstract: Systems, methods, and apparatuses relating to circuitry to precisely monitor memory store accesses are described.
    Type: Grant
    Filed: December 28, 2019
    Date of Patent: July 19, 2022
    Assignee: Intel Corporation
    Inventors: Ahmad Yasin, Raanan Sade, Liron Zur, Igor Yanover, Joseph Nuzman