Abstract: An apparatus and method are provided for speculatively vectorising program code. The apparatus includes processing circuitry for executing program code, the program code including an identified code region comprising at least a plurality of speculative vector memory access instructions. Execution of each speculative vector memory access instruction is employed to perform speculative vectorisation of a series of scalar memory access operations using a plurality of lanes of processing. Tracking storage is used to maintain, for each speculative vector memory access instruction, tracking information providing an indication of a memory address being accessed within each lane. Checking circuitry then references the tracking information during execution of the identified code region by the processing circuitry, in order to detect any inter lane memory hazard resulting from the execution of the plurality of speculative vector memory access instructions.

Abstract: System and techniques for synchronized request handling at a memory device are described herein. A request is received at the memory device. Here, the request indicates a memory address corresponding to a set of cache lines and a single cache line in the set of cache lines. The memory device maintains a deferred list for the set of cache lines and a set of lists with each member of the set of lists corresponding to one cache line in the set of cache lines. The memory device tests the deferred list to determine that the deferred list is not empty and places the request in the deferred list.

Abstract: Devices and techniques for parking threads in a barrel processor for managing hazard clearing are described herein. A barrel processor includes hazard management circuitry that is used to receive an indication of an instruction executing in a compute pipeline of the barrel processor, the instruction having encountered a hazard and unable to progress through the compute pipeline; store the indication of the instruction in a hazard memory; receive a signal indicating that the hazard has cleared; and cause the instruction to be rescheduled at the beginning of the compute pipeline in response to the signal.

Abstract: A method comprises receiving, in a store buffer, at least a portion of a store instruction, the at least a portion of the store instruction comprising a data operand and a first object capability register operand which comprises a first object type identifier for a first object, obtaining, from a corresponding load instruction, a second object capability register operand which comprises a second object type identifier, and determining whether the first object type identifier matches the second object type identifier.

Abstract: The described technology relates to a publish-subscribe message framework in which an application, decomposed to a plurality of processing stages, is run by executing respective processing stages of the application asynchronously and simultaneously with each other. Communications between the respective processing stages may exclusively be in accordance with the publish-subscribe execution model. The described publish-subscribe framework provides for processing stages to be executed in a multi-process and/or multi-threaded manner while also enabling the distribution of the processing stages to respective processing resources in a multi-processor/multi-core processing environment. An example electronic exchange application and a corresponding example exchange gateway application are described.

Abstract: A processor for mitigating side channel attacks includes units that perform fetch, decode, and execution of instructions and pipeline control logic. The processor performs speculative and out-of-order execution of the instructions. The units detect and notify the control unit of events that cause a change from a first translation context (TC) to a second TC. In response, the pipeline control logic prevents speculative execution of instructions that are dependent in their execution on the change to the second TC until all instructions that are dependent on the first TC have completed execution, which may involve stalling their dispatch until all first-TC-dependent instructions have at least completed execution, or by tagging them and dispatching them to execution schedulers but preventing them from starting execution until all first-TC-dependent instructions have at least completed execution.

Abstract: An electronic device comprises: a memory management module; a processor operatively connected to the memory management module; and a memory controlled by the memory management module and operatively connected to the processor. The memory is configured to store instructions which, when executed, cause the processor to: execute at least one process, identify a rate at which the at least one process is terminated, based on a preconfigured first cycle, determine a number of times the identified rate exceeds a first threshold value, and based on a determination that the number of times the identified rate exceeds the first threshold value is greater than a second threshold value, reboot the electronic device.

Abstract: A system and method for providing access to third-party application programming interfaces (APIs) as a service. In particular, an API access manager can be configured to execute one or more serverless functions selected form a database of serverless functions in order to obtain data from one or more third-party APIs. Execution of different versions of the serverless functions (e.g., original and refactored) can be compared to determine whether the versions are equivalent and deterministic.

Abstract: Representative apparatus, method, and system embodiments are disclosed for a self-scheduling processor which also provides additional functionality. Representative embodiments include a self-scheduling processor, comprising: a processor core adapted to execute a received instruction; and a core control circuit adapted to automatically schedule an instruction for execution by the processor core in response to a received work descriptor data packet. In another embodiment, the core control circuit is also adapted to schedule a fiber create instruction for execution by the processor core, to reserve a predetermined amount of memory space in a thread control memory to store return arguments, and to generate one or more work descriptor data packets to another processor or hybrid threading fabric circuit for execution of a corresponding plurality of execution threads. Event processing, data path management, system calls, memory requests, and other new instructions are also disclosed.

Abstract: A processor and an operating method thereof for renaming a destination logical register of a move instruction are provided. The processor comprises a plurality of physical registers and a renaming circuit. The renaming circuit is coupled to the plurality of physical registers and is configured to receive an instruction sequence and check the instruction sequence. When a current instruction of the instruction sequence comprises the move instruction, the renaming circuit assigns a first physical register, which is assigned to a source logical register of the current instruction previously, to the destination logical register of the current instruction. The first physical register is one of the plurality of physical registers.

Abstract: Some embodiments of the invention provide a network forwarding element that can be dynamically reconfigured to adjust its data message processing to stay within a desired operating temperature or power consumption range. In some embodiments, the network forwarding element includes (1) a data-plane forwarding circuit (“data plane”) to process data tuples associated with data messages received by the IC, and (2) a control-plane circuit (“control plane”) for configuring the data plane forwarding circuit. The data plane includes several data processing stages to process the data tuples. The data plane also includes an idle-signal injecting circuit that receives from the control plane configuration data that the control plane generates based on the IC's temperature. Based on the received configuration data, the idle-signal injecting circuit generates idle control signals for the data processing stages.

Abstract: The present disclosure provides systems, methods, and computer-readable media for implementing security polices at software call stack level. In one example, a method includes generating a call stack classification scheme for an application, detecting a call stack during deployment of the application; using the call stack classification scheme during runtime of the application, classifying the detected call stack as one of an authorized call stack or an unauthorized call stack to yield a classification; and applying a security policy based on the classification.

Abstract: A dependency-based startup method in a multi-modality medical processing system that includes receiving initialization information about a plurality of executable components to be started, the plurality of executable components including an executable modality component configured to communicate with a medical device communicatively coupled to the multi-modality medical processing system. The method also includes receiving dependency information about the executable modality component, the dependency information identifying one or more of the executable components upon which the executable modality component depends and transforming the initialization information and the dependency information into a dependency map that represents the dependencies between the plurality of executable components.

Abstract: Systems, methods and apparatuses to intelligently migrate content involving borrowed memory are described. For example, after the prediction of a time period during which a network connection between computing devices having borrowed memory degrades, the computing devices can make a migration decision for content of a virtual memory address region, based at least in part on a predicted usage of content, a scheduled operation, a predicted operation, a battery level, etc. The migration decision can be made based on a memory usage history, a battery usage history, a location history, etc. using an artificial neural network; and the content migration can be performed by remapping virtual memory regions in the memory maps of the computing devices.

Abstract: Techniques for executing shader programs with divergent control flow on a single instruction multiple data (“SIMD”) processor are disclosed. These techniques includes detecting entry into a divergent section of a shader program and, for the work-items that enter the divergent section, placing a task entry into a task queue associated with the target of each work-item. The target is the destination, in code, of any particular work-item, and is also referred to as a code segment herein. The task queues store task entries for code segments generated by different (or the same) wavefronts. A command processor examines task lists and schedules wavefronts for execution by grouping together tasks in the same task list into wavefronts and launching those wavefronts. By grouping tasks from different wavefronts together for execution in the same front, serialization of execution is greatly reduced or eliminated.

Abstract: Recording a trace of code execution using reference bits in a processor cache. A computing device comprises processing units and a shared cache. The shared cache includes a plurality of cache lines that is each associated with a plurality of accounting bits, which each includes a reference bits portion. Stored control logic uses these reference bits to log a second read operation by a second processing unit in reference to an already logged first read operation by a first processing unit.

Abstract: A method for automatic systems devices rediscovery includes creating a hardware map of hardware components of a computing system at a time when each of the hardware components of the computing system is discoverable. The method includes determining discoverability of each hardware component in the hardware map at a point in time after creation of the hardware map, and in response to determining that a hardware component listed in the hardware map is not discoverable, initiating a reset of the hardware component.

Abstract: Herein is database administration workflow automation with source annotations and intelligent scheduling techniques for applying a hierarchy of interdependent administrative tasks to distributed and/or nested databases. In an embodiment, a source language compiler analyzes annotations to identify a hierarchy of administrative tasks that administers pluggable databases in container databases. From the annotations, a runtime codebase is generated that implements and invokes the administrative task hierarchy. At runtime, a container database management system (CDBMS) autonomously identifies and instantiates the administrative tasks, including identifying a dependency of a first administrative task on a second administrative task and a lack of dependency of a third administrative task on the second administrative task.

Abstract: The disclosure provides a method for distributing instructions in a reconfigurable processor. The reconfigurable processor includes an instruction fetch module, an instruction sync control module and an instruction queue module. The method includes: configuring a format of a Memory Sync ID Table of each instruction type, obtaining a first memory identification field and a second memory identification field of each instruction, obtaining one-hot encodings of first and second memory identification fields, obtaining a sync table and executing each instruction of a plurality of to-be-run instructions.

Abstract: Instruction scheduling in a processor using operation source parent tracking. A source parent is a producer instruction whose execution generates a produced value consumed by a consumer instruction. The processor is configured to track identifying operation source parent information for instructions processed in a pipeline and providing such operation source parent information to a scheduling circuit along with the associated consumer instruction. The scheduling circuit is configured to perform instruction scheduling using operation source parent tracking on received instruction(s) to be scheduled for execution. The processor is configured to compare sources and destinations for each of the instructions to be scheduled based on the operation source parent information to determine instructions ready for scheduling for execution.

Abstract: A display control device includes a cancellation detection unit that is configured to detect a cancellation regarding a program rewrite from first update data stored in the rewrite target ECU to second update data acquired from an external device, a write instruction unit that is configured to distribute the second update data to the rewrite target ECU and instruct the rewrite target ECU to write the second update data thereinto, and a notification instruction unit that is configured to give an instruction for notification of a progress regarding the program rewrite. The notification instruction unit is further configured to give the instruction to make the notification of the progress regarding the program rewrite in a first manner when the write instruction unit is distributing the second update data, and give the instruction to make the notification of the progress regarding the program rewrite in a second manner when the cancellation detection unit detects the cancellation.

Abstract: Disclosed herein are systems and method for adjusting data protection levels based on system metadata. A method may include monitoring a computing device for a cyberattack, wherein a kernel driver of the computing device is configured to allow access to kernel control paths and hash tables in accordance with a first protection level, and detecting that the cyberattack is in progress. While the cyberattack is in progress, the method may include identifying kernel control paths and hashes of software objects that will be affected by the cyberattack, and configuring the kernel driver to disable access to the identified kernel control paths and hashes of the software objects in accordance with a second protection level, wherein the second protection level includes greater access restrictions to the computing device than the first protection level.

Abstract: Various examples are directed to systems and methods for executing a loop in a reconfigurable compute fabric. A first flow controller may initiate a first thread at a first synchronous flow to execute a first portion of a first iteration of the loop. A second flow controller may receive a first asynchronous message instructing the second flow controller to initiate a first thread at a second synchronous flow to execute a second portion of the first iteration. The second flow controller may determine that the first iteration of the loop is the last iteration of the loop to be executed and initiate the first thread at the second synchronous flow with a last iteration flag set.

Abstract: A method, apparatus and storage medium for performing a video quality assessment (VQA) are provided. The method includes obtaining a plurality of images of a video, the plurality of images being divided into one or more groups; determining first images among the plurality of images to which a parametric-based VQA is to be applied, the first images being all of the plurality of images; determining a first score based on applying the parametric-based VQA to each of the first images; determining second images among the plurality of images to which a sample-based VQA is to be applied; determining a second score based on applying the sample-based VQA to each of the second images; and outputting a final score for at least one image based on the first score and the second score.

Abstract: A method for performing automated detection of transaction latency for a processor design model running an application in a hardware simulation accelerator. The method includes loading the processor design model into the hardware simulation accelerator, loading the application into the processor design model running within the hardware simulation accelerator, simulating the processor design model running the application within the hardware simulation accelerator, and for each individual transaction of the application: establishing a first checkpoint at a start of an execution of the individual transaction by creating a breakpoint and resetting a counter, establishing a second checkpoint at a completion of the transaction by creating another breakpoint and obtaining latency information for the second checkpoint. The latencies of the individual transaction from the start to the completion are measured based on the latency information.

Abstract: Techniques of scheduling workload(s) on partitioned resources of host systems are described. The techniques can be used, for example, in a container-orchestration system. One technique includes retrieving information characterizing at least one schedulable partition and determining an availability and a suitability of one or more of the schedulable partition(s) for executing a workload in view of the information. Each of the schedulable partition(s) includes resources of one or more host systems. The technique also includes selecting one or more of the schedulable partition(s) to execute the workload in view of the availability and the suitability.

Abstract: Application lifecycle management based on real-time resource usage. A first plurality of resource values that quantify real-time computing resources used by a first instance of an application is determined at a first point in time. Based on the first plurality of resource values, one or more utilization values are stored in a profile that corresponds to the application. Subsequent to storing the one or more utilization values in the profile, it is determined that a second instance of the application is to be initiated. The profile is accessed, and the second instance of the application is caused to be initiated on a first computing device utilizing the one or more utilization values identified in the profile.

Abstract: Apparatuses, methods of data processing, complementary instructions and programs related to atomic range-compare-and-modify operations are disclosed. Data processing operations are performed in response to received instructions, wherein the data processing operations comprise an atomic range-compare-and-modify operation, which receives indications of a data value storage location, a range start, and a range size and, as an atomic set of steps, reads a base value stored at the data value storage location, determines an in-range condition to be true when the base value is within a request range having a lower bound being the range start and an upper bound being the range start plus the range size, and when the in-range condition is true, modify the base value to an updated base value. Reduced contention between processes accessing the same data value storage location and range of locations is thus supported.

Abstract: A method may include detecting a first sub-flow, by executing a local defect analysis on code starting at a sink instruction, to a load instruction performing reading a first value using a first variable. The first sub-flow may include a first label of a first defect. The method may further include detecting a second sub-flow, by executing the local defect analysis on the code starting at a store instruction, to a load instruction performing writing a second value using a second variable. The second sub-flow may include a second label of a second defect. The method may further include determining that the first variable and the second variable are potential aliases by determining that the first label matches the second label, and obtaining, based on determining that the first variable and the second variable are potential aliases, a nonlocal flow by connecting the first sub-flow and the second sub-flow.

Abstract: A software-based instruction scoreboard indicates dependencies between closely-issued instructions issued to an arithmetic logic unit (ALU) pipeline. The software-based instruction scoreboard inserts one or more control words into the command stream between the dependent instructions, which is then executed by the ALU pipeline. The control words identify the instruction(s) upon which the dependent instructions depend (parent instructions) so that the GPU hardware can ensure that the ALU pipeline does not stall while the dependent instruction waits for results from the parent instruction.

Abstract: A processing device is described that includes a processing cluster having a message management facility and a message processing facility. The message management facility has a first message queue, a second message queue and a queue controller. The message processing facility has a plurality of processing device elements with at least two input ports, and the message processing facility is configured to: receive the selected instruction messages from the message management facility, accept or reject the selected instruction messages, return rejected selected instruction messages as a bounced instruction message to the message management facility, retrieve operand data from an accepted selected instruction message for an input port of a processing device element identified by the selected instruction message, and perform an operation designated to a processing device element once each of its input ports have received operand data.

Abstract: An apparatus to facilitate data prefetching is disclosed. The apparatus includes a cache, one or more execution units (EUs) to execute program code, prefetch logic to maintain tracking information of memory instructions in the program code that trigger a cache miss and compiler logic to receive the tracking information, insert one or more pre-fetch instructions in updated program code to prefetch data from a memory for execution of one or more of the memory instructions that triggered a cache miss and download the updated program code for execution by the one or more EUs.

Abstract: In accordance with an embodiment, a method verifies contents of a plurality of registers having two first registers, where each of the plurality of registers is configured to store a data word and a verification bit. The method includes determining whether a value of the verification bit of each respective register of the plurality of registers corresponds to the data word of its respective register. The data words stored in the two first registers are selected so that the bits of a same rank of the two first registers include two complementary bits, each bit of a common binary word is associated with a respective register of the plurality of registers, and the value of the verification bit of each respective register depends on the data word of the respective register and the bit of the common binary word associated with the respective register.

Abstract: Disclosed are methods, systems, and non-transitory computer-readable storage media for evaluating software posture as a condition of zero trust access. The present technology provides a client-side validation agent and a validation service which in tandem can capture and evaluate data representative of parameters associated with an application executing on a user device. The validation service can validate the application to a networked service, and in turn the networked service can permit communication to the application running on the user device.

Abstract: A computer-implemented method for execution of a service in a distributed environment, the method comprising performing a speculative execution of a service and storing a related result, wherein a decision whether the speculative execution of the service is performed is dependent on a dynamically changing score value and receiving a request for an execution of the service at a request proxy. Additionally, the method comprises upon determining that a valid result of the execution of the service is available from an earlier speculative execution of a comparable service, returning the valid result by the request proxy, and upon determining that a valid result of the execution of the service is not available from an earlier speculative execution of a comparable service, executing the service in a non-speculative manner, and returning a received non-speculative result by the request proxy.

Abstract: A processor for mitigating side channel attacks includes units that perform fetch, decode, and execution of instructions and pipeline control logic. The processor performs speculative and out-of-order execution of the instructions. The units detect and notify the control unit of events that cause a change from a first translation context (TC) to a second TC. In response, the pipeline control logic prevents speculative execution of instructions that are dependent in their execution on the change to the second TC until all instructions that are dependent on the first TC have completed execution, which may involve stalling their dispatch until all first-TC-dependent instructions have at least completed execution, or by tagging them and dispatching them to execution schedulers but preventing them from starting execution until all first-TC-dependent instructions have at least completed execution.

Abstract: A processor is disclosed that mitigates side channel attacks that exploit speculative store-to-load forwarding. The processor includes logic that conditions store-to-load forwarding of uncommitted store data in the store queue from an uncommitted store instruction to the load instruction upon circumstances associated with a translation context (TC) change or update. The TC comprises an address space identifier (ASID), a virtual machine identifier (VMID), a privilege mode (PM) or a combination of two or more of the ASID, VMID and PM or a derivative thereof. The logic is embedded or associated with any of several structures, such as a store queue (SQ), a memory dependence predictor (MDP), or a reorder buffer (ROB).

Abstract: An arithmetic processing apparatus includes an instruction execution control circuit that outputs an instruction from an entry of entries, including an executable instruction information storage circuit storing executable instruction information indicating whether an instruction in each of the entries is executable, a priority information storage circuit including, for each entry, storage areas storing priority information indicating whether an instruction in an entry has higher priority on an entry-by-entry basis, an executable instruction information write circuit writing the executable instruction information in response to determining whether an instruction in each of the entries is executable, a priority information write circuit writing the priority information in response to determining whether an instruction in each of the entries has higher priority, and an output determination circuit selecting an entry from which an instruction is output on a basis of the executable instruction information and the

Abstract: In a particular implementation, a method includes: receiving, at a computing device, first and second instructions of a plurality of instructions obtained from a memory, where the first instruction corresponds to a preceding instruction of a second instruction, and where the second instruction corresponds to a succeeding instruction of the first instruction; determining a dependency of the first and second instructions; sending the first and second instructions to an issue queue of the computing device; executing, at the computing device, the first and second instructions; and completing, at the computing device, the first and second instructions.

Abstract: In a particular implementation, a method includes: receiving, at a central processing unit (CPU), first and second instructions of a plurality of instructions obtained from a memory, where the first instruction corresponds to a preceding instruction of a second instruction, and where the second instruction corresponds to a succeeding instruction of the first instruction; determining a dependency of the first and second instructions; sending the first and second instructions to an issue queue of the CPU; executing, at the CPU, the first and second instructions; and completing, at the CPU, the first and second instructions.

Abstract: An execution unit circuit for use in a processor core provides efficient use of area and energy by reducing the per-entry storage requirement of a load-store unit issue queue. The execution unit circuit includes a recirculation queue that stores the effective address of the load and store operations and the values to be stored by the store operations. A queue control logic controls the recirculation queue and issue queue so that that after the effective address of a load or store operation has been computed, the effective address of the load operation or the store operation is written to the recirculation queue and the operation is removed from the issue queue, so that address operands and other values that were in the issue queue entry no longer require storage. When a load or store operation is rejected by the cache unit, it is subsequently reissued from the recirculation queue.

Abstract: In one embodiment, a processor includes fetch logic to fetch instructions, decode logic to decode the fetched instructions, and execution logic to execute at least some of the instructions. The decode logic may determine whether a flag portion of a first instruction to be folded is to be performed, and if not, accumulate a first immediate value of the first instruction with a folded immediate value obtained from an entry of an immediate buffer.

Abstract: Some embodiments of the invention provide a network forwarding element that can be dynamically reconfigured to adjust its data message processing to stay within a desired operating temperature or power consumption range. In some embodiments, the network forwarding element includes (1) a data-plane forwarding circuit (“data plane”) to process data tuples associated with data messages received by the IC, and (2) a control-plane circuit (“control plane”) for configuring the data plane forwarding circuit. The data plane includes several data processing stages to process the data tuples. The data plane also includes an idle-signal injecting circuit that receives from the control plane configuration data that the control plane generates based on the IC's temperature. Based on the received configuration data, the idle-signal injecting circuit generates idle control signals for the data processing stages.

Abstract: A method for operation of a processor core is provided. A rejected first load instruction is received that has been rejected due to a false load-hit-store detection against a first store instruction. A warning label is generated on a basis of the false load-hit-store detection. The warning label is added to the received first load instruction to create a labeled first load instruction. The labeled first load instruction is issued such that the warning label causes the labeled first load instruction to bypass the first store instruction in the store reorder queue and thereby avoid another false load-hit-store detection against the first store instruction. A computer system and a processor core configured to operate according to the method are also disclosed herein.

Abstract: In one aspect, the present disclosure relates to a method including: determining whether first data representative of a first string of content used by a user to access an application is present within the data structure having positions that contain values representative of strings of content; responsive to determination that the first data is not present within the data structure, retrieving a value from an index using a key associated with the user, the value being derived from positions in the data structure that contain values representative of a second string of content previously used by the user to access the application; decrementing the values of the positions in the data structure representative of the second string of content to remove second data representative of the second string of content from the data structure; and adding the first data representative of the first string of content to the data structure.

Abstract: Techniques are disclosed relating to an apparatus, including a data storage circuit having a plurality of entries, and a load-store pipeline configured to allocate an entry in the data storage circuit in response to a determination that a first instruction includes an access to an external memory circuit. The apparatus further includes an execution pipeline configured to make a determination, while performing a second instruction and using the entry in the data storage circuit, that the second instruction uses a result of the first instruction, and cease performance of the second instruction in response to the determination.

Abstract: Generating customized documentation is disclosed, including: receiving a set of meta information describing an aspect of an application; and generating a document to provide guidance specific to the application based at least in part on at least a subset of the set of meta information.

Abstract: A method, computer readable medium, and processor are described herein for inline data inspection by using a decoder to decode a load instruction, including a signal to cause a circuit in a processor to indicate whether data loaded by a load instruction exceeds a threshold value. Moreover, an indication of whether data loaded by a load instruction exceeds a threshold value may be stored.

Abstract: Provided are embodiments for a computer-implemented method, system and computer program product for identifying dependencies in a control sequence. Embodiments include receiving a control block that comprises a first error dependency (EDEP) level, maintaining the first EDEP level, and determining whether the received control block was successfully executed. Embodiments also include receiving a subsequent control block that comprises a second EDEP level, comparing the first EDEP level and the second EDEP level, and providing the subsequent control block for execution based at least in part on the successful execution of the received control block, and on the second EDEP level being less than or equal to the first EDEP level.

Abstract: Methods, systems and apparatuses for graph processing are disclosed. One graph streaming processor includes a thread manager, wherein the thread manager is operative to dispatch operation of the plurality of threads of a plurality of thread processors before dependencies of the dependent threads have been resolved, maintain a scorecard of operation of the plurality of threads of the plurality of thread processors, and provide an indication to at least one of the plurality of thread processors when a dependency between the at least one of the plurality of threads that a request has or has not been satisfied. Further, a producer thread provides a response to the dependency when the dependency has been satisfied, and each of the plurality of thread processors is operative to provide processing updates to the thread manager, and provide queries to the thread manager upon reaching a dependency.