Commitment Control Or Register Bypass Patents (Class 712/218)
  • Patent number: 11137980
    Abstract: A data storage system implements techniques for efficient retrieval of data stored thereon, using time of upload or another monotonically increasing variable as a key or identifier for the data to be stored and/or retrieved. Data is sorted according to, e.g., upload time, and the data is addressed with respect to time of upload and byte offset within the archive.
    Type: Grant
    Filed: September 27, 2016
    Date of Patent: October 5, 2021
    Assignee: Amazon Technologies, Inc.
    Inventors: Rishabh Animesh, Adam Frederick Brock, Umar Farooq, James Caleb Kirschner
  • Patent number: 11132199
    Abstract: A processor that includes a register file, a latency shifter, a decode unit and a plurality of functional units is introduced. The register file includes a write port. The latency shifter includes a plurality of shifter entries and shifts out a shifter entry among the shifter entries every clock cycle. Each of the shifter entries is associated with a clock cycle and each of shifter entries includes a writeback value that indicates whether the write port of the register file is available for a writeback operation in the associated clock cycles. The decode unit is configured to decode an instruction and issue the instruction according to the writeback value of the latency shifter. The functional units are coupled to the decode unit and the register file and are configured to execute the instruction issued by the decode unit and perform writeback operation to the write port of the register file.
    Type: Grant
    Filed: March 31, 2020
    Date of Patent: September 28, 2021
    Assignee: ANDES TECHNOLOGY CORPORATION
    Inventor: Thang Minh Tran
  • Patent number: 11106469
    Abstract: Methods and systems for implementing an instruction selection mechanism with class-dependent age-array are described. In an example, a system can include a processor that may sequence instructions. The system can further include a memory operatively coupled to the processor. The system can further include an array allocated on the memory. The array can be operable to store instruction age designations associated with a plurality of instructions sequenced by the processor. The array can be further operable to store the instruction age designations based on instruction classes. The processor can be operable to fetch an instruction from the memory. The processor can be operable to dispatch the instruction to a queue. The processor can be operable to store the instruction age designations associated with the instruction, in the array, based on an instruction class of the instruction.
    Type: Grant
    Filed: August 14, 2019
    Date of Patent: August 31, 2021
    Assignee: International Business Machines Corporation
    Inventor: Joel A. Silberman
  • Patent number: 11068273
    Abstract: Swapping and restoring context-specific branch predictor states on context switches in a processor. A branch prediction circuit in an instruction processing circuit of a processor includes a private branch prediction memory configured to store branch prediction states for a context of a process being executed. The branch prediction states are accessed by the branch prediction circuit to predict outcomes of its branch instructions of the process. In certain aspects, when a context switch occurs in the processor, branch prediction states stored in a private branch prediction memory and associated with the current, to-be-swapped-out context, are swapped out of the private branch prediction memory to the shared branch prediction memory. Branch prediction states in the shared branch prediction memory previously stored (i.e., swapped out) and associated with to-be-swapped-in context for execution are restored in the private branch prediction memory to be used for branch prediction.
    Type: Grant
    Filed: September 3, 2019
    Date of Patent: July 20, 2021
    Assignee: Microsoft Technology Licensing, LLC
    Inventors: Rami Mohammad Al Sheikh, Michael Scott McIlvaine
  • Patent number: 11061807
    Abstract: A method for tracing software code executing on a core of a processor is described. The method includes generating a set of packets for a trace packet stream based on a main cycle counter, which maintains a count of cycles elapsing in the core since a packet was emitted into the trace packet stream, and a commit cycle counter, which maintains a cycle count in the core since the last commit operation, wherein the generating comprises (1) storing a value of the main cycle counter in the commit cycle counter in response to detecting a commit operation and (2) storing a value of the commit cycle counter in the main cycle counter in response to detecting an abort in the core; and emitting the set of packets from the processor into the trace packet stream for tracing execution of the software code.
    Type: Grant
    Filed: December 28, 2018
    Date of Patent: July 13, 2021
    Assignee: Intel Corporation
    Inventors: Beeman Strong, Matthew C. Merten, Jason Agron
  • Patent number: 11055100
    Abstract: Embodiments of the present disclosure relate to a method for processing information, and a processor. The processor includes an arithmetic and logic unit, a bypass unit, a queue unit, a multiplexer, and a register file. The bypass unit includes a data processing subunit; the data processing subunit is configured to acquire at least one valid processing result outputted by the arithmetic and logic unit, determine a processing result from the at least one valid processing result, output the determined processing result to the multiplexer, and output processing results except for the determined processing result of among the at least one valid processing result to the queue unit; and the multiplexer is configured to sequentially output more than one valid processing results to the register file.
    Type: Grant
    Filed: July 3, 2019
    Date of Patent: July 6, 2021
    Assignee: Beijing Baidu Netcom Science and Technology Co., Ltd.
    Inventor: Jian Ouyang
  • Patent number: 11055096
    Abstract: An in-order processor has a mapping storage element to store current register mapping information identifying, for each of two or more architectural register specifiers, which physical register specifies valid data for that architectural register specifier. At least one checkpoint storage element stores checkpoint register mapping corresponding to a checkpoint of previous architectural state. This enables checkpoints to be saved and restored simply by transferring mapping information between the mapping and checkpoint storage elements, rather than transferring the actual state data.
    Type: Grant
    Filed: January 5, 2018
    Date of Patent: July 6, 2021
    Assignee: Arm Limited
    Inventors: Neil Burgess, Lee Evan Eisen
  • Patent number: 11036510
    Abstract: A merging predicated instruction controls a processing pipeline to perform a processing operation to determine a processing result based on at least one source operand, and to perform a merging operation to merge the processing result with a previous value of a destination register under control of a predicate value identifying, for each of a plurality of portions of the destination register, whether that portion is to be set to a corresponding portion of the processing result or a corresponding portion of the previous value. The merging predicated instruction is permitted to be issued to the pipeline with a timing which results in the previous value of the destination register still being unavailable when the merging predicated instruction is at a given pipeline stage at which the processing result is determined. This can help to improve performance of subsequent instructions which are independent of the merging predicated instruction.
    Type: Grant
    Filed: October 11, 2018
    Date of Patent: June 15, 2021
    Assignee: Arm Limited
    Inventors: Karel Hubertus Gerardus Walters, Chiloda Ashan Senarath Pathirane
  • Patent number: 11023232
    Abstract: In an embodiment, the present invention includes a processor having an execution logic to execute instructions and a control transfer termination (CTT) logic coupled to the execution logic. This logic is to cause a CTT fault to be raised if a target instruction of a control transfer instruction is not a CTT instruction. Other embodiments are described and claimed.
    Type: Grant
    Filed: March 13, 2019
    Date of Patent: June 1, 2021
    Assignee: Intel Corporation
    Inventors: Vedvyas Shanbhogue, Jason W. Brandt, Uday Savagaonkar, Ravi L. Sahita
  • Patent number: 11016779
    Abstract: Various embodiments are disclosed of a multiprocessor system with processing elements optimized for high performance and low power dissipation and an associated method of programming the processing elements. Each processing element may comprise a fetch unit and a plurality of address generator units and a plurality of pipelined datapaths. The fetch unit may be configured to receive a multi-part instruction, wherein the multi-part instruction includes a plurality of fields. A first address generator unit may be configured to perform an arithmetic operation dependent upon a first field of the plurality of fields. A second address generator unit may be configured to generate at least one address of a plurality of addresses, wherein each address is dependent upon a respective field of the plurality of fields. A parallel assembly language may be used to control the plurality of address generator units and the plurality of pipelined datapaths.
    Type: Grant
    Filed: August 13, 2019
    Date of Patent: May 25, 2021
    Assignee: Coherent Logix, Incorporated
    Inventors: Michael B. Doerr, Carl S. Dobbs, Michael B. Solka, Michael R. Trocino, Kenneth R. Faulkner, Keith M. Bindloss, Sumeer Arya, John Mark Beardslee, David A. Gibson
  • Patent number: 10929144
    Abstract: A computer system, processor, and method for processing information is disclosed that includes determining whether an instruction is a designated instruction, determining whether an instruction following the designated instruction is a subsequent store instruction, speculatively releasing the subsequent store instruction while the designated instruction is pending and before the subsequent store instruction is complete. Preferably, in response to determining that an instruction is the designated instruction, initiating or advancing a speculative tail pointer in an instruction completion table (ICT) to look through the instructions in the ICT following the designated instruction.
    Type: Grant
    Filed: February 6, 2019
    Date of Patent: February 23, 2021
    Assignee: International Business Machines Corporation
    Inventors: Kenneth L. Ward, Hung Q. Le, Dung Q. Nguyen, Bryan Lloyd
  • Patent number: 10922129
    Abstract: An operation processing device includes a first register unit including first registers configured to hold data to be used for an operation in an operation unit; a first selection unit that selects data held by a first register indicated by a read address signal; a second selection unit that selects, based on a bypass selection signal, data from a data group including the data selected by the first selection unit and data indicative of a result of the operation; a second register unit that outputs the data selected by the second selection unit to the operation unit; a timing adjustment unit that outputs the read address signal to the first selection unit; and a bypass control unit that stops an operation of the timing adjustment unit when generating the bypass selection signal indicative of a selection of data other than the data selected by the first selection unit.
    Type: Grant
    Filed: June 21, 2018
    Date of Patent: February 16, 2021
    Assignee: FUJITSU LIMITED
    Inventors: Seiji Hirao, Sota Sakashita
  • Patent number: 10878131
    Abstract: A hardware secure element is described. The hardware secure element includes a microprocessor and a memory, such as a non-volatile memory. The memory stores a plurality of software routines executable by the microprocessor. Each software routine starts at a respective memory start address. The hardware secure element also includes a receiver circuit and a hardware message handler module. The receiver circuit is configured to receive command data that includes a command. The hardware message handler module is configured to determine a software routine to be executed by the microprocessor as a function of the command, and also configured to provide address data to the microprocessor that indicates the software routine to be executed.
    Type: Grant
    Filed: April 27, 2018
    Date of Patent: December 29, 2020
    Assignees: STMICROELECTRONICS S.R.L., STMICROELECTRONICS APPLICATION GMBH
    Inventors: Roberto Colombo, Nicolas Bernard Grossier, Giovanni Disirio, Lorenzo Re Fiorentin
  • Patent number: 10802756
    Abstract: Systems and methods are disclosed for command status polling at a flash queue of a non-volatile memory device. The flash queue may be configured to perform polling on the status of flash operations without direct oversight from the data storage controller or firmware. In certain embodiments, a flash queue circuit may be configured to receive, from a data storage controller of a nonvolatile solid state memory (NVSSM) data storage device, one or more commands to access a flash memory of the NVSSM data storage device, each command of the one or more commands including one or more instructions. The flash queue circuit may execute the one or more commands to access the flash memory, evaluate a status response from the flash memory at the flash queue circuit, and re-execute a sequence of instructions of the one or more commands based on the status response.
    Type: Grant
    Filed: July 12, 2018
    Date of Patent: October 13, 2020
    Assignee: Seagate Technology LLC
    Inventors: Jeffrey John Pream, Jeremy Blair Goolsby
  • Patent number: 10776123
    Abstract: Systems, apparatuses, and methods for performing efficient processor pipeline flush recovery are disclosed. A processor core includes a retire queue for storing information of outstanding instructions. When the retire queue logic detects that a pipeline flush condition occurs, the logic creates one or more groups of entries in the retire queue. The logic begins the groups with an entry storing information for a youngest outstanding instruction, and creates other groups in a contiguous manner after creating this first group. The logic marks with a first indication a given group when the given group includes one or more instructions of a given type. The logic marks with a second indication the given group when the given group does not include an instruction of the given type. The logic sends to flush recovery logic information of one or more entries in only groups marked with the first indication.
    Type: Grant
    Filed: December 3, 2018
    Date of Patent: September 15, 2020
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Erik D. Swanson, Michael Estlick, Sneha V. Desai
  • Patent number: 10747542
    Abstract: A processor circuit and an operation method thereof are provided. The processor circuit includes a first alias queue module, a second alias queue module, and a pattern detection module. The pattern detection module is coupled to the first alias queue module and the second alias queue module. When a next sequential instruction pointer value of a store data instruction of the first alias queue module is matched, and a next sequential instruction pointer value of a store address instruction of the second alias queue module is matched, the pattern detection module determines that the load instruction depends on the store data instruction or the store address instruction according to a pattern value corresponding to the store data instruction.
    Type: Grant
    Filed: August 22, 2018
    Date of Patent: August 18, 2020
    Assignee: Shanghai Zhaoxin Semiconductor Co., Ltd.
    Inventor: Xiaolong Fei
  • Patent number: 10725786
    Abstract: Method and apparatus for a completion mechanism for a microprocessor are provided by marking entries in a section of an Instruction Completion Table (ICT) as ready to complete using corresponding Ready to Complete (RTC) status bits; determining a tail pointer indicating a start of the entries in the ICT that are ready for completion in a current clock cycle; performing a counting leading ones on an RTC vector that organizes the RTC status bits according to a program order for completing the entries to determine a count leading ones pointer that indicates an end of the entries in the ICT that are ready for completion in the current clock cycle; completing instructions included in the entries between the tail pointer and the count leading ones pointer in one clock cycle; and updating the tail pointer to a value of the count leading ones pointer for a subsequent clock cycle.
    Type: Grant
    Filed: August 23, 2018
    Date of Patent: July 28, 2020
    Assignee: International Business Machines Corporation
    Inventors: Kenneth L. Ward, Susan E. Eisen, Dung Q. Nguyen, Glenn O. Kincaid, Joe Lee, Deepak K. Singh
  • Patent number: 10706494
    Abstract: A method for processing data in a graphics processing unit including receiving an indication that all threads of a warp in a graphics processing unit (GPU) are to execute a same branch in a first set of instructions, storing one or more predicate bits in a memory as a single set of predicate bits, wherein the single set of predicate bits applies to all of the threads in the warp, and executing a portion of the first set of instructions in accordance with the single set of predicate bits. Executing the first set of instructions may include executing the first set of instruction in accordance with the single set of predicate bits using a single instruction, multiple data (SIMD) processing core and/or executing the first set of instruction in accordance with the single set of predicate bits using a scalar processing unit.
    Type: Grant
    Filed: August 14, 2018
    Date of Patent: July 7, 2020
    Assignee: QUALCOMM Incorporated
    Inventors: Andrew Evan Gruber, Pramod Vasant Argade, Jing Wu
  • Patent number: 10691461
    Abstract: Data processing circuitry comprises fetch circuitry to fetch blocks, containing instructions for execution, defined by a fetch queue; and prediction circuitry to predict one or more next blocks to be fetched and to add the predicted next blocks to the fetch queue; the prediction circuitry comprising: branch prediction circuitry to detect a predicted branch destination for a branch instruction in a current block, the predicted branch destination representing either a branch target for a branch predicted to be taken or a next instruction after the branch instruction, for a branch predicted not to be taken; and sequence prediction circuitry to detect sequence data, associated with the predicted branch destination, identifying a next block following the predicted branch destination in the program flow order having a next instance of a branch instruction, to add to the fetch queue the identified next block and any intervening blocks between the current block and the identified next block, and to initiate branch pr
    Type: Grant
    Filed: December 22, 2017
    Date of Patent: June 23, 2020
    Assignee: ARM Limited
    Inventors: Houdhaifa Bouzguarrou, Guillaume Bolbenes, Vincenzo Consales, Eddy Lapeyre
  • Patent number: 10691462
    Abstract: A processor and instruction graduation unit for a processor. In one embodiment, a processor or instruction graduation unit according to the present invention includes a linked-list-based multi-threaded graduation buffer and a graduation controller. The graduation buffer stores identification values generated by an instruction decode and dispatch unit of the processor as part of one or more linked-list data structures. Each linked-list data structure formed is associated with a particular program thread running on the processor. The number of linked-list data structures formed is variable and related to the number of program threads running on the processor. The graduation controller includes linked-list head identification registers and linked-list tail identification registers that facilitate reading and writing identifications values to linked-list data structures associated with particular program threads.
    Type: Grant
    Filed: December 14, 2017
    Date of Patent: June 23, 2020
    Assignee: ARM Finance Overseas Limited
    Inventor: Kjeld Svendsen
  • Patent number: 10614019
    Abstract: In general, embodiments of the technology relate to a method and system for performing fast ordered writes in a storage appliance that includes multiple separate storage modules. More specifically, embodiments of the technology enable multicasting of data to multiple storage modules in a storage appliance, where the order in which the write requests are processed is the same across all storage modules in the storage appliance.
    Type: Grant
    Filed: April 28, 2017
    Date of Patent: April 7, 2020
    Assignee: EMC IP Holding Company LLC
    Inventors: Michael Nishimoto, Samir Rajadnya
  • Patent number: 10613859
    Abstract: An execution pipeline architecture of a microprocessor employs a third-pass functional unit, for example, third-level of arithmetic logic unit (ALU) or third short-latency execution unit to execute instructions with reduced complexity and area cost of out-of-order execution. The third-pass functional unit allows instructions with long latency execution to be moved into a retire queue. The retire queue further includes the third functional unit (e.g., ALU), a reservation station and a graduate buffer. Data dependencies of dependent instructions in the retire queue is handled independently from the main pipeline.
    Type: Grant
    Filed: August 18, 2016
    Date of Patent: April 7, 2020
    Assignee: Synopsys, Inc.
    Inventor: Thang Tran
  • Patent number: 10553316
    Abstract: A system for generating an alimentary instruction set based on vibrant constitutional guidance using artificial intelligence includes a diagnostic engine operating on at least a server and configured to receive at least a biological extraction from a user and generate a diagnostic output, based on the at least a biological extraction. The system includes a plan generation module operating on the at least a server, the plan generation module designed and configured to generate, based on the diagnostic output, a comprehensive instruction set associated with the user. The system is further configured to generate an alimentary instruction set associated with the user based on the comprehensive instruction set, wherein the alimentary instruction set is configured to interact with a plurality of processes and services based on components of the alimentary instruction set.
    Type: Grant
    Filed: April 4, 2019
    Date of Patent: February 4, 2020
    Assignee: KPN Innovations, LLC
    Inventor: Kenneth Neumann
  • Patent number: 10445101
    Abstract: In a processing pipeline, hazards involving conditional instructions may be ignored when the conditional instruction would fail its test condition and there are no earlier instructions than the conditional instruction remaining which could potentially update the condition status information used to evaluate the test condition.
    Type: Grant
    Filed: August 1, 2016
    Date of Patent: October 15, 2019
    Assignee: ARM Limited
    Inventor: Spyros Lyberis
  • Patent number: 10430208
    Abstract: A method and system for using multiple versions of a software component, includes storing, in memory, a first function table that points to executable code in the memory for functions from a first version of the software component, and storing, in the memory, a second function table that points to executable code in the memory for functions from a second version of the software component, referencing the first function table, when running a first application thread, to execute the functions from the first version of the software component; and referencing the second function table, when running a second application thread that is active concurrently with the first application thread, to execute the functions from the second version of the software component.
    Type: Grant
    Filed: May 2, 2017
    Date of Patent: October 1, 2019
    Assignee: HUAWEI TECHNOLOGIES CO., LTD.
    Inventors: Kai-Ting Amy Wang, Peng Wu, Brice Dobry, Haichuan Wang
  • Patent number: 10430197
    Abstract: According to one general aspect, an apparatus may include a register circuit and an instruction scheduler circuit. The register circuit may include a plurality of physical registers that are partitioned into at least a common portion that is associated with a predefined plurality of instructions, and a shared portion, and a plurality of write ports, wherein each portion is associated with at least one respective write port. The instruction scheduler circuit configured to determine an instruction, and rename an architectural register associated with the instruction to a physical register. Wherein the portion including the physical register is selected based, at least in part, upon a characteristic of the current instruction.
    Type: Grant
    Filed: July 21, 2017
    Date of Patent: October 1, 2019
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventor: Ankit Ghiya
  • Patent number: 10338926
    Abstract: A computer implemented method for processing machine instructions by a physical processor, includes receiving a machine instruction, stored in a memory, to execute, the machine instruction including an identification of at least one first operation to execute and a conditional prefix representing a condition to verify to execute the at least one first operation; evaluating, using a management module, the prefix, and executing, using a processing unit, the at least one first operation identified in the machine instruction, according to whether the condition is verified or not.
    Type: Grant
    Filed: May 19, 2015
    Date of Patent: July 2, 2019
    Assignee: BULL SAS
    Inventor: Ghassan Chehaibar
  • Patent number: 10318302
    Abstract: Certain embodiments of the present disclosure support a method and apparatus for efficient multithreading on a single core microprocessor. Thread switching in the single core microprocessor presented herein is based on a reserved space in a memory allocated to each thread for storing and restoring of registers in a register file. The thread switching is achieved without full save and restore of the register file, and only those registers referenced in the memory are saved and restored during thread switching.
    Type: Grant
    Filed: June 3, 2016
    Date of Patent: June 11, 2019
    Assignee: Synopsys, Inc.
    Inventor: Thang Tran
  • Patent number: 10296316
    Abstract: A method is for generating a parallel program for a multicore microcomputer from processes in a single program for a single core. The method includes extraction procedure, association procedure, and analysis procedure. The extraction procedure extracts (i) an extracted address of an accessed data item, which is among data items stored in a storage area together with the processes and accessed when each process is executed and (ii) an extracted symbol name of the accessed data item. The association procedure associates an associated address in the storage area storing the accessed data item of the extracted symbol name with the extracted symbol name. The analysis procedure analyzes a dependency between each process based on the extracted address and the associated address, and determines that two processes accessing an identical address have a dependency while determining that two processes not accessing an identical address have no dependency.
    Type: Grant
    Filed: November 14, 2016
    Date of Patent: May 21, 2019
    Assignee: DENSO CORPORATION
    Inventor: Kenichi Mineda
  • Patent number: 10277955
    Abstract: A signal receiver chip may be configured to receive a satellite signal, and when the satellite signal is partially-processed off-chip, to bypass at least a portion of processing functions applied in the signal receiver chip during processing of satellite signals. The bypassed processing functions may comprise or correspond to signal band conversions. The satellite signal chip may generate an output signal, corresponding to the satellite signal, with the output signal being configured for communication to a peer device (e.g., satellite STB). The output signal may be generated and/or configured such that to enable distributing content carried in the output signal to a plurality of client devices in a local network serviced by the peer device. The signal receiver chip may combine a plurality of portions, corresponding to a plurality of satellite signals, into the output signal.
    Type: Grant
    Filed: October 13, 2015
    Date of Patent: April 30, 2019
    Assignee: MAXLINEAR, INC.
    Inventors: Raja Pullela, Glenn Chang, Curtis Ling
  • Patent number: 10241797
    Abstract: A method for reducing a number of operations replayed in a processor includes decoding an operation to determine a memory address and a command in the operation. If data is not in a way predictor based on the memory address, a suppress wakeup signal is sent to an operation scheduler, and the operation scheduler suppresses waking up other operations that are dependent on the data.
    Type: Grant
    Filed: July 17, 2012
    Date of Patent: March 26, 2019
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Ganesh Venkataramanan, Mike Butler, Krishnan V. Ramani
  • Patent number: 10209995
    Abstract: A processor core supporting out-of-order execution (OOE) includes load-hit-store (LHS) hazard prediction at the instruction execution phase, reducing load instruction rejections and queue flushes at the dispatch phase. The instruction dispatch unit (IDU) detects likely LHS hazards by generating entries for pending stores in a LHS detection table. The entries in the table contain an address field (generally the immediate field) of the store instruction and the register number of the store. The IDU compares the address field and register number for each load with entries in the table to determine if a likely LHS hazard exists and if an LHS hazard is detected, the load is dispatched to the issue queue of the load-store unit (LSU) with a tag corresponding to the matching store instruction, causing the LSU to dispatch the load only after the corresponding store has been dispatched for execution.
    Type: Grant
    Filed: October 24, 2014
    Date of Patent: February 19, 2019
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Sundeep Chadha, Richard James Eickemeyer, John Barry Griswell, Jr., Dung Quoc Nguyen
  • Patent number: 10198298
    Abstract: The technology disclosed improves existing streaming processing systems by allowing the ability to both scale up and scale down resources within an infrastructure of a stream processing system. In particular, the technology disclosed relates to a dispatch system for a stream processing system that adapts its behavior according to a computational capacity of the system based on a run-time evaluation. The technical solution includes, during run-time execution of a pipeline, comparing a count of available physical threads against a set number of logically parallel threads. When a count of available physical threads equals or exceeds the number of logically parallel threads, the solution includes concurrently processing the batches at the physical threads. Further, when there are fewer available physical threads than the number of logically parallel threads, the solution includes multiplexing the batches sequentially over the available physical threads.
    Type: Grant
    Filed: December 31, 2015
    Date of Patent: February 5, 2019
    Assignee: salesforce.com, inc.
    Inventors: Elden Gregory Bishop, Jeffrey Chao
  • Patent number: 10152396
    Abstract: A method, apparatus, and system for a time-based checkpoint target is provided for standby databases. Change records received from a primary database are applied for a standby database, creating dirty buffer queues. As the change records are applied, a mapping is maintained, which maps timestamps to logical times of change records that were most recently applied at the timestamp for the standby database. On a periodic dirty buffer queue processing interval, the mapping is used to determine a target logical time that is mapped to a target timestamp that is prior to a present timestamp by at least a checkpoint delay. The dirty buffer queues are then processed up to the target logical time, creating an incremental checkpoint. On a periodic header update interval, file headers reflecting a consistent logical time for the checkpoint are also updated. The intervals and the checkpoint delay are adjustable by user or application.
    Type: Grant
    Filed: May 5, 2014
    Date of Patent: December 11, 2018
    Assignee: Oracle International Corporation
    Inventors: Jonghyun Lee, Yunrui Li, Mahesh Baburao Girkar, Amrish Srivastava
  • Patent number: 10133582
    Abstract: A processor includes a first logic to execute an instruction stream out-of-order, the instruction stream divided into a plurality of strands, the instruction stream and each strand ordered by program order (PO). The processor also includes a second logic to determine an oldest undispatched instruction in the instruction stream and store an associated PO value of the oldest undispatched instruction as an executed instruction pointer. The instruction stream includes dispatched and undispatched instructions. The processor also includes a third logic to determine a most recently retired instruction in the instruction stream and store an associated PO value of the most recently retired instruction as a retirement pointer, a fourth logic to select a range of instructions between the retirement pointer and the executed instruction pointer, and a fifth logic to identify the range of instructions as eligible for retirement.
    Type: Grant
    Filed: December 23, 2013
    Date of Patent: November 20, 2018
    Assignee: Intel Corporation
    Inventors: Nikolay Kosarev, Sergey Y. Shishlov, Jayesh Iyer, Alexander V. Butuzov, Boris A. Babayan, Andrey Kluchnikov
  • Patent number: 10127074
    Abstract: Various embodiments include methods and apparatus structured to provide synchronization of a transaction identification between a host and a memory module using a parity check. A transaction identification can be generated at both the host and the memory module independently using incremental counters of these apparatus. Synchronization of the transaction identifications generated by the host and by a controller of the memory module can be implemented using a parity bit sequences pattern of a combination of the generated transaction identification plus the corresponding transaction command and data address. Use of transaction commands modified with respect to transaction identifications can be used in initialization of the synchronization, in message passing, and in error detection and response to errors. Additional apparatus, systems, and methods can be implemented in a variety of applications.
    Type: Grant
    Filed: January 27, 2017
    Date of Patent: November 13, 2018
    Assignee: Futurewei Technologies, Inc.
    Inventors: Xiaobing Lee, Feng Yang, Shaojie Chen
  • Patent number: 10108420
    Abstract: An apparatus including first and second reservation stations. The first reservation station dispatches a load micro instruction, and indicates on a hold bus if the load micro instruction is a specified load micro instruction directed to retrieve an operand from a prescribed resource other than on-core cache memory, where the specified load instruction requires more than a first number of clock cycles to retrieve the operand. The second reservation station is coupled to the hold bus, and dispatches one or more younger micro instructions therein that depend on the load micro instruction for execution after a number of clock cycles following dispatch of the first load micro instruction, and if it is indicated on the hold bus that the load micro instruction is the specified load micro instruction, the second reservation station is configured to stall dispatch of the one or more younger micro instructions until the load micro instruction has retrieved the operand.
    Type: Grant
    Filed: November 24, 2015
    Date of Patent: October 23, 2018
    Assignee: VIA ALLIANCE SEMICONDUCTOR CO., LTD
    Inventors: Gerard M. Col, Colin Eddy, G. Glenn Henry
  • Patent number: 10108425
    Abstract: A computing device reorders an iteratively executed sequence of instructions such that constituent instructions that require longer execution time than other constituent instructions are grouped together. The computing device inserts, within the iteratively executed sequence of instructions, one or more additional instructions to enable parallel execution of two or more instances of the sequence of instructions such that the constituent instructions that require longer execution time will be executed concurrently with the other constituent instructions.
    Type: Grant
    Filed: October 25, 2016
    Date of Patent: October 23, 2018
    Assignee: Superpowered Inc.
    Inventors: Gabor Szanto, Alexander Patrick Vlaskovits
  • Patent number: 10108429
    Abstract: An apparatus including first and second reservation stations. The first reservation station dispatches a load micro instruction, and indicates on a hold bus if the load micro instruction is a specified load micro instruction directed to retrieve an operand from a prescribed resource other than on-core cache memory. The second reservation station is coupled to the hold bus, and dispatches one or more younger micro instructions therein that depend on the load micro instruction for execution after a number of clock cycles following dispatch of the first load micro instruction, and if it is indicated on the hold bus that the load micro instruction is the specified load micro instruction, the second reservation station is configured to stall dispatch of the one or more younger micro instructions until the load micro instruction has retrieved the operand.
    Type: Grant
    Filed: December 14, 2014
    Date of Patent: October 23, 2018
    Assignee: VIA ALLIANCE SEMICONDUCTOR CO., LTD
    Inventors: Gerard M. Col, Colin Eddy, G. Glenn Henry
  • Patent number: 10108421
    Abstract: An apparatus including first and second reservation stations. The first reservation station dispatches a load micro instruction, and indicates on a hold bus if the load micro instruction is a specified load micro instruction directed to retrieve an operand from a prescribed resource other than on-core cache memory. The second reservation station is coupled to the hold bus, and dispatches one or more younger micro instructions therein that depend on the load micro instruction for execution after a number of clock cycles following dispatch of the first load micro instruction, and if it is indicated on the hold bus that the load micro instruction is the specified load micro instruction, the second reservation station is configured to stall dispatch of the one or more younger micro instructions until the load micro instruction has retrieved the operand.
    Type: Grant
    Filed: November 24, 2015
    Date of Patent: October 23, 2018
    Assignee: VIA ALLIANCE SEMICONDUCTOR CO., LTD
    Inventors: Gerard M. Col, Colin Eddy, G. Glenn Henry
  • Patent number: 10108426
    Abstract: Embodiments include issuing dynamic issue masks for processor hang prevention. Aspects include storing an instruction in an issue queue for execution by an execution unit, the instruction including a default issue mask. Aspects further include determining whether the instruction in the issue queue is likely to be rescinded by the execution unit. Based on determining that the instruction is not likely to be rescinded by the execution unit, aspects include issuing the instruction to the execution unit with the default issue mask. Based on determining that the instruction is likely to be rescinded by the execution unit, aspects include issuing the instruction to the execution unit with a likely to be rescinded issue mask.
    Type: Grant
    Filed: September 1, 2015
    Date of Patent: October 23, 2018
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Gregory W. Alexander, Steven R. Carlough, Lee E. Eisen, David A. Schroter
  • Patent number: 10108428
    Abstract: An apparatus including first and second reservation stations. The first reservation station dispatches a load micro instruction, and indicates on a hold bus if the load micro instruction is a specified load micro instruction directed to retrieve an operand from a prescribed resource other than on-core cache memory, where the specified load instruction requires more than a first number of clock cycles to retrieve the operand. The second reservation station is coupled to the hold bus, and dispatches one or more younger micro instructions therein that depend on the load micro instruction for execution after a number of clock cycles following dispatch of the first load micro instruction, and if it is indicated on the hold bus that the load micro instruction is the specified load micro instruction, the second reservation station is configured to stall dispatch of the one or more younger micro instructions until the load micro instruction has retrieved the operand.
    Type: Grant
    Filed: December 14, 2014
    Date of Patent: October 23, 2018
    Assignee: VIA ALLIANCE SEMICONDUCTOR CO., LTD
    Inventors: Gerard M. Col, Colin Eddy, G. Glenn Henry
  • Patent number: 10102002
    Abstract: Embodiments include issuing dynamic issue masks for processor hang prevention. Aspects include storing an instruction in an issue queue for execution by an execution unit, the instruction including a default issue mask. Aspects further include determining whether the instruction in the issue queue is likely to be rescinded by the execution unit. Based on determining that the instruction is not likely to be rescinded by the execution unit, aspects include issuing the instruction to the execution unit with the default issue mask. Based on determining that the instruction is likely to be rescinded by the execution unit, aspects include issuing the instruction to the execution unit with a likely to be rescinded issue mask.
    Type: Grant
    Filed: September 30, 2014
    Date of Patent: October 16, 2018
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Gregory W. Alexander, Steven R. Carlough, Lee E. Eisen, David A. Schroter
  • Patent number: 10102158
    Abstract: Methods and apparatus relating to the transfer of data for processing and/or the transfer of the resulting processed data are described. Some features relate to a processing system which performs data transfers under control of a Dynamic Sequence Controller (DSC). In various embodiments a sequence of operational codes is used to control data transfer with the status of data source and destination locations taken into consideration. Modification of the op code sequence used to control the dynamic sequence controller and thus the transfer of data can be performed asynchronously to control of processing units which can be controlled via a command and control bus used to control the function of operators which process the data provided via the data bus.
    Type: Grant
    Filed: December 31, 2014
    Date of Patent: October 16, 2018
    Assignee: Accusoft Corporation
    Inventor: Robert M Nally
  • Patent number: 10102142
    Abstract: A method for detecting an instruction ordering violation in a CPU. The method includes receiving a reordered stream of instructions and detecting whether an ordering violation has occurred by using virtual addresses. The method further includes transferring results of the reordered stream of instructions from a load store buffer into a cache and detecting whether an ordering violation has occurred by using physical addresses. Subsequently, a recovery is initiated upon detection of an ordering violation.
    Type: Grant
    Filed: December 26, 2012
    Date of Patent: October 16, 2018
    Assignee: Nvidia Corporation
    Inventors: Guillermo J. Rozas, Bharath Krishnan, James Van Zoeren
  • Patent number: 10095647
    Abstract: An accelerated processor structure on a programmable integrated circuit device includes a processor and a plurality of configurable digital signal processors (DSPs). Each configurable DSP includes a circuit block, which in turn includes a plurality of multipliers. The accelerated processor structure further includes a first bus to transfer data from the processor to the configurable DSPs, and a second bus to transfer data from the configurable DSPs to the processor.
    Type: Grant
    Filed: May 29, 2015
    Date of Patent: October 9, 2018
    Assignee: Altera Corporation
    Inventors: David Shippy, Martin Langhammer, Jeffrey Eastlack
  • Patent number: 10083035
    Abstract: A streaming engine employed in a digital data processor specifies fixed first and second read only data streams. Corresponding stream address generator produces address of data elements of the two streams. Corresponding steam head registers stores data elements next to be supplied to functional units for use as operands. The two streams share two memory ports. A toggling preference of stream to port ensures fair allocation. The arbiters permit one stream to borrow the other's interface when the other interface is idle. Thus one stream may issue two memory requests, one from each memory port, if the other stream is idle. This spreads the bandwidth demand for each stream across both interfaces, ensuring neither interface becomes a bottleneck.
    Type: Grant
    Filed: December 20, 2016
    Date of Patent: September 25, 2018
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Joseph Zbiciak, Timothy Anderson
  • Patent number: 10025554
    Abstract: An apparatus and a corresponding method for processing a sequence of received data items are disclosed. The processing is performed by multiple processing elements. A reorder buffer comprising multiple slots is used to maintain the order of the received data items, wherein a processing element reserves a next available slot in the reorder buffer before beginning processing the next data item of the sequence of received data items. On completion of the processing a buffer change indicator value is read by the processing element when seeking to insert the processed data item into the reserved slot. If the buffer change indicator changes during the course of the insertion process, this serves as an indication to the processing element that another processing element is modifying the content of the reorder buffer in parallel. A check may be repeated for at least one subsequent already-processed data item, since this latter data item may have become ready to be retired from the reorder buffer.
    Type: Grant
    Filed: September 19, 2016
    Date of Patent: July 17, 2018
    Assignee: ARM Limited
    Inventor: Eric Ola Harald Liljedahl
  • Patent number: 9952901
    Abstract: Described herein are technologies related to enforcing thread dependency using a hybrid scoreboard. An encoded video information that includes a plurality of threads is received, a first set and a second set of threads from the plurality of thread is determined, the first and second sets of threads are assigned to a hardware and a software, respectively, and dependency threads in the first and second sets of threads is enforced.
    Type: Grant
    Filed: December 9, 2014
    Date of Patent: April 24, 2018
    Assignee: Intel Corporation
    Inventors: Haihua Wu, Julia A. Gould, Li-An Tang
  • Patent number: 9934039
    Abstract: Methods of predicting stack pointer values of variables stored in a stack are described. When an instruction is seen which stores a variable in the stack in a position offset from the stack pointer, an entry is added to a data structure which identifies the physical register which currently stores the stack pointer, the physical register which stores the value of the variable and the offset value. Subsequently when an instruction to load a variable from the stack from a position which is identified by reference to the stack pointer is seen, the data structure is searched to see if there is a corresponding entry which includes the same offset and the same physical register storing the stack pointer as the load instruction. If a corresponding entry is found the architectural register in the load instruction is mapped to the physical register storing the value of the variable from the entry.
    Type: Grant
    Filed: January 16, 2015
    Date of Patent: April 3, 2018
    Assignee: MIPS Tech Limited
    Inventor: Hugh Jackson