Logic Operation Instruction Processing Patents (Class 712/223)
  • Patent number: 10321131
    Abstract: Techniques for context-adaptive binary arithmetic coding (CABAC) coding with a reduced number of context coded and/or bypass coded bins are provided. Rather than using only truncated unary binarization for the syntax element representing the delta quantization parameter and context coding all of the resulting bins as in the prior art, a different binarization is used and only part of the resulting bins are context coded, thus reducing the worst case number of context coded bins for this syntax element. Further, binarization techniques for the syntax element representing the remaining actual value of a transform coefficient are provided that restrict the maximum codeword length of this syntax element to 32 bits or less, thus reducing the number of bypass coded bins for this syntax element over the prior art.
    Type: Grant
    Filed: February 13, 2017
    Date of Patent: June 11, 2019
    Assignee: Texas Instruments Incorporated
    Inventors: Vivienne Sze, Madhukar Budagavi
  • Patent number: 10223112
    Abstract: A method of an aspect includes receiving an instruction. The instruction indicates an integer stride, indicates an integer offset, and indicates a destination storage location. A result is stored in the destination storage location in response to the instruction. The result includes a sequence of at least four integers in numerical order with a smallest one of the at least four integers differing from zero by the integer offset and with all integers of the sequence in consecutive positions differing by the integer stride. Other methods, apparatus, systems, and instructions are disclosed.
    Type: Grant
    Filed: September 30, 2017
    Date of Patent: March 5, 2019
    Inventors: Seth Abraham, Elmoustapha Ould-Ahmed-Vall, Robert Valentine, Zeev Sperber, Amit Gradstein
  • Patent number: 10037205
    Abstract: Vector blend and permute functionality are provided, responsive to instructions specifying: a destination vector register comprising fields to store vector elements, a first vector register, a vector element size, a second vector register, and a third operand. Indices are read from fields in the second register. Each index has a first selector portion and a second selector portion. Corresponding unmasked vector elements are stored to fields of the destination register, wherein each vector element, responsive to the respective first selector portion having a first value, is copied to an intermediate vector from a corresponding data field of the first register, and responsive to the respective first selector portion having a second value, is copied to the intermediate vector from a corresponding data field of the third operand. Then unmasked data fields of the destination are replaced by data fields in the intermediate vector indexed by the corresponding second selector portions.
    Type: Grant
    Filed: December 23, 2011
    Date of Patent: July 31, 2018
    Assignee: Intel Corporation
    Inventors: Robert Valentine, Bret L. Toll, Jesus Corbal, Jeffrey G. Wiedemeier, Sridhar Samudrala
  • Patent number: 9996361
    Abstract: A processor comprises a first register to store a plurality of data items at a plurality of positions within the first register, a second register, and an execution unit, operatively coupled to the first register and the second register, the execution unit comprising a logic circuit implementing a sort instruction for sorting the plurality of data items stored in the first register in an order of data item values, and storing, in the second register, a plurality of indices, wherein each index identifies a position associated with a data item stored in the first register prior to the sorting.
    Type: Grant
    Filed: December 23, 2015
    Date of Patent: June 12, 2018
    Assignee: Intel Corporation
    Inventors: Asit K. Mishra, Kshitij A. Doshi, Elmoustapha Ould-Ahmed-Vall, Deborah T. Marr
  • Patent number: 9922039
    Abstract: Embodiments are directed to techniques for allowing write operations to proceed on units smaller than a block. Merely decreasing the block size is not desirable, however, since many files are written in large chunks at once, and larger block sizes can increase speed and decrease the amount of overhead metadata required. Therefore, in order to maintain large block sizes while still obtaining the benefit of being able to make small writes when necessary, blocks may be divided into sub-blocks. Unaligned writes that do not fill up an entire block may be segregated and stored separately from aligned writes, the unaligned writes having finer granularity. These techniques may result in faster operation for unaligned writes. They also especially benefit systems using compression because they allow efficiently partially overwriting compressed blocks.
    Type: Grant
    Filed: March 31, 2016
    Date of Patent: March 20, 2018
    Assignee: EMC IP Holding Company LLC
    Inventors: Philippe Armangau, Christopher A. Seibel, Ahsan Rashid
  • Patent number: 9898251
    Abstract: The invention relates to a processor comprising, in its instruction set, a bit matrix multiplication instruction (sbmm) having a first double precision operand (A) representing a first matrix to multiply, a second operand (B) explicitly designating any two single precision registers whose joint contents represent a second matrix to multiply, and a destination parameter (C) explicitly designating any two single precision registers for jointly containing a matrix representing the result of the multiplication.
    Type: Grant
    Filed: May 19, 2015
    Date of Patent: February 20, 2018
    Assignee: KALRAY
    Inventors: Benoît Dupont De Dinechin, Marta Rybczynska
  • Patent number: 9823924
    Abstract: A Vector Element Rotate and Insert Under Mask instruction. Each element of a second operand of the instruction is rotated in a specified direction by a specified number of bits. For each bit in a third operand of the instruction that is set to one, the corresponding bit of the rotated elements in the second operand replaces the corresponding bit in a first operand of the instruction.
    Type: Grant
    Filed: January 23, 2013
    Date of Patent: November 21, 2017
    Assignee: International Business Machines Corporation
    Inventors: Jonathan D. Bradbury, Robert F. Enenkel, Eric M. Schwarz, Timothy J. Slegel
  • Patent number: 9823926
    Abstract: A Vector Element Rotate and Insert Under Mask instruction. Each element of a second operand of the instruction is rotated in a specified direction by a specified number of bits. For each bit in a third operand of the instruction that is set to one, the corresponding bit of the rotated elements in the second operand replaces the corresponding bit in a first operand of the instruction.
    Type: Grant
    Filed: December 5, 2014
    Date of Patent: November 21, 2017
    Assignee: International Business Machines Corporation
    Inventors: Jonathan D. Bradbury, Robert F. Enenkel, Eric M. Schwarz, Timothy J. Slegel
  • Patent number: 9772824
    Abstract: Embodiments relate to program structure-based blocking. An aspect includes receiving source code corresponding to a computer program by a compiler of a computer system. Another aspect includes determining a prefetching section in the source code by a marking module of the compiler. Yet another aspect includes performing, by a blocking module of the compiler, blocking of instructions located in the prefetching section into instruction blocks, such that the instruction blocks of the prefetching section only contain instructions that are located in the prefetching section.
    Type: Grant
    Filed: March 25, 2015
    Date of Patent: September 26, 2017
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Carlo Bertolli, Alexandre E. Eichenberger, John K. O'Brien, Zehra N. Sura
  • Patent number: 9696976
    Abstract: A method, computer system and computer program for optimizing the processing of a character string during execution of the program by using characteristic information that indicates a characteristic of the character string and is associated with the character string. The method includes the steps of determining, on the basis of a characteristic of a first character string and operation for the first character string, a characteristic information of at least one of the first character string and a second character string obtained as a result of the operation, and associating the characteristic information with the at least one character string.
    Type: Grant
    Filed: May 26, 2010
    Date of Patent: July 4, 2017
    Assignee: International Business Machines Corporation
    Inventors: Kazuaki Ishizaki, Kiyokuni Kawachiya, Kazunori Ogata
  • Patent number: 9584802
    Abstract: Techniques for context-adaptive binary arithmetic coding (CABAC) coding with a reduced number of context coded and/or bypass coded bins are provided. Rather than using only truncated unary binarization for the syntax element representing the delta quantization parameter and context coding all of the resulting bins as in the prior art, a different binarization is used and only part of the resulting bins are context coded, thus reducing the worst case number of context coded bins for this syntax element. Further, binarization techniques for the syntax element representing the remaining actual value of a transform coefficient are provided that restrict the maximum codeword length of this syntax element to 32 bits or less, thus reducing the number of bypass coded bins for this syntax element over the prior art.
    Type: Grant
    Filed: April 14, 2013
    Date of Patent: February 28, 2017
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Vivienne Sze, Madhukar Budagavi
  • Patent number: 9524168
    Abstract: An apparatus and method are described for shuffling data elements from source registers to a destination register.
    Type: Grant
    Filed: December 23, 2011
    Date of Patent: December 20, 2016
    Assignee: Intel Corporation
    Inventors: Elmoustapha Ould-Ahmed-Vall, Robert Valentine, Jesus Corbal, Tal Uliel, Bret L Toll
  • Patent number: 9485507
    Abstract: A digital processor for recovering a source bitstream from an encoded bitstream that has been encoded according to a context adaptive binary arithmetic coding (CABAC) algorithm. The processor includes a first execution unit and a second execution unit. The first execution unit generates first execution data by operating on a first register and a second register, and stores the first execution data in the first register. The first execution data includes a current output bit, a temporary range value and a temporary offset value. The current output bit corresponds to a bit of the source bitstream. The second execution unit generates second execution data by operating on the first register and the second register, and stores the second execution data in the second register. The second execution data includes a normalized range value and a normalized offset value.
    Type: Grant
    Filed: January 8, 2014
    Date of Patent: November 1, 2016
    Assignee: Advanced Micro Devices, Inc.
    Inventor: Michael Frank
  • Patent number: 9256434
    Abstract: Methods of bit manipulation within a computer processor are disclosed. Improved flexibility in bit manipulation proves helpful in computing elementary functions critical to the performance of many programs and for other applications. In one embodiment, a unit of input data is shifted/rotated and multiple non-contiguous bit fields from the unit of input data are inserted in an output register. In another embodiment, one of two units of input data is optionally shifted or rotated, the two units of input data are partitioned into a plurality of bit fields, bitwise operations are performed on each bit field, and pairs of bit fields are combined with either an AND or an OR bitwise operation. Embodiments are also disclosed to simultaneously perform these processes on multiple units and pairs of units of input data in a Single Input, Multiple Data processing environment capable of performing logical operations on floating point data.
    Type: Grant
    Filed: March 15, 2013
    Date of Patent: February 9, 2016
    Assignee: International Business Machines Corporation
    Inventors: Christopher Kumar Anand, Simon Christopher Broadhead, Robert Frederick Enenkel
  • Patent number: 9146743
    Abstract: Methods of bit manipulation within a computer processor are disclosed. Improved flexibility in bit manipulation proves helpful in computing elementary functions critical to the performance of many programs and for other applications. In one embodiment, a unit of input data is shifted/rotated and multiple non-contiguous bit fields from the unit of input data are inserted in an output register. In another embodiment, one of two units of input data is optionally shifted or rotated, the two units of input data are partitioned into a plurality of bit fields, bitwise operations are performed on each bit field, and pairs of bit fields are combined with either an AND or an OR bitwise operation. Embodiments are also disclosed to simultaneously perform these processes on multiple units and pairs of units of input data in a Single Input, Multiple Data processing environment capable of performing logical operations on floating point data.
    Type: Grant
    Filed: July 11, 2012
    Date of Patent: September 29, 2015
    Assignee: International Business Machines Corporation
    Inventors: Christopher K. Anand, Simon C. Broadhead, Robert F. Enenkel
  • Patent number: 9075600
    Abstract: A computer implemented method of processing instructions of a computer program. The method comprises providing at least two copies of program status data; identifying a first update instruction of the instructions that writes to at least one field of the program status data; and associating the first update instruction with a first copy of the at least two copies of program status data.
    Type: Grant
    Filed: June 24, 2010
    Date of Patent: July 7, 2015
    Assignee: International Business Machines Corporation
    Inventors: Gregory W. Alexander, Brian D. Barrick, Michael Billeci, Fadi Y. Busaba, Bruce C. Giamei, David A. Schroter
  • Patent number: 9069547
    Abstract: Method, apparatus, and program means for performing a string comparison operation. In one embodiment, an apparatus includes execution resources to execute a first instruction. In response to the first instruction, said execution resources store a result of a comparison between each data element of a first and second operand corresponding to a first and second text string, respectively.
    Type: Grant
    Filed: September 22, 2006
    Date of Patent: June 30, 2015
    Assignee: Intel Corporation
    Inventors: Michael A. Julier, Jeffrey D. Gray, Srinivas Chennupaty, Sean P. Mirkes, Mark P. Seconi
  • Patent number: 9043576
    Abstract: System and method for conversion of virtual machine files without requiring copying of the virtual machine payload (data) from one location to another location. By eliminating this step, applicant's invention significantly enhances the efficiency of the conversion process. In one embodiment, a file system or storage system provides indirections to locations of data elements stored on a persistent storage media. A source virtual machine file includes hypervisor metadata (HM) data elements in one hypervisor file format, and virtual machine payload (VMP) data elements.
    Type: Grant
    Filed: August 21, 2013
    Date of Patent: May 26, 2015
    Assignee: SimpliVity Corporation
    Inventors: Jesse St. Laurent, James E. King, III
  • Patent number: 9009444
    Abstract: A method, computer program product, and computing system for receiving a reservation for a LUN from Host A, wherein the LUN is defined within a data array. A lock for the LUN is defined as Host A. A write request is received for the LUN from Host B. The lock for the LUN is defined as Transitioning A to B. The write request is delayed for a defined period of time.
    Type: Grant
    Filed: September 29, 2012
    Date of Patent: April 14, 2015
    Assignee: EMC Corporation
    Inventors: Philip Derbeko, Arieh Don, Anat Eyal, Kevin F. Martin, Richard A. Trabing
  • Publication number: 20150006860
    Abstract: A rotate then operate instruction having a T bit is fetched and executed wherein a first operand in a first register is rotated by an amount and a Boolean operation is performed on a selected portion of the rotated first operand and a second operand in of a second register. If the T bit is ‘0’ the selected portion of the result of the Boolean operation is inserted into corresponding bits of a second operand of a second register. If the T bit is ‘1’, in addition to the inserted bits, the bits other than the selected portion of the rotated first operand are saved in the second register.
    Type: Application
    Filed: September 12, 2014
    Publication date: January 1, 2015
    Inventors: Dan F. Greiner, Timothy J. Slegel, Joachim von Buttlar
  • Publication number: 20140365750
    Abstract: A system, method, and computer program product for generating flow-control signals for a processing pipeline is disclosed. The method includes the steps of generating, by a first pipeline stage, a delayed ready signal based on a downstream ready signal received from a second pipeline stage and a throttle disable signal. A downstream valid signal is generated by the first pipeline stage based on an upstream valid signal and the delayed ready signal. An upstream ready signal is generated by the first pipeline stage based on the delayed ready signal and the downstream valid signal.
    Type: Application
    Filed: June 10, 2013
    Publication date: December 11, 2014
    Inventors: Philip Payman Shirvani, Peter Benjamin Sommers, Eric T. Anderson
  • Patent number: 8843730
    Abstract: An apparatus includes a processor and a memory coupled to the processor. The memory stores an instruction packet (e.g., a VLIW instruction packet) including a first predicate independent instruction and a second predicate independent instruction. Each of the predicate independent instructions has the same destination.
    Type: Grant
    Filed: September 9, 2011
    Date of Patent: September 23, 2014
    Assignee: QUALCOMM Incorporated
    Inventors: Erich J. Plondke, Lucian Codrescu, Mao Zeng, Charles Joseph Tabony, Suresh K. Venkumahanti
  • Publication number: 20140281422
    Abstract: A method for sorting elements in hardware structures is disclosed. The method comprises selecting a plurality of elements to order from an unordered input queue (UIQ) within a predetermined range in response to finding a match between at least one most significant bit of the predetermined range and corresponding bits of a respective identifier associated with each of the plurality of elements. The method further comprises presenting each of the plurality of elements to a respective multiplexer. Further the method comprises generating a select signal for an enabled multiplexer in response to finding a match between at least one least significant bit of a respective identifier associated with each of the plurality of elements and a port number of the ordered queue. Finally, the method comprises forwarding a packet associated with a selected element identifier to a matching port number of the ordered queue from the enabled multiplexer.
    Type: Application
    Filed: October 11, 2013
    Publication date: September 18, 2014
    Applicant: Soft Machines, Inc.
    Inventors: Mohammad A. ABDALLAH, Mandeep SINGH
  • Publication number: 20140250288
    Abstract: Systems and methods allow formulation of embeddings of problems via targeted hardware (e.g., particular quantum processor). In a first stage, sets of connected subgraphs are successively generated, each set including a respective subgraph for each decision variable in the problem graph, adjacent decisions variables in the problem graph mapped to respective vertices in the hardware graph, the respective vertices which are connected by at least one respective edge in the hardware graph. In a second stage, the connected subgraphs are refined such that no vertex represents more than a single decision variable.
    Type: Application
    Filed: December 17, 2013
    Publication date: September 4, 2014
    Applicant: D-Wave Systems Inc.
    Inventor: Aidan Patrick Roy
  • Publication number: 20140223146
    Abstract: Reading a value into a register, checking to see if the value is a NULL, and then jumping out of a loop if the value is a NULL is a common task that processors perform. To speed performance of such a task, a novel “blank bit” is added to the flag register of a processor. When a first instruction (arithmetic, logic or load) is executed, the instruction operands are checked to see if any is a NULL character value. Information on the result of the check is stored in the blank bit. Execution of a second instruction uses the information stored in the blank bit to determine whether or not a second operation (for example, a jump) will be performed. By using the first and second instructions in a loop, the number of instructions executed to check for NULLs at the end of strings and arrays is reduced.
    Type: Application
    Filed: April 8, 2014
    Publication date: August 7, 2014
    Applicant: IXYS CH GmbH
    Inventor: Gyle D. Yearsley
  • Publication number: 20140223147
    Abstract: A virtual parallel computing system and method represents bits with matrices and computes over all input states in parallel through a sequence of matrix operations. The matrix operations relate to logic gate operators to carry out a function implementation that represents a problem to be solved. Initial matrices are prepared to encode the weights of all input states, which can be binary states. Intermediate results can be simplified to decrease computational complexity while maintaining useful approximation results. The final matrices can encode the answer(s) to the problem represented by the function implementation. The system and method are particularly useful in speeding up database searches and in counting solutions of satisfiability problems.
    Type: Application
    Filed: February 7, 2013
    Publication date: August 7, 2014
    Inventors: Claudio Chamon, Eduardo R. Mucciolo
  • Patent number: 8782379
    Abstract: A device employing techniques to optimize Context-based Adaptive Binary Arithmetic Coding (CABAC) for the H.264 video decoding is provided. The device includes a processing circuit operative to implement a set of instructions to decode multiple bins simultaneously and renormalize an offset register and a range register after the multiple bins are decoded. The range register and offset registers may be 32 or 64 bits. The use of a larger range register allows renormalization to be skipped when enough bits are still in the range register.
    Type: Grant
    Filed: September 27, 2007
    Date of Patent: July 15, 2014
    Assignee: QUALCOMM Incorporated
    Inventors: Zhen Liu, Kai Wang, Yiliang Bao
  • Publication number: 20140189322
    Abstract: Embodiments of systems, apparatuses, and methods for counting instructions of a particular type are described herein. In some embodiments, a processor includes a plurality of write mask registers, logic to determine write mask register usage of an instruction in a particular manner and a counter to count a number of instances of instructions that have been determined to use a write mask register in the particular manner.
    Type: Application
    Filed: December 28, 2012
    Publication date: July 3, 2014
    Inventor: Elmoustapha OULD-AHMED-VALL
  • Publication number: 20140149721
    Abstract: A method, computer program product, and system are provided for multi-input bitwise logical operations. The method includes the steps of receiving a multi-input bitwise logical operation instruction that specifies two or more input operands and a function operand, where a first input operand of the two or more input operands comprises a number of bits, each bit having a corresponding bit in each of the additional input operands in the two or more input operands. The function operand is written to a lookup table. Then, the lookup table is accessed for each set of corresponding input operand bits in the two or more input operands to generate an output for the multi-input bitwise logical operation instruction.
    Type: Application
    Filed: November 26, 2012
    Publication date: May 29, 2014
    Applicant: NVIDIA CORPORATION
    Inventor: Alexey Yuryevich Panteleev
  • Publication number: 20140122839
    Abstract: An apparatus is described that includes an execution unit within an instruction pipeline. The execution unit has multiple stages of a circuit that includes a) and b) as follows. a) a first logic circuitry section having multiple mix logic sections each having: i) a first input to receive a first quad word and a second input to receive a second quad word; ii) an adder having a pair of inputs that are respectively coupled to the first and second inputs; iii) a rotator having a respective input coupled to the second input; iv) an XOR gate having a first input coupled to an output of the adder and a second input coupled to an output of the rotator. b) permute logic circuitry having inputs coupled to the respective adder and XOR gate outputs of the multiple mix logic sections.
    Type: Application
    Filed: December 22, 2011
    Publication date: May 1, 2014
    Inventors: Gilbert M. Wolrich, Kirk S. Yap, James D. Guilford, Erdinc Ozturk, Vinodh Gopal, Wajdi K. Feghali, Sean M. Gulley, Martin G. Dixon
  • Publication number: 20140095844
    Abstract: Disclosed herein are systems, apparatuses, and methods performing in a computer processor of performing a rotate and XOR in response to a single XOR and rotate instruction, wherein the rotate and XOR instruction includes a first and second source operand, a destination operand, and an immediate value.
    Type: Application
    Filed: September 28, 2012
    Publication date: April 3, 2014
    Inventors: Vinodh Gopal, Gilbert M. Wolrich, James D. Guilford, Kirk S. Yap
  • Publication number: 20140095845
    Abstract: An apparatus and method are described for performing efficient Boolean operations in a pipelined processor which, in one embodiment, does not natively support three operand instructions. For example, a processor according to one embodiment of the invention comprises: a set of registers for storing packed operands; Boolean operation logic to execute a single instruction which uses three or more source operands packed in the set of registers, the Boolean operation logic to read at least three source operands and an immediate value to perform a Boolean operation on the three source operands, wherein the Boolean operation comprises: combining a bit read from each of the three operands to form an index to the immediate value, the index identifying a bit position within the immediate value; reading the bit from the identified bit position of the immediate value; and storing the bit from the identified bit position of the immediate value in a destination register.
    Type: Application
    Filed: September 28, 2012
    Publication date: April 3, 2014
    Inventors: Vinodh Gopal, Wajdi Feghali, Gilbert Wolrich, Kirk Yap
  • Patent number: 8624916
    Abstract: One embodiment of the invention sets forth a CROP configured to perform both color raster operations and atomic transactions. Upon receiving an atomic transaction, the distribution unit within the CROP transmits a read request to the L2 cache for retrieving the destination operand. The distribution unit also transmits the source operands and the operation code to the latency buffer for storage until the destination operand is retrieved from the L2 cache. The processing pipeline transmits the operation code, the source and destination operands and an atomic flag to the blend unit for processing. The blend unit performs the atomic transaction on the source and destination operands based on the operation code and returns the result of the atomic transaction to the processing pipeline for storage in the internal cache. The processing pipeline writes the result of the atomic transaction to the L2 cache for storage at the memory location associated with the atomic transaction.
    Type: Grant
    Filed: April 1, 2013
    Date of Patent: January 7, 2014
    Assignee: Nvidia Corporation
    Inventors: Narayan Kulshrestha, Adam Paul Dreyer, Chad D. Walker, Rui M. Bastos
  • Patent number: 8607241
    Abstract: A method, apparatus, and system are provided for performing compare and exchange operations using a sleep-wakeup mechanism. According to one embodiment, an instruction at a processor is executed to help acquire a lock on behalf of the processor. If the lock is unavailable to be acquired by the processor, the instruction is put to sleep until an event has occurred.
    Type: Grant
    Filed: June 30, 2004
    Date of Patent: December 10, 2013
    Assignee: Intel Corporation
    Inventors: Bratin Saha, Matthew C. Merten, Per Hammarlund
  • Patent number: 8583904
    Abstract: Embodiments of a system and a method in which a processor may execute instructions that cause the processor to receive an input vector and a control vector are disclosed. The executed instructions may also cause the processor to perform a negation operation dependent upon the input vector and the control vector.
    Type: Grant
    Filed: September 27, 2012
    Date of Patent: November 12, 2013
    Assignee: Apple Inc.
    Inventor: Jeffry E. Gonion
  • Patent number: 8560815
    Abstract: Embodiments of a system and a method in which a processor may execute instructions that cause the processor to receive an input vector and a control vector are disclosed. The executed instructions may also cause the processor to perform a Boolean operation on another input vector dependent upon the input vector and the control vector.
    Type: Grant
    Filed: September 27, 2012
    Date of Patent: October 15, 2013
    Assignee: Apple Inc.
    Inventor: Jeffry E. Gonion
  • Publication number: 20130254517
    Abstract: An apparatus for processing an invalid operation in a prologue and/or an epilogue of a loop includes a register file including a first region for storing a data validity value indicating whether data is valid or invalid, and a second region for storing the data; and a functional unit configured to determine whether an operation is valid or invalid based on a value of a first region of each of one or more input sources received from the register file, and output a destination including a value based on the value of the first region of each of the input sources
    Type: Application
    Filed: March 15, 2013
    Publication date: September 26, 2013
    Applicants: Seoul National University R&DB Foundation, Samsung Electronics Co., Ltd.
    Inventors: Seong-Hun Jeong, Bernhard Egger, Won-Sub Kim
  • Patent number: 8539206
    Abstract: An apparatus and method are described for performing arbitrary logical operations specified by a table. For example, one embodiment of a method for performing a logical operation on a computer processor comprises: reading data from each of two or more source operands; combining the data read from the source operands to generate an index value, the index value identifying a subset of bits within an immediate value transmitted with an instruction; reading the bits from the immediate value; and storing the bits read from the immediate value within a destination register to generate a result of the instruction.
    Type: Grant
    Filed: September 24, 2010
    Date of Patent: September 17, 2013
    Assignee: Intel Corporation
    Inventor: Andrew T. Forsyth
  • Publication number: 20130227253
    Abstract: A method and apparatus for including in a processor instructions for performing logical-comparison and branch support operations on packed or unpacked data. In one embodiment, instruction decode logic decodes instructions for an execution unit to operate on packed data elements including logical comparisons. A register file including 128-bit packed data registers stores packed single-precision floating point (SPFP) and packed integer data elements. The logical comparisons may include comparison of SPFP data elements and comparison of integer data elements and setting at least one bit to indicate the results. Based on these comparisons, branch support actions are taken. Such branch support actions may include setting the at least one bit, which in turn may be utilized by a branching unit in response to a branch instruction. Alternatively, the branch support actions may include branching to an indicated target code location.
    Type: Application
    Filed: March 15, 2013
    Publication date: August 29, 2013
    Inventors: Rajiv Kapoor, Ronen Zohar, Mark J. Buxton, Zeev Sperber, Koby Gottlieb
  • Publication number: 20130212363
    Abstract: Technologies related to machine transport and execution of logic simulation. In some examples, logic simulation systems may cyclically calculate logic state vectors based on the current state and inputs into the system. The state vector is a state of a logic storage element in a model. State vectors may be distributed from a core of common memory to one or more arrays of processors to compute the next state vector. The one or more arrays of processors are connected with arrays of logic processors and memory for efficiency and speed.
    Type: Application
    Filed: March 27, 2013
    Publication date: August 15, 2013
    Applicant: GRAYSKYTECH LLC
    Inventor: GRAYSKYTECH LLC
  • Patent number: 8504807
    Abstract: A method of one aspect may include receiving a rotate instruction. The rotate instruction may indicate a source operand and a rotate amount. A result may be stored in a destination operand indicated by the rotate instruction. The result may have the source operand rotated by the rotate amount. Execution of the rotate instruction may complete without reading a carry flag.
    Type: Grant
    Filed: December 26, 2009
    Date of Patent: August 6, 2013
    Assignee: Intel Corporation
    Inventors: Vinodh Gopal, James D. Guilford, Gilbert M. Wolrich, Wajdi K. Feghali, Erdinc Ozturk, Martin G. Dixon, Sean P. Mirkes, Bret L. Toll, Maxim Loktyukhin, Mark C. Davis, Alexandre J. Farcy
  • Patent number: 8494831
    Abstract: A simulator is partitioned into a functional component and a behavior prediction component and the components are executed in parallel. The execution path of the functional component is used to drive the behavior prediction component and the behavior prediction component changes the execution path of the functional component.
    Type: Grant
    Filed: November 19, 2010
    Date of Patent: July 23, 2013
    Inventor: Derek Chiou
  • Publication number: 20130166889
    Abstract: A method and apparatus are described for generating flags in response to processing data during an execution pipeline cycle of a processor. The processor may include a multiplexer configured generate valid bits for received data according to a designated data size, and a logic unit configured to control the generation of flags based on a shift or rotate operation command, the designated data size and information indicating how many bytes and bits to rotate or shift the data by. A carry flag may be used to extend the amount of bits supported by shift and rotate operations. A sign flag may be used to indicate whether a result is a positive or negative number. An overflow flag may be used to indicate that a data overflow exists, whereby there are not a sufficient number of bits to store the data.
    Type: Application
    Filed: December 22, 2011
    Publication date: June 27, 2013
    Applicant: ADVANCED MICRO DEVICES, INC.
    Inventors: Srikanth Arekapudi, Saurabh Gupta
  • Publication number: 20130159683
    Abstract: A particular method includes receiving, at a processor, an instruction and an address of the instruction. The method also includes preventing execution of the instruction based at least in part on determining that the address is within a range of addresses.
    Type: Application
    Filed: December 16, 2011
    Publication date: June 20, 2013
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Mark J. Hickey, Adam J. Muff, Matthew R. Tubbs, Charles D. Wait
  • Patent number: 8464031
    Abstract: During operation, a processor generates a result vector. In particular, the processor records a value from an element at a key element position in an input vector into a base value. Next, for each active element in the result vector to the right of the key element position, the processor generates a result vector by setting the element in the result vector equal to a result of performing a unary operation on the base value a number of times equal to a number of relevant elements. The number of relevant elements is determined from the key element position to and including a predetermined element in the result vector, where the predetermined element in the result vector may be one of: a first element to the left of the element in the result vector; or the element in the result vector.
    Type: Grant
    Filed: April 26, 2012
    Date of Patent: June 11, 2013
    Assignee: Apple Inc.
    Inventor: Jeffry E. Gonion
  • Publication number: 20130138928
    Abstract: A first operation unit 130 outputs, as a first operation result CR1, an output of a first comparison operation unit 122, or an AND or OR of the output and a value already held in a register 50 according to a first control signal ctr1. A second operation unit 140 outputs, as a second operation result CR2, an output of a second comparison operation unit 124, or an AND or OR of the output and a value already held in the register 50 according to a second control signal ctrl. A third operation unit 150 outputs, as an execution result, the first operation result CR1, or an AND or OR of the first operation result CR1 and the second operation result CR2 to the register 50 according to a third control signal ctr3. The register 50 newly holds and outputs the execution result from the third operation unit 150.
    Type: Application
    Filed: November 27, 2012
    Publication date: May 30, 2013
    Applicant: Renesas Electronics Corporation
    Inventor: Renesas Electronics Corporation
  • Publication number: 20130111386
    Abstract: A logical central processing unit (CPU) division management view is displayed for a device having multiple logical CPU divisions. The management view is displayed as a heat map representation that includes multiple cells, each of which corresponds to one of the multiple logical CPU divisions. As part of the heat map representation, each of the multiple cells is displayed in one of multiple different manners based on a usage of the corresponding logical CPU division, and a usage value identifying usage of the corresponding one of the multiple logical processors can also displayed in the cell.
    Type: Application
    Filed: January 6, 2012
    Publication date: May 2, 2013
    Applicant: MICROSOFT CORPORATION
    Inventors: Christina L. Rhodes, Peter Seraphim Ponomarev, Matthew P. Duignan, Phillip Daniel Donate
  • Patent number: 8433883
    Abstract: A computer system is operable to identify index elements in a vector index array that cannot be processed in parallel by calculating a complement modified bit matrix compare function between a first matrix filled with elements from the vector index array and a second matrix filled with the same elements from the vector index array.
    Type: Grant
    Filed: June 11, 2009
    Date of Patent: April 30, 2013
    Assignee: Cray Inc.
    Inventors: Terry D. Greyzck, William F. Long, Peter M. Klausler, Matthew F. Taylor
  • Patent number: 8423748
    Abstract: A register control circuit that controls a register specified by an inputted address includes a signal output that outputs a first control signal and a second control signal based on the inputted address, a selector that selects data of a register specified by the first control signal outputted from the signal output, a logical operator that performs a logical operation of write data outputted from a processor and the data selected by the selector to output an operation result, and a storage that stores data in the register specified by the first control signal by selecting one of the write data and the operation results as the data based on the second control signal outputted from the signal output.
    Type: Grant
    Filed: July 27, 2009
    Date of Patent: April 16, 2013
    Assignee: Fujitsu Limited
    Inventor: Yuusuke Ashizuka
  • Patent number: 8417922
    Abstract: A method and system to combine multiple register units within a microprocessor, such as, for example, a digital signal processor, are described. A first register unit and a second register unit are retrieved from a register file structure within a processing unit, the first register unit and the second register unit being non-adjacently located within the register file structure. The first register unit and the second register unit are further combined during execution of a single instruction to form a resulting register unit. Finally, the resulting register unit is stored within the register file structure for further processing. Alternatively, a first half word unit from the first register unit and a second half word unit from the second register unit are retrieved. The first half word unit and the second half word unit are further input into corresponding high and low portions of a resulting register unit to form the resulting register unit during execution of a single instruction.
    Type: Grant
    Filed: August 2, 2006
    Date of Patent: April 9, 2013
    Assignee: QUALCOMM Incorporated
    Inventors: Lucian Codrescu, Erich Plondke, Mao Zeng