Abstract: Systems and methods presented here allow recreation of prior scenes, even if assets used in the scenes have evolved over time. The systems and methods employ query of a database to obtain data for backup and retrieval, e.g., information about shots made at prior points in time, where a “shot” refers to a scene or associated set of sequential frames (a single image may also be considered a shot in some instances), rendered or not depending on context. In the VP-VCR systems and methods, information may be obtained about rendered scenes which allow knowledge and subsequent use of each asset employed in the scene, including its proper version and representation at the time of the rendering. Such may be employed not only to obtain prior versions of shots, but also to allow modification of assets in prior shots to obtain new effects.

Abstract: A system and method adjust instruction dispatch in a multi-pipeline processor core having a plurality of execution units for improved performance of out-of-order execution of instructions. A dispatch adjust circuit receives a queue full signal from one or more of the execution queues that indicates the corresponding execution queue is full. In response to the queue full signal, the instruction dispatch circuit sends a stop signal to the instruction issuer to stop issuing additional instructions to the queues until one or more of the queues are empty. The dispatch adjust circuit may also receive a queue empty signal from the queues to detect when they are empty to send a start signal to the issuer.

Abstract: Systems, methods, and computer program products to perform an operation comprising receiving, by a database management system (DBMS), a query for execution, computing, by a query governor, a first resource consumption value for executing a first portion of the received query against a plurality of data tuples in an operator graph of a distributed application, and upon determining that the first resource consumption value does not exceed a first threshold value, executing the query by operation of one or more computer processors.

Abstract: A method for performing root cause analysis of failures in a computer network is provided. The method includes receiving an Adaptive Service Intelligence (ASI) data set related to one or more failures reported in the computer network from a plurality of interfaces. One or more impact events associated with the reported failures are identified based on the received ASI data set. Each of the identified impact events is correlated with one or more cause events. A situation record is selectively generated based on the correlation results.

Abstract: A circuitry is provided. The circuitry comprises a signature memory having stored thereon a plurality of stored signatures. Moreover, the circuitry comprises a signature generator configured to receive one or more monitored signals, and to generate a generated signature depending on at least one of the one or more monitored signals. Furthermore, the circuitry comprises one or more subunits configured to be accessed depending on at least one of the one or more monitored signals. Moreover, the circuitry comprises a protection unit configured to restrict access on the one or more subunits. Furthermore, the circuitry comprises a decision controller configured to compare the generated signature with a stored signature of the plurality of stored signatures to obtain a comparison result. The protection unit is configured to provide access to one of the one or more subunits depending on the comparison result.

Abstract: A hardware acceleration block is configured to process via a dedicated pair of registers, a plurality of commands of each of a plurality of threads received from a compute complex. The hardware acceleration block receives successive commands that are separated by at least an amount of time, from a thread of the plurality of threads. The amount of time is adequate to process a command from the thread.

Abstract: A processing device includes a sorting module, which adds to each of a plurality of elements a position value of a corresponding position in a register rest resulting in a plurality of transformed elements in corresponding positions. The plurality of elements include a plurality of bits. The sorting module compares each of the plurality of transformed elements to itself and to one another. The sorting module also assigns one of an enabled or disabled indicator to each of the plurality of the transformed elements based on the comparison. The sorting module further counts a number of the enabled indicators assigned to each of the plurality of the transformed elements to generate a sorted sequence of the plurality of elements.

Abstract: Some embodiments facilitate high performance packet-processing by enabling one or more processors that perform packet-processing to determine whether to enter an idle state or similar state. As network packets usually arrive or are transmitted in batches, the processors of some embodiments determine that more packets may be coming down a multi-stage pipeline upon receiving a first packet for processing. As a result, the processors may stay awake for a duration of time in anticipation of an incoming packet. Some embodiments keep track of the last packet that entered the first stage of the pipeline and compare that with a packet that the processor just processed in a pipeline stage to determine whether there may be more packets coming that need processing. In some embodiments, a processor may also look at a queue length of a queue associated with an upstream stage to determine whether more packets may be coming.

Abstract: Methods and systems for rendering augmented reality aware standard digital content are disclosed. The method includes detecting a context sensitive trigger initiated in response to activation of a trigger condition related to a standard digital content; determining augmented reality content information associated with the context sensitive trigger using augmented reality awareness data; retrieving based on the augmented reality content information, at least one of augmented reality trigger information, augmented reality digital content or mixed content experience configuration; activating at least one reality source based on the context sensitive trigger to capture reality data in response to retrieving; identifying at least one augmented reality trigger in the at least one reality source; and selectively rendering one of the at least one portion of the standard digital content, the augmented reality digital content and the reality data relative to the at least one portion of the standard digital content.

Abstract: Systems, devices and methods for adaptive switching in multicast media streams are disclosed herein. In an embodiment, a method for adaptively transmitting content to one or more users based on currently available bandwidth via internet protocol (“IP”) multicast protocol, includes: receiving a first content stream having a plurality of data packets, the first content stream encoded at a first bit rate; receiving a second content stream having a plurality of data packets, the second content stream encoded at a second bit rate, wherein the first bit rate is different than the second bit rate and wherein the first and second content streams represent the same content; transmitting the first content stream to a user; determining that the user could receive the second content stream based on available bandwidth for transmitting data to the user; and transmitting the second content stream to the user.

Abstract: Disclosed aspects relate to hardware-based memory protection of a container-based virtualization environment. A set of access identifiers for a container of a kernel process related to a memory component may be established. An access request from a first user process to a first portion of the memory component may be received. A first candidate access identifier for the first portion of the memory component may be detected. A first access identifier of the set of access identifiers that corresponds to the first portion of the memory component may be identified. A hardware-based memory protection response operation may be determined. The hardware-based memory protection response operation may be carried-out.

Abstract: Embodiments for leveraging directed acyclic graph (DAG) information to group tasks for execution, by at least one processor device. For a set of tasks, an input host set is determined for each task using a shuffle type and hosts used during a previous stage, and the tasks in the set of tasks determined to be within a same input host set are classified together. An Input/Output (I/O) cost for each task in the set of tasks is calculated and tasks within the set of tasks are grouped into task groups according to an applied allocation time. The task groups are launched commensurate with a calculated delay time from each input host set so as to overlap I/O phases and central processing unit (CPU) phases to improve CPU efficiency, the launched task groups being executed by an executor according to the calculated delay time.

Abstract: Methods, systems, and apparatus, including computer programs encoded on computer storage media, for computing a multivalue reduction using a parallel processing device. One of the methods includes performing a parallel M-value reduction by parallel processing units of a parallel processing device. A plurality of initial reductions are performed in serial, each initial reduction operating on data in a different respective register space of at least M register spaces. Data is moved from the M register spaces so that all results from the plurality of initial reductions are in a same first register space. One or more subsequent reductions are performed in parallel to compute M final values, each subsequent reduction operating only on data in the first register space.

Abstract: A load-store unit having one or more banked queues is disclosed. In one embodiment, a load-store unit includes at least one queue that is subdivided into multiple banks. Although divided into multiple banks, the queue logically appears to software as a single queue. A first bank of the queue includes a first plurality of entries, with the second bank of the queue having a second plurality of entries, wherein each of the entries is arranged to store memory instructions. Each of the banks is associated with corresponding logic circuitry that controls one or more pointers for that bank. The pointer information may be exchanged between the logic circuits associated with the banks. Based on the pointer information that is exchanged, each bank may output (e.g., for retirement) one entry per cycle.

Abstract: Shader resources may be specified for input to a shader using a hierarchical data structure which may be referred to as a descriptor set. The descriptor set may be bound to a bind point of the shader and may contain slots with pointers to memory containing shader resources. The shader may reference a particular slot of the descriptor set using an offset, and may change shader resources by referencing a different slot of the descriptor set or by binding or rebinding a new descriptor set. A graphics pipeline may be specified by creating a pipeline object which specifies a shader and a rendering context object, and linking the pipeline object. Part or all of the pipeline may be validated, cross-validated, or optimized during linking.

Abstract: Dynamic power control embodiments concern a data processing pipeline. First and second pipeline stages respectively receive first and second clock signals. The first and second pipeline stages are configured to perform first and second operations respectively triggered by first timing edges of the first clock signal and second timing edges of the second clock signal. A clock controller is configured to generate the first and second clock signals. The clock controller is capable of operating in a first mode in which, during a first data processing cycle of the data processing pipeline, a first of the first timing edges is in-phase with a first of the second timing edges. The clock controller is also capable of operating in a second mode in which, during a second data processing cycle of the data processing pipeline, a second of the first timing edges is out of phase with a second of the second timing edges.

Abstract: A processor includes a front end, a decoder, an allocator, and a retirement unit. The decoder includes logic to identify an end-of-live-range (EOLR) indicator. The EOLR indicator specifies an architectural register and a location in code for which the architectural register is unused. The allocator includes logic to scan for a mapping of the architectural register to a physical register, based upon the EOLR indicator. The allocator also includes logic to generate a request to disassociate the architectural register from the physical register. The retirement unit includes logic to disassociate the architectural register from the physical register.

Abstract: Various techniques are provided to efficiently implement user designs in programmable logic devices (PLDs). In one example, a method includes identifying a multiplexer in the design, identifying one or more irrelevant inputs for the multiplexer by, at least in part, decomposing the select logic into one or more select line binary decision diagrams corresponding to the one or more select lines, and generating a reduced multiplexer by eliminating the one or more irrelevant inputs from the multiplexer. The reduced multiplexer may be used to generate configuration data to configure physical components of the PLD, and the configuration data may be used to program the PLD to conform to the timing constraints of the design and/or PLD.

Abstract: Embodiments detailed herein include an apparatus that includes a reliability assessment engine (RAE) stored in non-volatile memory and processing circuitry to execute the RAE to: receive data of at least one physical condition from a plurality of intra-die variation monitoring circuits, apply the received data least one to at least one reliability physics model, and calculate at least one of an estimated amount of lifetime consumed and an estimated amount of lifetime remaining.

Abstract: Operation of a multi-slice processor that includes a plurality of execution slices and a load/store superslice, where the load/store superslice includes a set predict array, a first load/store slice, and a second load/store slice. Operation of such a multi-slice processor includes: receiving a two-target load instruction directed to the first load/store slice and a store instruction directed to the second load/store slice; determining a first subset of ports of the set predict array as inputs for an effective address for the two-target load instruction; determining a second subset of ports of the set predict array as inputs for an effective address for the store instruction; and generating, in dependence upon logic corresponding to the set predict array that is less than logic implementing an entire load/store slice, output for performing the two-target load instruction in parallel with generating output for performing the store instruction.

Abstract: Operation of a multi-slice processor that includes a plurality of execution slices and a load/store superslice, where the load/store superslice includes a set predict array, a first load/store slice, and a second load/store slice. Operation of such a multi-slice processor includes: receiving a two-target load instruction directed to the first load/store slice and a store instruction directed to the second load/store slice; determining a first subset of ports of the set predict array as inputs for an effective address for the two-target load instruction; determining a second subset of ports of the set predict array as inputs for an effective address for the store instruction; and generating, in dependence upon logic corresponding to the set predict array that is less than logic implementing an entire load/store slice, output for performing the two-target load instruction in parallel with generating output for performing the store instruction.

Abstract: Embodiments relate to load queue entry reuse for operand store compare (OSC) history table update. An aspect includes allocating a load queue entry in a load queue to a load instruction that is issued into an instruction pipeline, the load queue entry comprising a valid tag that is set and a keep tag that is unset. Another aspect includes based on the flushing of the load instruction, unsetting the valid tag and setting the keep tag. Another aspect includes reissuing the load instruction into the instruction pipeline. Another aspect includes based on determining that the allocated load queue entry corresponds to the reissued load instruction, setting the valid tag and leaving the keep tag set. Another aspect includes based on completing the reissued load instruction, and based on the valid tag and the keep tag being set, updating the OSC history table corresponding to the load instruction.

Abstract: A method is presented for processing one or more instructions to be executed on multiple threads in a Single-Instruction-Multiple-Data (SIMD) computing system. The method includes the steps of analyzing the instructions to collect divergent threads among a plurality of thread groups of the multiple threads; obtaining a redirection array for thread-operand association adjustment among the divergent threads according to the analysis, where the redirection array is used for exchanging a first operand associated with a first divergent thread in a first thread group with a second operand associated with a second divergent thread in a second thread group; and generating compiled code corresponding to the instructions according to the redirection array.

Abstract: Systems and methods are provided for configuring a programmable integrated circuit device. A hard processor region of the programmable integrated circuit device includes a processor that identifies one or more tasks for assigning to an offload region of the programmable integrated circuit. The processor in the hard processor region transmits an instruction to the offload region. The plurality of offload nodes in the offload region are configured to perform the one or more tasks.

Abstract: A method of an aspect includes receiving a packed data rearrangement control indexes generation instruction. The packed data rearrangement control indexes generation instruction indicates a destination storage location. A result is stored in the destination storage location in response to the packed data rearrangement control indexes generation instruction. The result includes a sequence of at least four non-negative integers representing packed data rearrangement control indexes. In an aspect, values of the at least four non-negative integers are not calculated using a result of a preceding instruction. Other methods, apparatus, systems, and instructions are disclosed.

Abstract: A system and method for debugging of live webcasting applications during live events is disclosed. The debugging system permits a user to quickly locate errors in real time during time sensitive webcasting where it is imperative to find and fix errors before the conclusion of the live event.

Abstract: Methods and apparatuses relating to translating a logical thread identification to a physical thread identification. A processor may include a plurality of cores that include a buffer, and a thread mapping hardware unit to: return a physical thread identification in response to a logical thread identification sent to a buffer of a first core when the buffer includes a logical to physical thread mapping for the logical thread identification, and send a request to the buffers of the other cores when the first core's buffer does not include the logical to physical thread mapping for the logical thread identification, wherein each of the other cores are to send an unknown identification response if their buffer does not include the logical thread identification and at least one of the other cores is to send the physical thread identification to the first core if its buffer includes the logical thread identification.

Abstract: The invention relates to a method for handling faults in a central control device, wherein the control device comprises a distributed computer system (100), to which distributed computer system (100) sensors (112, 113, 122, 123) are connected or can be connected, wherein the distributed computer system (100), particularly all the components of the computer system, is distributed to a first fault containment unit FCU1 (101) and a second fault containment unit FCU2 (102), wherein FCU1 (101) and FCU2 (102) are each supplied with power via a separate, independent power supply, and wherein FCU1 (101) and FCU2 (102) interchange data solely via galvanically separated lines, and wherein some of the sensors are connected at least to FCU1 (101) and the remainder of the sensors are connected at least to FCU2 (102), and wherein FCU1 (101) and FCU2 (102) are connected to a redundantly designed communication system (131, 132) having one or more actuators, so that, if FCU1 fails, FCU2 will maintain a limited functionality u

Abstract: Techniques described herein generally relate to a task management system for a chip multiprocessor having multiple processor cores. The task management system tracks the changing instruction set capabilities of each processor core and selects processor cores for use based on the tracked capabilities. In this way, a processor core with one or more failed processing elements can still be used effectively, since the processor core may be selected to process instruction sets that do not use the failed processing elements.

Abstract: In one embodiment of the present invention, a streaming multiprocessor (SM) uses a tree of nodes to manage threads. Each node specifies a set of active threads and a program counter. Upon encountering a conditional instruction that causes an execution path to diverge, the SM creates child nodes corresponding to each of the divergent execution paths. Based on the conditional instruction, the SM assigns each active thread included in the parent node to at most one child node, and the SM temporarily discontinues executing instructions specified by the parent node. Instead, the SM concurrently executes instructions specified by the child nodes. After all the divergent paths reconverge to the parent path, the SM resumes executing instructions specified by the parent node. Advantageously, the disclosed techniques enable the SM to execute divergent paths in parallel, thereby reducing undesirable program behavior associated with conventional techniques that serialize divergent paths across thread groups.

Abstract: A compiling apparatus generates a dependency tree representing dependency relations among a plurality of instructions included in first code. The compiling apparatus detects, from the dependency tree, a partial tree including a first instruction, a second instruction, and a third instruction that depends on the operation results of the first and second instructions, and rewrites the instructions corresponding to the partial tree to a set of instructions including a plurality of complex instructions each of which causes a processor to perform a complex operation including a plurality of operations. The compiling apparatus generates second code on the basis of the dependency tree and the set of instructions.

Abstract: A system and method for scheduling data transfers between systems. One or more data requesting systems may request access to particular data. The request for access to the particular data may correspond to a request that a task to be performed. The task may be to exchange the particular data between a data accessing system having access to the particular data and a data requesting system requesting access to the particular data. The communication exchange may be scheduled for processing. In some embodiments, the communication exchange may be initiated based on a parameter included in the request that the task be performed.

Abstract: A coherent computer system includes a memory shared by a processor and a coherent accelerator device (CAD). The memory includes a work queue directly accessible by the accelerator functional unit (AFU) within the CAD and by the processor utilizing the same effective addresses. The coherent computer system provides accelerator functionality when the accelerator is unavailable by implementing a virtual AFU to carryout accelerator function while the AFU is unavailable. The virtual AFU is a functional logical equivalent of the AFU and is coherent with the processor. When the AFU becomes available, the virtual AFU is disabled and the accelerator is enabled to allow the accelerator to carryout accelerator functionality.

Abstract: An apparatus and method relate generally to generation and checking of a quaternary pseudo random binary sequence (“QPRBS”). In an apparatus, there is a pseudo random binary sequence (“PRBS”) generator configured to receive a seed of a PRBS to be generated. A mask generator is configured to generate a mask output corresponding to the PRBS. The PRBS generator and the mask generator are both configured for sequential operation with respect to one another. A masking circuit is configured to receive the mask output and the PRBS to bitwise mask the PRBS with the mask output to generate the QPRBS.

Abstract: A method for implementing an action-based to-do list includes monitoring user actions with a personal management device which is configured to compare the user actions to a task definition file. A processor of the personal management device determines if the user actions fulfill one or more predefined conditions, within the task definition file. If a condition is fulfilled, the processor of the personal management device modifies the to-do list based on the fulfilled condition. A personal management device for implementing an action-based to-do list includes a user interface configured to allow a user to interact with a to-do list application and a processor configured to execute the to-do list application.

Abstract: A method and apparatus for optimizing parallelized single threaded programs is herein described. Code regions, such as dependency chains, are replicated utilizing any known method, such as dynamic code replication. A flow network associated with a replicated code region is built and a minimum cut algorithm is applied to determine duplicated nodes, which may include a single instruction or a group of instructions, to be removed. The dependency of removed nodes is fulfilled with inserted communication to ensure proper data consistency of the original single-threaded program. As a result, both performance and power consumption is optimized for parallel code sections through removal of expensive workload nodes and replacement with communication between other replicated code regions to be executed in parallel.

Abstract: The embodiments relate to a method for managing a garbage collection process. The method includes executing a garbage collection process on a memory block of user address space. A load instruction is run. Running the load instruction includes loading content of a storage location into a processor. The loaded content corresponds to a memory address. It is determined if the garbage collection process is being executed at the memory address. The load instruction is diverted to a process to move an object at the memory address to a location outside of the memory block in response to determining that the garbage collection process is being executed at the first memory address. The load instruction is continued in response to determining that the garbage collection process is not being executed at the memory address.

Abstract: A method, system, and computer program product synchronize a group of workitems executing an instruction stream on a processor. The processor is yielded by a first workitem responsive to a synchronization instruction in the instruction stream. A first one of a plurality of program counters is updated to point to a next instruction following the synchronization instruction in the instruction stream to be executed by the first workitem. A second workitem is run on the processor after the yielding.

Abstract: A configurable processing circuit capable of handling multiple threads simultaneously, the circuit comprising a thread data store, a plurality of configurable execution units, a configurable routing network for connecting locations in the thread data store to the execution units, a configuration data store for storing configuration instances that each define a configuration of the routing network and a configuration of one or more of the plurality of execution units, and a pipeline formed from the execution units, the routing network and the thread data store that comprises a plurality of pipeline sections configured such that each thread propagates from one pipeline section to the next at each clock cycle, the circuit being configured to: (i) associate each thread with a configuration instance; and (ii) configure each of the plurality of pipeline sections for each clock cycle to be in accordance with the configuration instance associated with the respective thread that will propagate through that pipeline se

Abstract: Embodiments relate to load queue entry reuse for operand store compare (OSC) history table update. An aspect includes allocating a load queue entry in a load queue to a load instruction that is issued into an instruction pipeline, the load queue entry comprising a valid tag that is set and a keep tag that is unset. Another aspect includes based on the flushing of the load instruction, unsetting the valid tag and setting the keep tag. Another aspect includes reissuing the load instruction into the instruction pipeline. Another aspect includes based on determining that the allocated load queue entry corresponds to the reissued load instruction, setting the valid tag and leaving the keep tag set. Another aspect includes based on completing the reissued load instruction, and based on the valid tag and the keep tag being set, updating the OSC history table corresponding to the load instruction.

Abstract: Systems and methods that allow for dynamic quality of service (QoS) levels for an application processor in a multi-core on-chip system (SoC) in a portable computing device (PCD) are presented. During operation of the PCD an operational load of a co-processor of the SoC is determined, where the co-processor is in communication with an application processor of the SoC. Based on the determined load, the co-processor determines a QoS level required from the application processor. The QoS level is communicated to the application processor. The application processor determines whether it can implement power optimization measures, such as entering into a low power mode (LPM), based at least in part on the dynamically communicated QoS level from the co-processor. The present disclosure provides a cost effective ability to reduce power consumption in PCDs implementing one or more cores or CPUs that are dependent upon the application processor.

Abstract: A processor of an aspect includes a plurality of packed data registers, and a decode unit to decode a no-locality hint vector memory access instruction. The no-locality hint vector memory access instruction to indicate a packed data register of the plurality of packed data registers that is to have a source packed memory indices. The source packed memory indices to have a plurality of memory indices. The no-locality hint vector memory access instruction is to provide a no-locality hint to the processor for data elements that are to be accessed with the memory indices. The processor also includes an execution unit coupled with the decode unit and the plurality of packed data registers. The execution unit, in response to the no-locality hint vector memory access instruction, is to access the data elements at memory locations that are based on the memory indices.

Abstract: A method for performing dynamic port remapping during instruction scheduling in an out of order microprocessor is disclosed. The method comprises selecting and dispatching a plurality of instructions from a plurality of select ports in a scheduler module in first clock cycle. Next, it comprises determining if a first physical register file unit has capacity to support instructions dispatched in the first clock cycle. Further, it comprises supplying a response back to logic circuitry between the plurality of select ports and a plurality of execution ports, wherein the logic circuitry is operable to re-map select ports in the scheduler module to execution ports based on the response. Finally, responsive to a determination that the first physical register file unit is full, the method comprises re-mapping at least one select port connecting with an execution unit in the first physical register file unit to a second physical register file unit.

Abstract: The disclosure is related to systems and methods of using a data storage device's processing power to perform mathematical operations on data within a data storage device. The mathematical operation may be done independently of a host system and the data storage device may provide a calculated result to the host system instead of providing stored data. In a particular embodiment, the data storage device may perform a convolution operation on data received from a host, compare the result of the convolution operation to data comprising a set of potential matches previously stored on the data storage device, and select at least one of the set of potential matches to provide as a result to the host.

Abstract: According to one embodiment of the invention, a method for secured execution of commands is described. Initially, a second electronic device authenticates a first electronic device and registers the first electronic device as a trusted device. Thereafter, up receipt of a message with one or more embedded commands, such commands are executed without any pre-established communication protocol if the message is from the registered first electronic device.

Abstract: A streams manager monitors performance of a streaming application, and when the performance needs to be improved, the streams manager determines from split rules how to split the flow graph for the streaming application. The streams manager requests virtual machines from a cloud manager. In response, the cloud manager provisions one or more virtual machines in a cloud. The streams manager then modifies the flow graph so a portion of the flow graph is deployed to the one or more virtual machines in the cloud. In this manner a streaming application can dynamically evolve to increase its performance as needed.

Abstract: The present invention discloses a task processing apparatus and a method, and belongs to the field of radio communications technologies. The method includes: obtaining, by a task processing apparatus, one or more configured tasks, and selecting a task to be scheduled from the one or more tasks; and processing the task to be scheduled according to control parameters of the task to be scheduled to obtain a processing result, outputting the processing result of the task to be scheduled, and, according to the control parameters of the task to be scheduled, scheduling a next-level task processing apparatus to process the task to be scheduled. In the present invention, the task processing apparatus selects the task to be scheduled from the one or more configured tasks, and then processes the task to be scheduled in real time according to the control parameters of the task to be scheduled.

Abstract: A computer manages entries into a clustered index. The computer handles one or more commands, wherein each command loads a dataset into a database. The computer queries a database system catalog of the database for a target index, wherein the database system catalog contains a list of indices of the dataset in the form of metadata. The computer disables a parallel loading process for the dataset. The computer loads the dataset into the target index, wherein the dataset is sorted according to the target index.

Abstract: Embodiments relate to load queue entry reuse for operand store compare (OSC) history table update. An aspect includes allocating a load queue entry in a load queue to a load instruction that is issued into an instruction pipeline, the load queue entry comprising a valid tag that is set and a keep tag that is unset. Another aspect includes based on the flushing of the load instruction, unsetting the valid tag and setting the keep tag. Another aspect includes reissuing the load instruction into the instruction pipeline. Another aspect includes based on determining that the allocated load queue entry corresponds to the reissued load instruction, setting the valid tag and leaving the keep tag set. Another aspect includes based on completing the reissued load instruction, and based on the valid tag and the keep tag being set, updating the OSC history table corresponding to the load instruction.

Abstract: An apparatus is described that contains a processing core comprising a CPU core and at least one accelerator coupled to the CPU core. The CPU core comprises a pipeline having a translation look aside buffer. The CPU core comprising logic circuitry to set a lock bit in attribute data of an entry within the translation look-aside buffer entry to lock a page of memory reserved for the accelerator.