Abstract: A reduced programmable controller for an extensible digital signal processing architecture supports particular instructions to facilitate common digital signal processing operations. These instructions include extract and insert instructions, which are useful in managing the storage and extraction of digital signal processing variables to and from registers, and also useful in assembling fixed-length digital signal parameters from a section of a bitstream stored in a register. These instructions further include leading value detect instructions, including a leading zero detect instruction and a leading one detect instruction which are useful in parsing unique prefix codes such as Huffman codes used in MPEG encoding of video and other variable length codes, and useful in handling of a priority encoder such as a task manager.

Abstract: A multimedia extension unit (MEU) is provided for performing various multimedia-type operations. The MEU can be coupled either through a coprocessor bus or a local CPU bus to a conventional processor. The MEU employs vector registers, a vector ALU, and an operand routing unit (ORU) to perform a maximum number of the multimedia operations within as few instruction cycles as possible. Complex algorithms are readily performed by arranging operands upon the vector ALU in accordance with the desired algorithm flowgraph. The ORU aligns the operands within partitioned slots or sub-slots of the vector registers using vector instructions unique to the MEU. At the output of the ORU, operand pairs from vector source or destination registers can be easily routed and combined at the vector ALU. The vector instructions employ special load/store instructions in combination with numerous operational instructions to carry out concurrent multimedia operations on the aligned operands.

Abstract: An apparatus and method of synchronizing instruction execution in the apparatus with external events. The apparatus may be a processor or microprocessor capable of executing a function specific wait state that is dependant upon a type specified by an instruction field. The processor includes an event counter that maintains an event occurrence count, an instruction parser that strips the instruction type and event count from instructions and passes the stripped information to a comparator. The comparator compares the stripped information against an event count. The instruction types include: a relative type indicating execution at some event occurrence subsequent to the present cycle; a direct type indicating an absolute event occurrence count for execution; and a event range indicating a range of event occurrences wherein execution is valid.

Abstract: Improvements are made in how microprocessors execute logical exclusive OR instructions when the operands of this instruction are equal. XOR instructions with equal operands are used to clear registers and/or assign flags values without explicitly performing the actual XOR command. By setting or resetting these flags and/or clearing these registers directly, this mechanism allows these instructions to be paired with following dependent instructions simply by zeroing the dependent input of the following instructions. An architecture that hardwires the implementation into the microprocessor through logic gates is preferred. This will result in increased speed while reducing power consumption. Further, a full-sized ALU is not needed in order to execute the XOR instruction with equal operands. As this is a more direct procedure, a pipeline with a reduced capability ALU can be utilized.

Abstract: When an atomic instruction executed by a computer processor locks a memory location, the locking is performed before the processor has determined whether the instruction is to be executed to completion or canceled. The memory location is unlocked whether or not the instruction will be canceled. Since the locking operation can occur before it is known whether the instruction will be canceled, the reading of the memory location can also occur early, before it is known whether the instruction will be canceled.

Abstract: The data processor for executing, instructions realized by wired logic, by a pipeline system, includes a plurality of instruction registers, and arithmetic operation units of the same number. A plurality of instructions read in the instruction registers in one machine cycle at a time are processed in parallel by the plurality of arithmetic operation units.

Abstract: Methods and systems for bit manipulation instructions are disclosed. The instruction srlmsk shifts a value stored in a first register based on a shift value stored in a second register and loads N bits from the shift register to a third register using a single instruction. The instruction concat loads the lower N bits from a first register into the high order bits of a second register and loads a subset of least significant bits of a third register to the low order bits of the second register using a single instruction. These instructions may be used to improve variable length encoding and decoding processes.

Abstract: A method and apparatus for performing a divide operation in a computer are described. The apparatus includes a first memory containing estimated reciprocal terms, and a second memory containing reciprocal error terms. An adder adds a selected estimated reciprocal term from the first memory and a selected reciprocal error term from the second memory to provide the reciprocal. The selected estimated reciprocal term and the selected reciprocal error term correspond to at least a portion of a divisor. The apparatus includes a multiplier for multiplying a dividend by the reciprocal to generate a quotient. The method includes the step of looking up an estimated reciprocal term in a first lookup table stored in a first computer memory wherein the estimated reciprocal term corresponds to at least a portion of a given divisor. A reciprocal error term is looked up in a second lookup table stored in a second computer memory, the error term corresponds to at least a portion of the divisor.

Abstract: A processor includes execution resources and condition code logic. The execution resources execute an arithmetic or logical instruction by arithmetically or logically combining at least two operands. Concurrent with the execution of the arithmetic or logical instruction by the execution resources, the condition code logic determines less than, greater than, and equal to condition code bits associated with the result of the arithmetic or logical instruction. In one embodiment, the condition code logic includes a single computation stage that receives as inputs individual bit values of bit positions within first and second operands and logically combines the individual bit values. The single computation stage outputs, for each bit position, propagate, generate, and kill signals that collectively indicate values for the less than, greater than, and equal to condition code bits.

Abstract: A processing architecture includes a first CPU core portion coupled to a second embedded dynamic random access memory (DRAM) portion. These architectural components jointly implement a single processor and instruction set. Advantageously, the embedded logic on the DRAM chip implements the memory intensive processing tasks, thus reducing the amount of traffic that needs to be bussed back and forth between the CPU core and the embedded DRAM chips. The embedded DRAM logic monitors and manipulates the instruction stream into the CPU core. The architecture of the instruction set, data paths, addressing, control, caching, and interfaces are developed to allow the system to operate using a standard programming model. Specialized video and graphics processing systems are developed. Also, an extended very long instruction word (VLIW) architecture implemented as a primary VLIW processor coupled to an embedded DRAM VLIW extension processor efficiently deals with memory intensive tasks.

Abstract: A circuit for controlling execution of a loop in a digital signal processing chip. The circuit includes a least significant bit state detection unit to output an effective signal of a predetermined level according to the state of a least significant bit and the states of first and second signals, when every bit other than the least significant bit is zero as a result of detection of the state of each bit in a counter register to which the number of loop executions is loaded; a conditional clock output unit to receive a clock signal and the first and second signals and output the clock signal only when the first or second signal is effective; and an ending condition signal output unit to output the output signal of the least significant bit state detection unit when a signal output from the conditional clock output unit is effective.

Abstract: One aspect of the invention relates to an apparatus for processing a store instruction on a superscalar processor that employs in-order completion of instructions, the processor having an instruction dispatch unit, an architected register file, a rename register file, a load store unit, a completion unit and cache memory. In one embodiment of the invention, the apparatus includes a pointer queue having an entry corresponding to the store instruction, the entry containing a pointer to the entries in the architected and rename register files that contain data required by the store instruction; and a multiplexer coupled to read ports on the architected and rename register files so that data can be passed from one of the register files into an entry in a data queue, the data queue being coupled to the cache memory.

Abstract: A circuit for processing source code with associated array bounds limitations includes an execution unit that generates a register value signal and an index number signal corresponding to an array value defined in a source code instruction. A primary register is connected to the execution unit. The primary register produces a base memory address signal in response to the register value signal. A shadow register is also connected to the execution unit. The shadow register produces an array bound value signal in response to the register value signal. An address computation circuit is connected to the execution unit and the primary register. The address computation circuit generates an effective memory address signal based upon the base memory address signal and the index number signal. An address comparison circuit generates an array bound error signal when an effective memory address associated with the effective memory address signal exceeds an array bound value associated with the array bound value signal.

Abstract: An application accelerator (AA) unit that in one embodiment is part of an I/O processor (IOP) integrated circuit. The AAU includes logic circuitry for improving the performance of storage applications such as Redundant Array of Inexpensive Disks (RAID). A boolean unit performs operations such as exclusive-or (XOR) on multiple blocks of data to form the image parity block which is written to the redundant disk array. The AAU is associated with a memory-mapped programming interface that allows software executed by a core processor in the IOP to utilize the AAU for accelerating RAID storage applications as well as local memory DMA-type transfers, using the descriptor construct.

Abstract: A method, system and data structures for software development and execution includes a Run Time Event Manager and a set of Models. A Model is a type of data structure that contains no code but an ordered set of references to other Models, to Methods, or other Objects. Models are made accessible to the Run Time Event Manager by registering them upon satisfaction of a set of conditions. In one embodiment of the invention, the Run Time Events Manager is a fetch-execute loop implemented in code that, upon each loop, operates upon one of a set of Models, checks external I/O conditions and, subject to such conditions, may process different or Variant Models, rather than standard or Paradigm Models associated with default conditions. Also, an Elastic Database may be implemented according to the invention that permits dynamically extensible database functionality.

Abstract: A microprocessor capable of unpacking packed data in response to an unpack instruction. The microprocessor having a a storage area to store a first packed data and a second packed data respectively including a first plurality of data elements and a second plurality of data elements, wherein each data element in the first plurality of data elements corresponds to a different data element in the second plurality of data elements, in a respective position. The microprocessor also includes a circuit that simultaneously copies less than all data elements from the first plurality of data elements and corresponding data elements from the second plurality of data elements into a storage area as a third plurality of separate data elements in a third packed data in response to the unpack instruction.

Abstract: A microprocessor 1 has an instruction fetch/decode unit 10a-c, a plurality of execution units, including an arithmetic and load/store unit D1, a multiplier M1, an ALU/shifter unit S1, an arithmetic logic unit ("ALU") L1, a shared multiport register file 20a from which data are read and to which data are written, and a memory 22. The microprocessor can execute an instruction which shifts a source operand a specified number of bits and saturates the result if a numerical overflow would result from the shift. Execution unit S1 has circuitry for saturating a destination operand by setting all bits within the destination to represent a most positive or a most negative number in a same single instruction execution phase in which the shift would have occurred if not for the overflow. The saturation circuitry examines the source operand prior to shifting to determine if the destination should be saturated.

Abstract: An arrangement for shifting packed data is provided, in which packed data have multiple partial data each having n-byte, n being an integer greater or equal 1. The arrangement comprises: a shifter for shifting the packed data by a predetermined number of bits, a mask generator for generating a mask having multiple n-byte masks concatenated to the size of the packed data, and a logical unit for logically combining said mask with said shifted packed data to generate individually shifted partial data.

Abstract: A computer processor that allows the execution of the IBM ESA/390 STOSM and STNSM instructions, in an overlapped fashion, contains an apparatus that allows the STOSM and STNSM instructions to be executed without serializing the processor, or otherwise delaying subsequent instructions, after the STOSM or STNSM instruction, in most cases, thereby improving performance. It contains a mechanism that counts cycles after their execution and prohibits asynchronous interrupts during that time. The invention also contains an efficient mechanism for handling the execution of the STOSM and STNSM instructions when the processor is executing in the SIE environment.

Abstract: A three port FIFO buffer circuit uses off the shelf static RAM and dedicated shallow, e.g. 16 word, FIFOs in a multi-level caching scheme. The circuit results in multiple, reconfigurable, deep (e.g. up to 32k word) FIFO buffers. The preferred embodiment of the invention provides a buffer that comprises a bank of 32k word RAM, six dual port 16-word FIFOs, and associated sequencing logic. The sequencing logic includes RAM address registers/counter associated with each of the six FIFOs, and manages the movement of data into and out of the RAM.

Abstract: A computer processor that allows the execution of the IBM ESA/390 SPKA instruction, in an overlapped fashion, contains an apparatus that allows the SPKA instruction to be executed without serializing the processor after its execution in most cases, thereby improving performance. It contains a mechanism in the processor's cache that monitors if the Fetch Protect bit in the storage key is on, for instruction data being fetched. It also contains a mechanism to remember if an SPKA instruction has been executed recently. Based on this information, an apparatus determines if it really must serialize the processor after execution of the SPKA instruction.

Abstract: A method for scheduling a flag generating instruction and a subsequent instruction. The subsequent instruction has a data dependency on the flag generating instruction. The flag generating instruction is translated into first and second instructions. The subsequent instruction is translated into at least a third instruction. The first instruction, when executed, generates a result and intermediate flag generation data. The second instruction, when executed, generates a plurality of flags. The first instruction is scheduled to execute before the second and third instructions. The second instruction is scheduled to execute before the third instruction if the third instruction has a data dependency on the second instruction, otherwise the third instruction may be scheduled to execute before the second instruction.

Abstract: A state machine controller which can be used for fetching data for a real-time computer image generation system and which provides valid data for each clock interval of a system control clock. The state machine controller can produce a result per clock pulse, schedule new data to be processed before completion of the processing of previous data to prevent bubbles or interruptions in the data pipeline, and can stop and maintain its output if a hold is applied from a later pipeline stage, and can resume one clock operation on the clock pulse when the hold is removed.

Abstract: An execution unit is provided for executing a first instruction which includes an opcode field, a first operand field, and a second operand field. The execution unit includes a first input register for receiving a first operand specified by a value of the first operand field, and a second input register for receiving a second operand specified by a value of the second operand field. The execution unit further includes a comparator unit which is coupled to receive a value of the opcode field for the first instruction. The comparator unit is also coupled to receive the first and second operand values from the first and second input registers, respectively. The execution further includes a multiplexer which receives a plurality of inputs. These inputs include a first constant value, a second constant value, and the values of the first and second operand.

Abstract: According to a presently preferred embodiment of the present invention, a method for processing a incoming signal comprising the steps of selecting from a first signal a first plurality of bits of signal information to be processed, selecting from a second signal a second plurality of bits of signal information to be processed, reading the first plurality of bits of signal information into contiguous memory space so as to form a first word, reading the second plurality of bits of signal information into contiguous memory space so as to form a second word, causing a first logical AND operation to be performed on the second word with a mask, causing a first logical OR operation between the first word and the complement of the mask, causing a first EXCLUSIVE OR operation between the first word and the complement of the second word, causing a second logical AND operation between the results of the first EXCLUSIVE OR operation and the complement of the mask, subtracting the results of the first logical AND operati

Abstract: A packet control list (456) controls the transfer of data packets between at least one source location (452) and at least one destination location (460) each associated with a data packet transfer device (20). Packet control list (456) associates a plurality of data packet transfer control instructions (454) in a sequential list (466) including a plurality of logical functions (472) for controlling logical operations relating to the transfer of data packets from at least one source location (452) to at least one destination location (460). Instructions (486) control the operation of data packet transfer device (20) according to instructions (486).

Abstract: A microprocessor circuit is disclosed for instructions on an arithmetic/shift function performing standard operations (e.g., ALU instructions or Shift instructions) on instructions in a first cycle of operation, and a correction circuit responsive to the arithmetic/shift function for modifying the standard results provided by the arithmetic/shift function to results required by a SIMD instruction being executed. The arithmetic/shift function is an instruction provided by either an Arithmetic Logic Unit (ALU) or by a shift instruction. The correction circuit passes data, unchanged for logical instructions but provides condition codes according to the SIMD instruction.

Abstract: An instruction (also called a "bit reversal instruction") for reversing the order of bits in an input signal is implemented by reusing one or more components in a datapath normally found in a processor. Specifically, a bit reversal instruction is implemented by reuse of a shifter unit normally used in a datapath to shift bits of an input signal. The shifter unit includes three stages: a first stage formed by a number of input multiplexers, a second stage formed by, for example, a left shifter, and a third stage formed by a number of output multiplexers. When using a left shifter to implement the bit reversal instruction, the input multiplexers are not used. Instead, the left shifter is used to shift bits of the input signal left by a number that is inverse of the number of bits to be reversed. Thereafter, the output multiplexers reverse the order of bits generated by the left shifter, thereby completing the bit reversal instruction.

Abstract: A conventional bi-endian computer system is enhanced to include mixed-endian mechanisms that allows the computer system to dynamically change its endian mode. The mixed-endian computer system can change endian mode on a task by task basis if necessary. The mixed-endian mechanisms automatically format the data in the form expected by the running task, regardless of whether the task expects the data to be in big endian format or in little endian format. The mixed-endian mechanisms also format big and little endian instructions such that they can execute on the same computer system.

Abstract: Circuit for performing arithmetic operations in a 32-bit architecture. The circuit includes a five stage shift and rotate circuit coupled between first and second 32-bit busses in the following sequence: an 8-bit shift and rotate circuit, a 16-bit shift and rotate circuit, a 1-bit shift and rotate circuit, a 2-bit shift and rotate circuit and a 4-bit shift and rotate circuit. For double word sized (32-bit) operands, the variously sized shift and rotate circuits may be selectively enabled to perform between 1-bit and 31-bit shift/rotate/pass operations. For byte sized operands, the 8-bit and 16-bit shift and rotate circuits are used to pre-process the operands while the 1-bit, 2-bit and 4-bit shift and rotate circuits are selectively enabled to perform the full range, i.e., 1-bit to 7-bit, of possible shift/rotate operations.

Abstract: A processor having a modified Harvard architecture having first and second memories, an address register file divided into first and second sets of registers, first and second stream registers, and a general purpose register file for performing data streaming. The first and second sets of registers respectively address the first and second memories which, in turn, load data into the first and second stream registers. An arithmetic logic unit (ALU) accepts the stream registers and general purpose registers as inputs. Stream instructions are encoded such that a single instruction specifies an ALU operation performed on selected ALU inputs and where to store the results of the ALU operation, loads new values into the stream registers, and updates the address registers. A stream instruction has three operand fields respectively specifying two operands for the next ALU operation and a location to store the result of the current ALU operation.

Abstract: A CPU (central processing unit) of a computer that comprises an issue unit and an execution unit. The issue unit selectively issues arithmetic instructions of a predefined arithmetic instruction type as performance critical arithmetic instructions and non-performance critical arithmetic instructions. The execution unit comprises a performance critical pipeline to execute the performance critical arithmetic instructions. The execution unit also comprises a non-performance critical pipeline to execute the non-performance critical arithmetic instructions.