Abstract: A first transmitting unit transmits a processing command to a plurality of parallelized database servers. A second transmitting unit integrates data sets transmitted from the database servers in response to the processing command, and transmits an integrated data set to a client. An integrating unit integrates data sets buffered in a buffer unit. A determining unit determines a transmission start or a transmission suspend of the data sets based on a data size in the buffer unit. A third transmitting unit transmits a control command for the transmission start or the transmission suspend to the database servers based on a result of determination by the first determining unit.

Abstract: A programmable processor and method for improving the performance of processors by expanding at least two source operands, or a source and a result operand, to a width greater than the width of either the general purpose register or the data path width. The present invention provides operands which are substantially larger than the data path width of the processor by using the contents of a general purpose register to specify a memory address at which a plurality of data path widths of data can be read or written, as well as the size and shape of the operand. In addition, several instructions and apparatus for implementing these instructions are described which obtain performance advantages if the operands are not limited to the width and accessible number of general purpose registers.

Abstract: A computer implemented method converts a data set of a first type to a data set type of a second type. The method includes casting up a first data set of a first type to a prescribed data set type that is large enough to encompass a data set of a second type. The method then includes casting down the casted up first data set from the prescribed data set type to the second data set of the second data set type.

Abstract: A method for adaptive runtime reconfiguration of a co-processor instruction set, in a computer system with at least a main processor communicatively connected to at least one reconfigurable co-processor, includes the steps of configuring the co-processor to implement an instruction set comprising one or more co-processor instructions, issuing a co-processor instruction to the co-processor, and determining whether the instruction is implemented in the co-processor. For an instruction not implemented in the co-processor instruction set, raising a stall signal to delay the main processor, determining whether there is enough space in the co-processor for the non-implemented instruction, and if there is enough space for said instruction, reconfiguring the instruction set of the co-processor by adding the non-implemented instruction to the co-processor instruction set. The stall signal is cleared and the instruction is executed.

Abstract: The present invention includes a method and device for controlling the data length of read and write operations performed on a memory device. The method includes determining a first number of channels available to a memory controller operatively coupled to the memory device; determining a second number representative of the number of populated channels; calculating a burst length based on the first and second numbers; and programming the memory controller to use the burst length as the data length of read and write operations performed on the memory device.

Abstract: An event occurring in a graphics pipeline is detected and counted at the location of its occurrence using an event detector and a local counter. The event count maintained by the local counter is reported asynchronously to a global counter. The global counter is configured to be of higher precision than the local counter and is positioned at a place that is convenient for reporting the events, e.g., at the end of the graphics pipeline.

Abstract: An apparatus and method for efficiently managing store buffer operations is described in connection with a multithreaded multiprocessor chip. A CMT processor keeps track of stores by maintaining two store counters in the instruction fetch unit (IFU). A speculative store counter in the IFU tracks stores in flight to the store buffer as well as stores already in the store buffer. A committed store counter in the IFU tracks the number of stores actually in the store buffer. The store buffer provides allocate and deallocate signals to accurately maintain the committed store counter. The IFU stops issuing stores to the store buffer once the speculative counter has reached a threshold value. Upon a flush, the IFU sets the speculative counter equal to the committed store counter. In this way, an efficient feedback mechanism is provided for preventing store buffer overflow that minimizes the store buffer size, operations time and power usage.

Abstract: A load detecting apparatus includes a load controller, and judges a motion of a player on the basis of detected load values. Judgment timing for a motion of putting the feet on and down from the controller is decided on the basis of an elapsed time from an instruction of a motion. In a case that a step-up-and-down exercise is performed, a judgment timing of a motion for bringing about a state both of the feet are put down on a ground at a fourth step is decided on the basis of a judgment timing of a motion of putting a third step down.

Abstract: The present invention broadly contemplates braids and fibers, high-level programming constructs which facilitate the creation of programs that are partially ordered, to address the continuing trend of ever-increasing processor speeds and attendant increases in memory latencies. These partial orders can be used to respond adaptively to memory latencies. It is shown how these constructs can be effectively supported with simple and inexpensive instruction set and micro-architectural extensions.

Abstract: A method and apparatus for conditional memory ordering are disclosed. The cost of memory ordering is reduced by determining circumstances in which a memory ordering operation is unnecessary and avoiding the overheads of these operations by reducing the frequency of invoking hardware memory ordering mechanisms. Hardware instructions for implementing a conditional memory ordering method and apparatus is described which may be implemented in a multiprocessor environment. The conditional memory ordering instruction executes locally using a release vector containing release numbers for each processor in the system. The instruction first determines whether a processor identifier of the release number is associated with the current processor. Where it is not, a conditional register is examined and appropriate remote synchronization operations are commanded where necessary.

Abstract: A method for reducing the number of times in-flight loads must be searched by store instructions in a multi-threaded processor. A load issue for a thread t_old is frozen for a number of cycles. A t13 new load instruction is rejected. A notification is sent to the rest of the processor that the t_new load instruction has been rejected. A load reorder queue (LRQ) of a t_old is snooped for any load which comes from a cache line L accessed by the load instruction and then forces such loads to be re-executed. Ownership of line L is changed to thread t_new.

Abstract: Systems and methods that vary multiple data sampling rates, to collect sets of data with different levels of granularity for an industrial system. The data for such industrial system includes sets of data from the “internal” data stream(s) (e.g., history data collected from an industrial unit) and sets of data from an “external” (e.g., traffic data on network services) data stream(s), based in part on the criticality/importance criteria assigned to each collection stage. Each set of data can be assigned its own unique data collection rate. For example, a higher sample rate can be employed when collecting data from the network during an operation stage that is deemed more critical (e.g., dynamic attribution of predetermined importance factors) than the rest of the operation.

Abstract: A method of managing data movement in a cell broadband engine processor, comprising: determining one or more idle synergistic processing elements among multiple SPEs in the cell broadband engine processor as a managing SPE, and informing a computing SPE among said multiple SPEs of a starting effective address of a LS of said managing SPE and an effective address for a command queue; and said managing SPE managing movement of data associated with computing of said computing SPE based on the command queue from the computing SPE.

Abstract: An apparatus and method for efficiently managing data cache load misses is described in connection with a multithreaded, pipelined multiprocessor chip. A CMT processor keeps track of load misses for each thread by issuing a load miss signal each time a load instruction to the data cache misses. A detection logic functionality in the IFU responds the load miss signal to determine if a valid instruction from the thread is at the one of the pipeline stages. If no instructions from the thread are detected in the pipeline, then no flush is required and the thread is placed in a wait state until the requested data is returned from higher order memory. If any instruction from the thread is detected in the pipeline, the thread is flushed and the instruction is re-fetched.

Abstract: A processor chip that provides a dynamically selectable operating mode in which particular sequences of instructions are executed without an external interrupt. The processor chip comprises an architected bit that may be set by software and which enables the external interrupt of the processing system to be dynamically enabled/disabled. When a sequence of instructions constituting a data move operation is being issued, the architected bit is toggled to an interrupt disabled state so that execution of the sequence of instructions occurs without an external interrupt. Following the execution of the sequence of instructions, the architected bit is toggled to an interrupt enabled state, which causes instruction execution to be subjected to external interrupts.

Abstract: Systems and methods implemented in a PC for enabling communication between an application executing on the CPU and a DSP that is incorporated into a codec in the High Definition Audio (HDA) system, wherein the communication is carried out via the HDA bus. In one embodiment, an HDA codec includes one or more conventional HDA widgets coupled to a programmable processor such as a DSP. The codec includes a set of registers that are configured to store HDA verbs and data transmitted via the HDA bus. The programmable processor is configured to identify verbs that indicate associated information is a communication from an application executing on the CPU, read the associated information, and process the information according to the associated verbs. The information may be program instructions, parametric data, requests for information, etc.

Abstract: In one embodiment, the present invention includes a method for requesting an allocation of memory to be a backing store for architectural state information of a processor and storing the architectural state information in the backing store using an application. In this manner, the backing store and processor enhancements using information in the backing store may be transparent to an operating system. Other embodiments are described and claimed.

Abstract: An integrated circuit includes a plurality of processor cores and a readable non-volatile memory that stores information expressive of at least one operating characteristic for each of the plurality of processor cores. Also disclosed is a method to operate a data processing system, where the method includes providing a multicore processor that contains a plurality of processor cores and a readable non-volatile memory that stores information, determined during a testing operation, that is indicative of at least a maximum operating frequency for each of the plurality of processor cores. The method further includes operating a scheduler coupled to an operating system and to the multicore processor, where the scheduler is operated to be responsive at least in part to information read from the memory to schedule the execution of threads to individual ones of the processor cores for a more optimal usage of energy.

Abstract: A computer architecture and programming model for high speed processing over broadband networks are provided. The architecture employs a consistent modular structure, a common computing module and uniform software cells. The common computing module includes a control processor, a plurality of processing units, a plurality of local memories from which the processing units process programs, a direct memory access controller and a shared main memory. A synchronized system and method for the coordinated reading and writing of data to and from the shared main memory by the processing units also are provided. A hardware sandbox structure is provided for security against the corruption of data among the programs being processed by the processing units. The uniform software cells contain both data and applications and are structured for processing by any of the processors of the network. Each software cell is uniquely identified on the network.

Abstract: A mechanism receives memory reads and writes from a packet processing engine, each memory access having an associated packet identifier or sequence number. The mechanism is placed between the packet processing engine and a memory system such that write data is buffered and information based upon both reads and writes is recorded. Information is maintained allowing the detection of memory conflicts. Both a strict and alternate packet ordering are evaluated, such that the semantic ordering of packets is delayed until necessary to ensure that a consistent order exists. Such a late order binding mechanism is used to allow packets to be defined in any order so long as they obey a consistent order, thereby reducing the number of packet restarts and increasing overall efficiency.

Abstract: A method of transferring guard values and a computer system, such as a processor for digital signal processing, including a parallel set of execution units that utilizes the method. A master set of guard indicators is held in association with one of the execution units. If other execution units require the guard values for particular guard indicators, a sendguard instruction is issued to the execution unit holding the master guard values. The sendguard instructions are held in a separate queue from the main instructions intended for that execution unit. Circuitry is provided in the execution unit to avoid stalling in the dispatch of sendguard instructions even in the context of earlier guard modifying instructions.

Abstract: An information delivery apparatus includes an encoding information collection unit which collects information used to encode content information, a generation unit which predicts decode processes of the content information based on the collected information, and generates configuration information used to configure data paths required to execute the decode processes, an embedding unit which embeds the configuration information in the content information, and a delivery unit which delivers the content information embedded with the configuration information.

Abstract: The present invention provides for parallel subword instructions that cause results to be non-contiguously stored in a result register. For example, a targeting-type instruction can specify (implicitly or explicitly) a bit position and the result of each of the parallel subword compare operations can be stored at that bit position within the respective subword location of a result register. Alternatively, for a shifting-type instruction, pre-existing contents of a result register can be shifted one bit toward greater significance while the results are of the present operation are stored in the least-significant bits of respective result-register subword locations. This approach provides the results of multiple parallel subword compare instructions to be combined with relatively few instructions and reduces the maximum lateral movement of information—both of which can enhance performance.

Abstract: In some embodiments, the execution of load and store instructions for internal fields of data structures is accelerated by using on-chip template registers and appropriate machine code instructions. A load/store machine code instruction comprises an identifier of a memory address offset of an internal field word relative to a base address of the data structure, an identifier of an intra-word start bit of the internal field, and an identifier of an intra-word length of the internal field. The three identifiers may coincide, for example if the three identifiers are represented by an identity of a template register storing a template entry including the memory address offset, the start position, and the field length. The three identifiers may also be provided as part of a machine code instruction itself. Further provided are compilers, compiler methods, and hardware systems for implementing accelerated internal-field load and store operations.

Abstract: Methods and related computer program products, systems, and devices for using a NAND flash as a program ROM are disclosed.

Abstract: A threshold mechanism is provided so that a producer and a corresponding consumer, executing on the same resource (e.g., CPU) are able to switch context between them in a manner that reduces the total number of such context switches. The threshold mechanism is associated with a buffer into which the producer stores packets up to a given threshold before the consumer is allowed to remove packets. The buffer has an associated upper limit on the number of packets that can be stored in the buffer. A flush empties the buffer of any remaining packets when no more packets are to be produced. This reduction in the total number of context switches in general leads to better performance at the cost of more latency.

Abstract: A method and system for updating electronic operating instructions of a vehicle is provided. Local operating instruction data objects are stored in a local storage device arranged in the vehicle so that they can be used by the driver. Corresponding current operating instruction data objects are stored in an external storage device. One data object category, respectively, is assigned to the operating instruction data objects. For updating, a current operating instruction data object is transmitted from the external storage device to the local storage device in order to modify the corresponding local operating instruction data object in the local storage device The frequency of the updating of a local operating instruction data object depends on the data object category assigned to the data object.

Abstract: A processor includes an instruction decoder, an instruction execution part and a register file. The instruction decoder is adapted to decode an instruction. The instruction execution part is adapted to execute processing corresponding to the instruction decoded by the instruction decoder. The register file is capable of storing load data from a data memory and supplying input data to the instruction execution part. The register file includes a plurality of registers, each of which is capable of holding a plurality of bits of data. Furthermore, the register file is configured to update the data held by the plurality of registers by shifting the data held by the plurality of registers among the plurality of registers.

Abstract: A mechanism receives start and done commands containing packet identifiers or sequence numbers from a packet processing engine for packets for which processing is being started and for which processing has completed respectively. Upon receiving a packet start command, an entry in an active packet list is created. Upon receiving a packet done command, the active packet list is updated. The oldest done packet in the active list is retired by flushing buffered write information to a memory system. The active packet list can be used in conjunction with a system supporting speculative reads and conflict detection. In some embodiments the packet start command is inferred from a read command containing a packet identifier or sequence number.

Abstract: An apparatus includes an instruction generator which generates a load instruction and a first store instruction from a program, a processor which executes said load and store instruction, wherein said instruction generator analyzes a relevancy between said load instruction and said first store instruction with respect to memory addresses accessed by said instructions, specifies a second store instruction irrelevant to said load instruction with respect to said memory address, and notifies said second store instruction to said processor, wherein said processor executes said load instruction in advance of said second store instruction during said processor prepares to execute said second store instruction.

Abstract: The invention relates to a method for operating a multiprocessor system, especially in conjunction with a medical imaging system. The invention also relates to a medical imaging device which is designed to perform this method. The multiprocessor system in this case has at least two processing units, at least one control unit and operations which can be allocated to the processing units. Data provided from an input is processed by the processing unit and made available at an output. The at least one control unit enhances the named data with control data, which defines an allocation of the data to the respective operations for the purposes of processing.

Abstract: A two-dimensional command block queue includes a plurality of command blocks in a first linked list. One of the command blocks in a string is included in the first linked list. The string is delimited by only a tail pointer stored in a tail pointer list. Following dequeuing the string for processing, a pointer to the one command block of the string that was in the common queue is included in a string head pointer list. The tail pointer to the string is not changed in the tail pointer list following dequeuing of the string. This allows any new SCBs to be appended to the end of the string, while the string is being processed. This allows streaming of new SCBs to an I/O device that had previously been selected and is still connected to the host adapter.

Abstract: One embodiment of the present invention provides a system that facilitates deferring execution of instructions with unresolved data dependencies as they are issued for execution in program order. During a normal execution mode, the system issues instructions for execution in program order. Upon encountering an unresolved data dependency during execution of an instruction, the system generates a checkpoint that can subsequently be used to return execution of the program to the point of the instruction. Next, the system executes the instruction and subsequent instructions in an execute-ahead mode, wherein instructions that cannot be executed because of an unresolved data dependency are deferred, and wherein other non-deferred instructions are executed in program order. Upon encountering a store during the execute-ahead mode, the system determines if the store buffer is full. If so, the system prefetches a cache line for the store, and defers execution of the store.

Abstract: A system comprises a system interface to receive one or more instruction sets from a microcontroller and to receive digital data to be processed. The system further comprises a controller that is reconfigurable according to the one or more instruction sets received by the system interface. The system further comprises a data path device to perform digital filtering operations on the digital data as directed by the controller according to the reconfiguration of the controller by the one or more instruction sets.

Abstract: We propose a class of mechanisms to support a new style of synchronization that offers simple and efficient solutions to several existing problems for which existing solutions are complicated, expensive, and/or otherwise inadequate. In general, the proposed mechanisms allow a program to read from a first memory location (called the “flagged” location), and to then continue execution, storing values to zero or more other memory locations such that these stores take effect (i.e., become visible in the memory system) only while the flagged memory location does not change. In some embodiments, the mechanisms further allow the program to determine when the first memory location has changed. We call the proposed mechanisms conditional multi-store synchronization mechanisms.

Abstract: The queue execution mode is selected based on the unique tag that is assigned to the command. In one method embodiment a tag is assigned for each of several disc access commands sent by the host. Two or more queues are created, each having a queue execution mode. Which of the queues is assigned to the command depends on the command's tag. One device embodiment comprises a data storage disc, a memory, and a controller. The memory is configured to hold several pending commands for accessing the disc(s),each of the commands having a unique tag. The controller is configured to execute each queued command according to a mode that is determined base on the command's tag.

Abstract: The present information processing apparatus, which receives and executes commands, monitors time-outs of commands with reliability, thereby making it possible to prevent a command initiator from detecting time-outs of the commands. The apparatus includes: a time stamp unit for storing, in a command buffer, a receiving time at which a command receiving unit received a command, in association with the command; and a read-out time-out detecting unit for detecting read-out time-out of a first buffered command in the command buffer, based on the receiving time of the first buffered command. If the read-out time-out detecting unit detects a read-out time-out, the command executing unit reads the command, for which the read-out time-out is detected, from the command buffer and executes the read-out command.

Abstract: The processor includes: a plurality of functional bocks that are respectively synchronized and operates to perform a process according to a control signal; a connection unit that is changeable to a smaller bandwidth than a bandwidth of inputs/outputs of the respective functional blocks and is connected between the respective functional blocks; a first data converter that switches a bandwidth of the connection unit; a second data converter that switches a data transmission rate of input/output data of the respective functional blocks; and a controller that controls the first data converter and the second data converter.

Abstract: Techniques for performing a bit rake instruction in a programmable processor. The bit rake instruction extracts an arbitrary pattern of bits from a source register, based on a mask provided in another register, and packs and right justifies the bits into a target register. The bit rake instruction allows any set of bits from the source register to be packed together.

Abstract: A mechanism receives memory reads and writes from a packet processing engine, each memory access having an associated packet identifier or sequence number. The mechanism is placed between a processing element and a memory system such that write data is buffered and information based upon both reads and writes is recorded. Information is maintained allowing the detection of memory conflicts. The packet processor implements a checkpoint repair mechanism allowing processing to restart from defined checkpoints. In some embodiments this is done with sub-sequence numbers. When a memory conflict is detected a restart signal is generated to backup and restart from a given checkpoint.

Abstract: A tag monitoring system for assigning tags to instructions embodied in software on a tangible computer-readable storage medium. A source supplies instructions to be executed by a functional unit. A queue having a plurality of slots containing tags which are used for tagging instructions. A register file stores information required for the execution of each instruction at a location in the register file defined by the tag assigned to that instruction. A control unit monitors the completion of executed instructions and advances the tags in the queue upon completion of an executed instruction. The register file also contains a plurality of read address enable ports and corresponding read output ports. Each of the slots from the queue is coupled to a corresponding one of the read address enable ports. Thus, the information for each instruction can be read out of the register file in program order.

Abstract: The invention provides a method of transmitting messages over an interconnect between processors, each message comprising a header token specifying a destination processor and at least one of a data token and a control token. The method comprises: executing a first instruction on a first one of the processors to generate a data token comprising a byte of data and at least one additional bit to identify that token as a data token, and outputting the data token from the first processor onto the interconnect as part of one of the messages. The method also comprises executing a second instruction on said first processor to generate a control token comprising a byte of control information and at least one additional bit to identify that token as a control token, and outputting the control token from the first processor onto the interconnect as part of one of the messages.

Abstract: A service management system for devices with embedded processor systems manages use of memory by programs implementing the services by assigning services to classes and limiting the number of services per class that can be loaded into memory. Classes enable achieving predictable and stable system behavior, defining the services and service classes in a manifest that is downloaded to embedded devices operating on a network, such as a cable or satellite television network, telephone or computer network, and permit a system operator, administrator, or manager to manage the operation of the embedded devices while deploying new services implemented with applications downloaded from the network when the service is requested by a user.

Abstract: A queue processor and its data processing method are provided. It can do high-speed data processing and decreases the electric energy consumption. The queue processor equips multiple operation data storing queues (18, 19) for storing the obtained memory stored data and intermediate result data during processing, and multiple execution units (17a, 17b, 17c) accessible to each of multiple operation data storing queues (18, 19), the execution unit (17a, 17b, 17c) doing the processing using memory stored data or intermediate result data obtained from any one of multiple operation data storing queues (18, 19), the execution units (17a, 17b, 17c) storing a calculated result in any one of multiple operation data storing queues (18, 19).

Abstract: A mechanism receives memory reads and writes from a packet processing engine, each memory access having an associated packet identifier or sequence number. The mechanism is placed between a processing element and a memory system such that write data is buffered and information based upon reads and writes is recorded. Information is maintained, including a write dependency list, allowing for the detection of memory conflicts. When a memory conflict is detected, a restart signal is generated and the entries for the associated sequence number are flushed. Further, the write dependency list is consulted to determine if other packets have been potentially corrupted and also need to be flushed. Upon detection of dependent packets that have potentially been corrupted, further packet restart signals are generated and sent to the packet processing engine.

Abstract: A mechanism receives memory reads and writes from a packet processing engine, each memory access having an associated packet identifier or sequence number. The mechanism is placed between a processing element and a memory system such that write data is buffered and information based upon reads and writes is recorded. Upon receiving a memory write, conflict detection logic determines if a conflict has occurred and if packet processing for a packet needs to be restarted. When such a conflict occurs, restart logic conditionally delays the restart to the packet processing engine. This can be accomplished using a stall signal or by delaying the return of the first memory read after the restart. Such a conditional delayed restart mechanism can optimize processing based on the likelihood of multiple conflicts or a single conflict.

Abstract: A design structure for a circuit function that implements a load when reservation lost instruction for performing cacheline polling is disclosed. Initially, a first process requests an action to be performed by a second process. The request is made via a store operation to a cacheable memory location. The first process then reads the cacheable memory location via a conditional load operation to determine whether or not the requested action has been completed by the second process, and the first process sets a reservation at the cacheable memory location if the requested action has not been completed by the second process. The conditional load operation of the first process is stalled until the reservation at the cacheable memory location has been lost. After the requested action has been completed, the reservation in the cacheable memory location is reset by the second process.

Abstract: A design structure embodied in a machine readable storage medium for designing, manufacturing, and/or testing a design for forwarding data in a processor is provided. The design structure includes a processor. The processor includes at least one cascaded delayed execution pipeline unit having a first and second pipeline, wherein the second pipeline is configured to execute instructions in a common issue group in a delayed manner relative to the first pipeline, and circuitry. The circuitry is configured to determine if a first instruction being executed in the first pipeline modifies data in a data register which is accessed by a second instruction being executed in the second pipeline, and if the first instruction being executed in the first pipeline modifies data in the data register which is accessed by the second instruction being executed in the second pipeline, forward the modified data from the first pipeline to the second pipeline.

Abstract: In one embodiment, a processor comprises a retire unit and a load/store unit coupled thereto. The retire unit is configured to retire a first store memory operation responsive to the first store memory operation having been processed at least to a pipeline stage at which exceptions are reported for the first store memory operation. The load/store unit comprises a queue having a first entry assigned to the first store memory operation. The load/store unit is configured to retain the first store memory operation in the first entry subsequent to retirement of the first store memory operation if the first store memory operation is not complete. The queue may have multiple entries, and more than one store may be retained in the queue after being retired by the retire unit.

Abstract: Briefly, in accordance with an embodiment of the invention, an apparatus and method to enable execution of a thread in a multi-threaded computer system is provided. The method may include enabling execution of a non-executing thread based at least on whether a hardware resource is or will be available to an instruction of the non-executing thread. The apparatus may include a thread dispatch circuit to enable execution of a pending thread based at least on whether a hardware resource is or will be available to an instruction of the non-executing thread.