Abstract: Techniques can include: configuring source sites in a replication configuration with a target site; receiving, at a first of the source sites from a host, a write I/O to a target location of a source storage object of the source site; sending a replicated write corresponding to the write I/O from the first source site to the target site, wherein the replicated write writes to the target location of a target storage object of the target site; prioritizing the replicated write, based at least in part, on a site-level priority associated with the first source site; placing the first replicated write in a first queue of a first plurality of queues based, at least in part, on the site level priority associated with the first source site; selecting the first replicated write from said first queue; and servicing the first replicated write.

Abstract: A method of adjusting core and un-core operating frequencies of two or more processors of a server includes determining core and un-core operating frequency variations versus power consumption limit variations of the two or more processors. The method also includes determining two or more first power consumption levels associated with the two or more processors. Each one of the two or more processors run at essentially a same target core operating frequency and at a same target un-core operating frequency at the respective first power consumption level of the processor. The method further includes adjusting the core and un-core operating frequencies of the two or more processors by setting a power consumption limit of each one of the two or more processors at the respective first power consumption level of the processor.

Abstract: A computing device includes a host device and a storage device. The host device is configured to receive instruction information via a code bus based on a code address comprised in a code address map of particular address maps and receive data via a system bus that is separate from the code bus based on a data address included in a data address map. The storage device is configured to store target instruction information via the system bus and provide the target instruction information to the host device via the code bus in response to a request from the host device for an object code address included in the code address map and corresponding to the target instruction information.

Abstract: Trace recording based on data influxes to an outer-level cache and cache coherence protocol (CCP) transitions between inner caches. Example computing device(s) include a plurality of processing units, a plurality of (N-1)-level caches, and an N-level cache that is associated with two or more of the (N-1)-level caches and that is a backing store for the two or more (N-1)-level caches. Based at least on detecting influx(es) of data to a location in the N-level cache during execution across the processing units, the computing device(s) causes the influx(es) of data to be logged. The computing device(s) also causes one or more (N-1)-level CCP transitions between the two or more (N-1)-level caches to be logged. The (N-1)-level CCP transitions result from the location being accessed by two or more of the processing units.

Abstract: In one embodiment, an apparatus comprises a fabric controller of a first computing node. The fabric controller is to receive, from a second computing node via a network fabric that couples the first computing node to the second computing node, a request to execute a kernel on a field-programmable gate array (FPGA) of the first computing node; instruct the FPGA to execute the kernel; and send a result of the execution of the kernel to the second computing node via the network fabric.

Abstract: An integrated circuit device may include programmable logic circuitry on a first integrated circuit die and memory that includes compute-in-memory circuitry on a second die. The programmable logic circuitry may be programmed with a circuit design that operates on a first set of data. The compute-in-memory circuitry of the memory may perform an arithmetic operation using the first set of data from the programmable logic circuitry and a second set of data stored in the memory.

Abstract: Systems, apparatuses, and methods related to hierarchical memory are described. A hierarchical memory system that can leverage persistent memory to store data that is generally stored in a non-persistent memory. Logic circuitry can be configured to determine that a request to access a persistent memory device corresponds to an operation to divert data from the non-persistent memory device to the persistent memory device, generate an interrupt signal, and cause the interrupt signal to be asserted on a host coupleable to the logic circuitry as part of the operation to divert data from the non-persistent memory device to the persistent memory device. Access data and control messages can be transferred between or within a memory device, including to or from a multiplexer and/or a state machine. A state machine can include logic circuitry configured to transfer interrupt request messages to and receive interrupt request messages.

Abstract: A method for maintaining coherence for memory storage devices comprising a plurality of controllers in a side-by-side configuration. The method includes generating, by a first controller of the plurality of controllers, a first plurality of requests to access a first plurality of memory ranges; receiving, by the first controller from a second controller of the plurality of controllers, a second plurality of requests to access a second plurality of memory ranges; and serializing, by the first controller, the first plurality of requests and the second plurality of requests to generate a serialized request.

Abstract: A leadless pacemaker, and method for storing event data therein, comprising a central processing unit, a first logic circuit configured to generate event data based on a first event occurring during operation of the leadless pacemaker, a first hardware event counter configured to be incremented if specific event data are generated by said first logic circuit, a first memory unit comprising a first bit configured to be set if said first hardware event counter is incremented to a first maximum number of counts, a second memory unit communicating with said first memory unit, wherein said central processing unit is configured to transfer said first bit to said second memory unit, a first RAM event counter in a random access memory of said leadless pacemaker, wherein said central processing unit is configured to increment said first RAM event counter if said first bit is transferred to the second memory unit.

Abstract: Graphics processors for implementing multi-tile memory management are disclosed. In one embodiment, a graphics processor includes a first graphics device having a local memory, a second graphics device having a local memory, and a graphics driver to provide a single virtual allocation with a common virtual address range to mirror a resource to each local memory of the first and second graphics devices.

Abstract: A program generation method includes extracting a control flow that represents a call/return relationship between functions as well as extracting the functions themselves from a program code, determining an importance of the extracted functions; and inserting an instruction into the program code, to properly perform the control flow based on the importance of the extracted functions. Overhead that occurs during an execution of the program execution is reducible by using control flow integrity (CFI) technique that does not depend on domains.

Abstract: An information processing apparatus, includes a memory; and a first processor coupled to the memory and configured to: identify a maximum operating frequency of each of a plurality of second processors, when executing a plurality of processes to be subjected to parallel processing by the plurality of second processors, measure a load value representing a magnitude of a load of each of the plurality of processes, and determine, based on the identified maximum operating frequency of each of the plurality of second processors and the measured load value of each of the plurality of processes, a specific processor as an assignment destination of each of the plurality of processes from the plurality of second processors.

Abstract: To set data breakpoints on properties and certain other functions, constituent data locations (CDLs) that can contribute to computation of the property value or other function result are identified, and respective constituent data breakpoints are added at one or more CDLs by data breakpoint adder code. Each constituent data breakpoint will suspend execution of an inspectable software in response to occurrence of a CDL data entry. The CDLs are identified by CDL identifier code using static data flow analysis, enhanced interpretation, or disassembly, with recursion as appropriate. Kernel or runtime routines, and other routines designated as known, can be excluded from the CDL search. Data locations marked read-only, or that are effectively read-only because they will not be written, can also be excluded.

Abstract: Methods, articles of manufacture, and apparatus are disclosed to manage workload memory allocation. An example method includes identifying a primary memory and a secondary memory associated with a platform, the secondary memory having first performance metrics different from second performance metrics of the primary memory, identifying access metrics associated with a plurality of data elements invoked by a workload during execution on the platform, prioritizing a list of the plurality of data elements based on the access metrics associated with corresponding ones of the plurality of data elements, and reallocating a first one of the plurality of data elements from the primary memory to the secondary memory based on the priority of the first one of the plurality of memory elements.

Abstract: A system and method to automate validating media redirection in a virtual media redirection testing process. A computing device is provided for performing the test. During the test, the computing device executes an automated script to obtain, from a media storage device, a media file to be redirected, and then calculate a first checksum value for the media file being obtained. The computing device then executes a redirection module to perform the virtual media redirection process for the media file, and copy the media file to a local path of the computing device. Once the media file is redirected, the automated script calculates a second checksum value for the media file at the local path of the computing device. Thus, the media file may be validated by matching the two checksum values, and the redirection process is determined to be successful when the checksum values match.

Abstract: To optimize NC program cores included in a generated machining program and expedite operation of a machine tool. An optimization device includes a block analysis unit, a code processing unit, and a program generation unit. The block analysis unit analyzes a preparatory function code and/or an auxiliary function code for each of a plurality of blocks included in a first program. The code processing unit performs a process on the preparatory function code and/or the auxiliary function code in a plurality of successive blocks based on a result of the analysis by the block analysis unit and optimizes the first program. The program generation unit generates the first program optimized by the code processing unit as a second program.

Abstract: Software tracing can be accomplished in a multitenant environment according to various examples of the present disclosure. In one example, a processing device can receive tracing information and a tenant identifier. The tracing information can indicate a sequence in which a group of microservices forming a software application executed in response to a request transmitted to the software application. The tenant identifier can correspond to a particular tenant among a group of tenants having access to an instance of the software application. The processing device can then select, based on the tenant identifier, a particular collector from among a group of collectors corresponding to the group of tenants. The processing device can forward the tracing information to the particular collector for causing the tracing information to be stored in a datastore corresponding to the particular tenant.

Abstract: An apparatus and method are provided to control assertion of a trigger signal to processing circuitry. The apparatus has evaluation circuitry to receive program instruction execution information indicative of a program instruction executed by the processing circuitry, which is arranged to perform an evaluation operation to determine with reference to evaluation information whether the program instruction execution information indicates presence of a trigger condition. Trigger signal generation circuitry is used to assert a trigger signal to the processing circuitry in dependence on whether the trigger condition is determined to be present. Further, filter circuitry is arranged to receive event information indicative of at least one event occurring within the processing circuitry, and is arranged to determine with reference to filter control information and that event information whether a qualifying condition is present.

Abstract: A simultaneous multithreading processor and related method of operating are disclosed. The method comprises dispatching portions of a first instruction to be executed by a respective plurality of execution units of the processor; receiving, at an instruction completion table of the processor, respective finish reports responsive to execution of the portions of the first instruction; determining, using the received finish reports, that all of the portions of the first instruction have been executed; and updating the instruction completion table to indicate that the first instruction is ready for completion.

Abstract: A method for verifying data plane programs is provided in some embodiments. Because the behavior of a data plane program (e.g., a program written in the P4 language) is determined in part by the control plane populating match-action tables with specific forwarding rules, in some embodiments, programmers are provided with a way to document assumptions about the control plane using annotations (e.g., in the form of “assertions” or “assumptions” about the state based on the unknown control plane contribution). In some embodiments, annotations are added automatically to verify common properties, including checking that every header read or written is valid, that every expression has a well-defined value, and that all standard metadata is manipulated correctly. The method in some embodiments translates programs from a first language (e.g., P4) to a second language (e.g., Guarded Command Language (GCL)) for verification by a satisfiability modulo theory (SMT) solver.

Abstract: Interrupt code conversion for efficient computer program recovery. In response to an error being detected while processing instructions of a computer program running on a computer system, the OS receives a first program interrupt code (PIC) and interrupts the computer program. Control of the computer program is passed to a program interrupt handler and the program interrupt handler inspects the first PIC issued as a result of detecting the error. The first PIC is converted to a second PIC wherein the second PIC is associated with another error predicted when subsequent running of the computer program occurs. The second PIC is presented to a recovery routine associated with the computer program and, in response to the detected error, running of the computer program is customized based on the second PIC rather than the first PIC.

Abstract: Aspects of the invention include receiving, by a processor, a plurality of instructions at an instruction pipeline. The processor can further determine an operand bit field size for each of the received plurality of instructions. The processor can further compare the operand bit field size of at least a subset of the received instructions to a predetermined threshold. The processor can further fuse at least two of the received instructions that have an operand bit field size that meets the predetermined threshold. The processor can further perform an execution stage within the instruction pipeline to execute the received instructions, including the fused instructions.

Abstract: An apparatus and method are provided for executing debug instructions. The apparatus has processing circuitry for executing instructions fetched from memory, and a debug interface. The processing circuitry is responsive to a halt event to enter a halted mode where the processing circuitry stops executing the instructions fetched from memory, and instead is arranged to execute debug instructions received from a debugger via the debug interface. The processing circuitry is responsive to detection of a trigger condition when executing a given debug instruction to exit the halted mode transparently to the debugger, and to take an exception in order to execute exception handler code comprising a sequence of instructions fetched from memory. On return from the exception, the processing circuitry then re-enters the halted mode and performs any additional processing required to complete execution of the given debug instruction.

Abstract: A software only debug approach is provided that does not require special hardware in a target embedded system undergoing debug. Instead, already present DMA capabilities of the target system are utilized to transfer I/O operation parameters into a memory area accessible to both the target processor and a debugger executing on a host system. The debugger can thereby access and execute the I/O operations without program execution stopping on the target. A semihosting library is provided as a replacement for the standard C I/O library on the target. The semihosting library provides a range of equivalent functions to the standard C I/O API that program a DMA transfer to copy the I/O function parameters to an external memory area that is not otherwise being used by the target core processor. The external memory area is then accessed by a debug tool on the host computer.

Abstract: Operation of a multi-slice processor that includes execution slices and a dispatch network of the multi-slice processor implementing a hardware level transfer of an execution thread between execution slices. Operation of such a multi-slice processor includes responsive to a thread switch signal: halting dispatch of one or more instructions retrieved from an instruction cache; generating a plurality of instructions to transfer an execution thread from a first execution slice to a second execution slice; and dispatching the plurality of instructions instead of the one or more instructions retrieved from the instruction cache; and transferring, in dependence upon execution of the plurality of instructions from the thread switching instruction generator, the execution thread from the first execution slice to the second execution slice.

Abstract: A coprocessor stores at least part of an execution trace based on code execution at a primary processor. The coprocessor includes control logic that configures the coprocessor to listen to a bus that interconnects the primary processor and the coprocessor, and to receive one or more cache coherency protocol (CCP) messages from the bus (i.e., CCP message(s) sent on the bus by the primary processor, based on the primary processor having consumed data for a memory cell). Based on receiving the CCP message(s), the coprocessor initiates storing of the consumed data for the memory cell into an execution trace.

Abstract: Techniques for an extended prefix including a routing bit for an extended instruction format are described herein. An aspect includes generating, by an instruction preprocessing module, a first extended instruction corresponding to an internal operation including a first routing bit. Another aspect includes generating, by the instruction preprocessing module, a second extended instruction corresponding to a prefixed instruction set architecture (ISA) instruction including a second routing bit, wherein a value of the second routing bit is opposite a value of the first routing bit. Another aspect includes providing the first extended instruction and the second extended instruction to a central processing unit (CPU). Another aspect includes, based on the value of the first routing bit, routing the internal operation directly to an execution unit of the CPU, and based on the value of the second routing bit, routing the prefixed ISA instruction to a decode/execute path of the CPU.

Abstract: Digit validation check control for execution of an instruction. A process obtains an instruction to perform operation(s) using input value(s). The instruction includes a no validation indicator for controlling whether digit validation check control is enabled for execution of the instruction. The process executes the instruction, including determining, based on the no validation indicator, whether digit validation check control is enabled for execution of the instruction, and performing processing based on the determining. Based on the no validation indicator being set to a defined value, digit validation check control is enabled and the processing includes forcing a digit check error indicator output by the executing to indicate no digit check error with respect to the at least one input value.

Abstract: Embodiments of the present invention are directed to techniques for optimizing an execution mode used to process a request. A self-training storage system can determine one or more proposed execution modes based on a real-time evaluation of various factors, including a history of execution modes used to process historical requests. This history can serve as training data for a machine learning model that can predict an execution mode based on one or more request parameters. This predicted execution mode can be taken as one of a number of proposed execution modes that can be combined using a weightage system to automatically classify an ultimate execution mode used to process the request. Associated weights for combining proposed execution modes can be determined by training a machine learning model using a training set constructed based on a survey of user satisfaction with a determined execution mode.

Abstract: Methods and systems for performing mainframe batch testing and/or property-based validation testing using a finite-state machine are provided. According to certain aspects, a validation server may receive a set of batch data designed to validate a property under test, such as during mainframe batch testing. A validation server may validate that the set of batch data is in a proper format. The validation server may then cause a finite-state machine to process instructions contained within the set of batch data. Once the finite-state machine processes the set of batch data, the validation server may then validate that the finite-state machine adheres to the property under test. If the validation fails, the validation server may generate an error report describing the failure.

Abstract: This information processing system (100) includes an information processing device (1) and a display input device (2). The display input device (2) receives settings of a first target, first processing, a second target, and second processing. The information processing device (1) takes, as a condition, the execution of the set first processing by using the set first target, and, when the condition is satisfied, generates a workflow (5) for executing the set second processing by using the set second target.

Abstract: A processor receives a signal and determines whether an application has registered a signal handler therewith for handling the signal. In response to determining that the application has registered the signal handler, the processor transmits the signal directly to the signal handler of the application for handling the signal, without an operating system in relation to which the trusted application is running intervening. In response to determining that the trusted application has not registered the signal handler, the processor transmits the signal to a signal handler of the operating system for handling the signal.

Abstract: A method and system for enabling persistence of a value by a dynamically reconfigurable processor (“DRP”) from the time of execution of an earlier executed instruction to a time of later executed instruction. The value may represent a constant a variable value of a software program. The value may be read from or written into a memory circuit, a DRP logic element, an iterator of a DRP logic element, or other value storing element or aspect of the DRP. The value may be maintained in a single logic element through the duration of one or more instruction execution cycles, or alternatively or additionally, the value may be transferred between or among one or more value storage hardware elements. The persistence of the value and transfer of the value within, into and/or out of the DRP enables later access of the value by, and/or positioning the value within, the DRP.

Abstract: A method includes, in one non-limiting embodiment, sending a request from a mass memory storage device to a host device, the request being one to allocate memory in the host device; writing data from the mass memory storage device to allocated memory of the host device; and subsequently reading the data from the allocated memory to the mass memory storage device. The memory may be embodied as flash memory, and the data may be related to a file system stored in the flash memory. The method enables the mass memory storage device to extend its internal volatile RAM to include RAM of the host device, enabling the internal RAM to be powered off while preserving data and context stored in the internal RAM.

Abstract: An apparatus has processing circuitry to perform, in response to decoding of an iterative-operation instruction by the instruction decoder, an iterative operation comprising at least two iterations of processing where one iteration depends on an operand generated in a previous iteration. Preliminary information generating circuitry performs a preliminary portion of processing for a given iteration to generate preliminary information. Result generating circuitry performs a remaining portion of processing for the given iteration, to generate a result value using the preliminary information. Forwarding circuitry forwards the result value as an operand for a next iteration of the iterative operation, for iterations other than the final iteration. The preliminary information generating circuitry starts performing the preliminary portion for the next iteration in parallel with the result generating circuitry completing the remaining portion for the current iteration, to improve performance.

Abstract: Provided are systems, methods, and media for concurrency conflict testing for shared resources. An example method includes identifying shared resources that are to be accessed by an application. Generating a plurality of concurrency test scenarios based on the shared resources. Analyzing a plurality of concurrency test cases to detect which concurrency test cases include a reference to the shared resources. Executing a concurrency test scenario.

Abstract: Techniques are described herein for isolating runtime environments in a multitenant container DBMS. A CDB may contain a database dictionary that defines a plurality of pluggable databases and a respective database nest for each pluggable database. Each respective database nest of said each pluggable database is associated with different operating system privileges. When database sessions are established on a container DBMS, each database session is given access to a pluggable database by attaching the respective database nest of the pluggable database to each database session.

Abstract: Techniques are described for managing access tokens in a computing environment. A proxy service can be configured to issue a first token to a workflow engine, the first token having a substantially unlimited lifetime to not time out during the workflow duration. The first token may be provided to the workflow in place of a shorter-lifetime token that may have otherwise been requested from a backend service. The first token may be used by the workflow engine to provide authorization for operations of the workflow. On completion of the workflow, the workflow engine may send an indication to the proxy service to request interactions with the backend service. The proxy service may request a second (e.g., limited-lifetime) token from the backend service, and use the second token to interact with the backend service on behalf of the workflow, thus acting as an intermediary between the workflow and the backend service.

Abstract: A method and a circuit for implementing single event upset (SEU) parity detection, and a design structure on which the subject circuit resides are provided. The circuit implements detection of unwanted state changes due to SEUs, noise or other event in a latch having a default state of zero. The latch includes an L1 latch and an L2 latch with the L2 latch having the connected output and is used and monitored for a flip. A pair of series-connected field effect transistors (FETs) is connected between a drive input of a parity control circuit and ground potential. An inverted output of the L1 latch and a true output of the L2 latch is applied to a respective gate of the pair of series-connected FETs.

Abstract: Systems, methods, and products for database system transaction management are provided herein. One aspect provides for annotating via a computing device at least one data object residing on the computing device utilizing at least one transaction tag, the at least one transaction tag being configured to indicate a status of an associated data object; processing at least one database transaction utilizing a transactional memory process, wherein access to the at least one data object is determined based on the status of the at least one data object; and updating the status of the at least one data object responsive to an attempted access of the at least one data object by the at least one database transaction. Other embodiments and aspects are also described herein.

Abstract: A computation unit having at least one computation core, a primary memory device, and at least one main connecting unit for connecting the at least one computation core to the primary memory device, the computation unit having at least two functional units, at least a first functional unit of the at least two functional units being embodied a) to receive first data from at least one further functional unit of the at least two functional units, and/or b) to transmit second data to at least one further functional unit of the at least two functional units.

Abstract: The present invention provides a TrustZone-based security isolation system for shared library, the system at least comprising: a sandbox creator, a library controller, and an interceptor, the sandbox creator, in a normal world, dynamically creating a sandbox isolated from a Rich OS, the interceptor, intercepting corresponding system-calling information and/or Android framework APIs by means of inter-process stack inspection, the library controller, performing analysis based on the intercepted system-calling information and/or Android framework APIs, redirecting a library function to the sandbox, and switching calling states of the library function in the sandbox as well as setting up a library authority. The present invention has good versatility, low cost and high security. It realizes isolation of the library without increasing the trusted bases in the Secure World of the TrustZone, effectively reducing the risk of being attacked.

Abstract: Expressly turning tracing on and off at each juncture between code that a developer wants to have traced and other code may reduce trace file size but adds computational cost. Described technologies support selectively tracing a process's execution, with some extra tracing done beyond the code the developer wanted traced, but with significantly reduced computational cost, by reducing the number of trace enablement and disablement operations. A trace controller uses a tracing disablement distance variable whose values indicate the computational distance from trace disablement. A distance variable modifier automatically moves the distance variable closer to a stop-tracing value as the process executes. The amount of extra tracing is balanced against the reduction in trace enablement/disablement operations by tuning thresholds, based on information about routine size and computational cost.

Abstract: Described technologies support selectively tracing a process's execution, with some extra tracing done beyond the code the developer wanted traced, but with significantly reduced computational cost, by reducing the number of trace enablement and disablement operations. A trace controller uses a tracing disablement distance variable whose values indicate the computational distance from trace disablement. A distance variable modifier automatically moves the distance variable closer to a stop-tracing value as the process executes. A create task function is modified to include the setting of an indicator that a newly created task is to be traced if a current task or thread is being traced. An execute task function is modified to request the tracing of the newly created task when it is executed based on the indicator, thereby enabling selective tracing that operates across process boundaries and traces asynchronous code execution.

Abstract: An integrated circuit can include a functional unit and a local debug unit. The local debug unit can include a trace buffer, and the local debug unit is configured to track and store operation information of the functional unit in the trace buffer. The integrated circuit can also include a global debug unit coupled to the local debug unit. The integrated circuit is configured to send a debug reset command to reset the functional unit, without sending the debug reset command to the local debug unit, thereby retaining information stored in the trace buffer. The integrated circuit is also configured to send a power-up reset command to reset the local debug unit and the functional unit, thereby causing the local debug unit to clear the trace buffer.

Abstract: A processing apparatus is described. The apparatus includes a graphics processing unit (GPU), including a plurality of execution units to process graphics context data and a register file having a plurality of registers to store the graphics context data; and register renaming logic to facilitate re-use of register data by partitioning a first part and a second part, the first part to include thread-independent code and the second part to include thread-dependent code.

Abstract: Processing circuitry 2 includes data storage circuitry 18 for storing one or more ordered sets of data entries. Access control circuitry 20 controls access during a given access cycle to a given ordered set of data entries in dependence upon, for that given set of data entries, a head-entry flag, a next-following-entry flag and preceding-cycle data. The head-entry flag indicates the oldest data entry for the given ordered set, the next-following-entry flag indicates the next oldest entry and the preceding-cycle flag indicates whether the given ordered set was accessed during a preceding access cycle. If the given ordered set was accessed during the preceding access cycle, then the next-following entry corresponding to the next-following flag is accessed during the current access cycle instead of that indicated by the head flag.

Abstract: A method for managing a discontinuous call stack is disclosed to more efficiently use the memory of devices without a memory management unit.

Abstract: A process for processor testing includes generating a set of test instructions having a first portion and a second portion. A first branch instruction is randomly generated for the first portion where the first branch instruction branches to a respective instruction in a second portion by a branching location offset. A second branch instruction is randomly generated for the second portion where the second branch instruction branches to a respective instruction in the first portion by the branching location offset. If additional instructions are to be added to the set of test instructions, a value of the branching location offset is incrementing by a predetermined amount.

Abstract: Provided is a vectorization device 30 comprising: a unit 31 that detects a configuration in which the inner loop length depends on the outer loop variable, and in which a first array indicating the results of dual-loop processing does not contain the inner loop variable as an index value; an unit 32 that, when the configuration is detected, determines a fixed value as the inner loop length; an unit 33 that expands the array size of a second array used in the calculation of the first array value, and thereby enables dual-loop processing of the inner loop; an unit 34 that sets an element value for an added element of the second array, and thereby, before and after such processing is carried out, enables the results of the dual-loop processing to be made equal; and an unit 35 that updates the software on the basis of such processing results.