Specialized Instruction Processing In Support Of Testing, Debugging, Emulation Patents (Class 712/227)
  • Patent number: 10152406
    Abstract: According to an aspect of an embodiment, one or more systems or methods may be configured to locate a fault in a software program using a test suite. The systems or methods may be further configured to modify, using a repair template, the software program in response to locating the fault. In addition, the systems or methods may be configured to determine whether the modification satisfies an anti-pattern condition. The anti-pattern condition may indicate whether the modification is improper. The systems or methods may also be configured to disallow the modification in response to the modification satisfying the anti-pattern condition or perform further testing on the software program, as modified, in response to the modification not satisfying the anti-pattern condition.
    Type: Grant
    Filed: August 25, 2015
    Date of Patent: December 11, 2018
    Assignee: FUJISTU LIMITED
    Inventors: Hiroaki Yoshida, Shin Hwei Tan, Mukul R. Prasad
  • Patent number: 10146607
    Abstract: The techniques described herein provides troubleshooting, monitoring, reporting and dynamic adjustments and virtualization to management of application delivery. A system can be completely external to an application delivery data path, or can be highly compatible for integration to the application delivery path. Entities can be billed on a per user, per application, per usage, or any combination of consumption-based billing.
    Type: Grant
    Filed: November 26, 2014
    Date of Patent: December 4, 2018
    Assignee: Anunta Technology Management Services Ltd.
    Inventors: Ananda Mukerji, Sanjiv Dalal, Vinod Jeyachandran
  • Patent number: 10140196
    Abstract: Systems and methods can use a testing framework for testing an event processing system. The testing framework operates to send a stream of input events for an event processing system, wherein each said input event is associated with a timestamp that is based on a system time, and wherein said event processing system processes the stream of input events in a batch mode with one or more sliding cycles. Furthermore, the testing framework can determine a base time for an event window in the system time, wherein said event window includes one or more input events in a sliding cycle that corresponds to a plurality of expected output events associated with a shared timestamp, and applies the event window on the stream of input events that are sent to the event processing system.
    Type: Grant
    Filed: February 9, 2015
    Date of Patent: November 27, 2018
    Assignee: ORACLE INTERNATIONAL CORPORATION
    Inventors: Guan Nan He, Ying Xi
  • Patent number: 10133569
    Abstract: An electronic circuit (4000) includes a bias value generator circuit (3900) operable to supply a varying bias value in a programmable range, and an instruction circuit (3625, 4010) responsive to a first instruction to program the range of said bias value generator circuit (3900) and further responsive to a second instruction having an operand to repeatedly issue said second instruction with said operand varied in an operand value range determined as a function of the varying bias value.
    Type: Grant
    Filed: December 15, 2016
    Date of Patent: November 20, 2018
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Kenichi Tashiro, Hiroyuki Mizuno, Yuji Umemoto
  • Patent number: 10120798
    Abstract: Technologies for field-programmable gate array (FPGA) processing include a computing device having a field-programmable gate array (FPGA) and a virtual FPGA controller (VFC). The computing device generates a user-specific platform profile (PP) that identifies one or more FPGA applications to be instantiated. The computing device synthesizes each FPGA application identified by the PP to generate a bit stream image that is associated with the PP and saves the bit stream image in a profile storage of the computing device. The computing device generates a virtual memory address that is indicative of the identified FPGA applications in response to saving the bit stream image. The VFC translates the virtual memory address to a user segment of the FPGA and a logical element (LE) offset within the user segment. The FPGA executes the bit stream associated with the PP with the FPGA at the LE offset. Other embodiments are described and claimed.
    Type: Grant
    Filed: June 12, 2017
    Date of Patent: November 6, 2018
    Assignee: Intel Corporation
    Inventors: Ned M. Smith, Rajesh Poornachandran, Abdul M. Bailey
  • Patent number: 10120770
    Abstract: Embodiments detect and group multiple failure events to enable batch processing of those failure events, such as in a virtual datacenter executing a plurality of virtual machines (VMs). A long timer, adaptive short timer, and adaptive polling frequency enable a computing device to efficiently detect and group the failure events that may be related (e.g., resulting from one failure). The grouped failure events are processed in parallel thereby reducing the time for recovery from the failure events.
    Type: Grant
    Filed: November 9, 2016
    Date of Patent: November 6, 2018
    Assignee: VMware, Inc.
    Inventors: Anjaneya Prasad Gondi, Hemanth Kalluri, Naveen Kumar Kalaskar
  • Patent number: 10114643
    Abstract: Various embodiments are generally directed to techniques to detect a return-oriented programming (ROP) attack by verifying target addresses of branch instructions during execution. An apparatus includes a processor component, and a comparison component for execution by the processor component to determine whether there is a matching valid target address for a target address of a branch instruction associated with a translated portion of a routine in a table comprising valid target addresses. Other embodiments are described and claimed.
    Type: Grant
    Filed: May 23, 2013
    Date of Patent: October 30, 2018
    Assignee: INTEL CORPORATION
    Inventors: Koichi Yamada, Palanivelra Shanmugavelayutham, Arvind Krishnaswamy, Jason M. Agron, Jiwei Lu
  • Patent number: 10102034
    Abstract: A method and device for clearing an application process, and a mobile terminal are provided. The method for clearing an application process includes: clearing the application process; obtaining a restart interval of the application process; and clearing the application process continuously according to the restart interval, until the restart interval is greater than a predetermined time.
    Type: Grant
    Filed: August 13, 2014
    Date of Patent: October 16, 2018
    Assignee: CONEW NETWORK TECHNOLOGY CO. LTD.
    Inventors: Peng Luo, Zongliang Lin, Kangzong Zhang, Shengmo Xu, Sheng Fu
  • Patent number: 10102115
    Abstract: An application can include program code in multiple programming languages. Typically, a primary or host application program code will include secondary program code of at least one other programming language embedded within the primary application program code. A selective testing framework can be designed that efficiently evaluates embedded program code separately from the host application program code. The selective testing framework records specified embedded program code detected during execution of the application. Recording the embedded program code while the application executes allows the selective testing framework to incrementally construct an independently testable program in accordance with execution of the application. The testing framework can then test the constructed program code as it would run within the application, but test it external to and independent of the application. Without the overhead of executing the primary program code (e.g.
    Type: Grant
    Filed: November 15, 2016
    Date of Patent: October 16, 2018
    Assignee: CA, Inc.
    Inventor: David William Cosgrove, Jr.
  • Patent number: 10095603
    Abstract: A method, computer program product and/or system for pre-fetching disassembly code. A breakpoint is set within an application under test (AUT). Setting of the breakpoint triggers pre-fetching of disassembly code associated with the breakpoint. The pre-fetched disassembly code is retained in a store local to a debug analysis system. When runtime processing of the AUT reaches the breakpoint, the debug analysis system retrieves the disassembly code from the local store.
    Type: Grant
    Filed: January 9, 2017
    Date of Patent: October 9, 2018
    Assignee: International Business Machines Corporation
    Inventors: Xiao Ling Chen, Chuan He, Yan Huang, Jiang Yi Liu, Jian Xu, Chong Zhou
  • Patent number: 10089262
    Abstract: A system and method for searching for and finding data across industrial time-series data is disclosed executing a series of instructions on a computer system. While executing a first instruction in the series of instructions, the virtual machine receives an interrupt signal. In response to receiving the interrupt signal, the virtual machine searches the series of instructions to identify a second instruction that is a safe point. The virtual machine replaces the second instruction in the series of instructions with one or more interrupt handler instructions that initiate an interrupt handler. The virtual machine resumes execution of the first instruction.
    Type: Grant
    Filed: June 19, 2015
    Date of Patent: October 2, 2018
    Assignee: SAP SE
    Inventor: Martin Doerr
  • Patent number: 10067851
    Abstract: A method, computer program product and/or system for pre-fetching disassembly code. A breakpoint is set within an application under test (AUT). Setting of the breakpoint triggers pre-fetching of disassembly code associated with the breakpoint. The pre-fetched disassembly code is retained in a store local to a debug analysis system. When runtime processing of the AUT reaches the breakpoint, the debug analysis system retrieves the disassembly code from the local store.
    Type: Grant
    Filed: August 22, 2017
    Date of Patent: September 4, 2018
    Assignee: International Business Machines Corporation
    Inventors: Xiao Ling Chen, Chuan He, Yan Huang, Jiang Yi Liu, Jian Xu, Chong Zhou
  • Patent number: 10042729
    Abstract: An apparatus and method are described for a scalable testing agent. For example, one embodiment of a scalable test engine comprises: an input interface to receive commands and/or data from a processor core or an external test system, the commands and/or data to specify one or more test operations to be performed on one or more intellectual property (IP) blocks of a chip; a first circuit to establish communication with an IP block over an interconnect fabric, the first circuit to transmit the one or more test operations to the IP block responsive to the received commands and/or data, the IP block to process the test operations and generate results; and a second circuit to receive the results from the IP block over the interconnect fabric, the results to be provided from the second circuit to the processor core and/or the external test system for analysis.
    Type: Grant
    Filed: April 1, 2016
    Date of Patent: August 7, 2018
    Assignee: Intel Corporation
    Inventors: Lakshminarayana Pappu, Robert De Gruijl, Suketu U. Bhatt, Robert P. Adler, R Selvakumar Raja Gopal, Rius Tanadi
  • Patent number: 10001992
    Abstract: A method includes: calculating a percentage of an instruction belonging to a certain instruction type among instruction types included in each of a plurality of blocks partitioned from a program; extracting an execution address and a number of execution instructions from an arithmetic processing unit that executes the program and performs sampling of the execution address and the number of execution instructions at a plurality of time points, calculating a first execution frequency of the instruction included in each of the plurality of blocks based on the extracted execution address and the number of execution instructions; calculating a second execution frequency of the instruction belonging to the instruction type by multiplying the first execution frequency of the block by the percentage of the instruction in the block; calculating total number of second execution frequencies calculated for each of the plurality of blocks.
    Type: Grant
    Filed: February 12, 2016
    Date of Patent: June 19, 2018
    Assignee: FUJITSU LIMITED
    Inventor: Masao Yamamoto
  • Patent number: 9971599
    Abstract: A processor includes support for executing binary-translated code including code modifications. The processor includes a processor core that includes a cache to store translation indicators from a physical map, each translation indicator to indicate whether a corresponding memory location includes translated code to be protected. The processor core also includes logic to execute a translated instruction. The translated instruction is translated from an instruction stored in a memory location. The processor core further includes logic to set a translation indicator in the cache corresponding to the memory location to indicate that it includes translated code to be protected. The processor core also includes logic to request senior store buffer drains of other processor cores of the processor based upon the execution of the translated instruction.
    Type: Grant
    Filed: May 8, 2017
    Date of Patent: May 15, 2018
    Assignee: Intel Corporation
    Inventors: John H. Kelm, David P. Keppel, David N. Mackintosh
  • Patent number: 9965280
    Abstract: A processor includes a front end to decode an instruction and pass the instruction to execution units with branch suffix information. The processor further includes execution units to execute the instruction and a retirement unit to retire the instruction. The instruction is to specify an operation to be conditionally executed based upon a branch suffix to identify previous execution. The processor further includes logic to, upon retirement of the instruction, determine the result of a series of branch operations preceding execution of the instruction, compare the result to the branch suffix information, allow execution and retirement of the instruction based on a determination that the result matches the branch suffix information, and generate a fault based on a determination that the result does not match the branch suffix information.
    Type: Grant
    Filed: September 25, 2015
    Date of Patent: May 8, 2018
    Assignee: Intel Corporation
    Inventors: Michael F. Spear, Gilles A. Pokam
  • Patent number: 9958503
    Abstract: An optimized JTAG interface is used to access JTAG Tap Domains within an integrated circuit. The interface requires fewer pins than the conventional JTAG interface and is thus more applicable than conventional JTAG interfaces on an integrated circuit where the availability of pins is limited. The interface may be used for a variety of serial communication operations such as, but not limited to, serial communication related integrated circuit test, emulation, debug, and/or trace operations.
    Type: Grant
    Filed: November 9, 2016
    Date of Patent: May 1, 2018
    Assignee: Texas Instruments Incorporated
    Inventor: Lee D. Whetsel
  • Patent number: 9934038
    Abstract: An acquisition unit acquires a command that is executable by a processor of an other type being a processor of a different type from a processor of a processing execution subject apparatus. An identification unit identifies processing that is executable by the processor of the processing execution subject apparatus which is associated with the command acquired by the acquisition unit. An execution control unit controls execution of the processing performed by the processor of the processing execution subject apparatus based on a value of a parameter which is set in a specific command for the processor of the other type, the value of the parameter which is set in the specific command not affecting execution of processing performed by the processor of the other type.
    Type: Grant
    Filed: June 18, 2012
    Date of Patent: April 3, 2018
    Assignee: Sony Interactive Entertainment Inc.
    Inventors: Tsutomu Teranishi, Tomohiro Oto
  • Patent number: 9934118
    Abstract: Embodiments disclose techniques for executing a test case to test a processor by bypassing an instruction pipeline of the processor. In one embodiment, the processor receives a plurality of test cases to execute on the processor. Each test case includes one or more instructions. Once received, the processor loads a plurality of registers with one or more first register values for the test case by bypassing the instruction pipeline. Once loaded, the processor runs the test case using the one or more first register values. The processor then retrieves, from the plurality of registers, one or more second register values associated with results of the test case run, by bypassing the instruction pipeline.
    Type: Grant
    Filed: January 22, 2016
    Date of Patent: April 3, 2018
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventor: Shakti Kapoor
  • Patent number: 9921979
    Abstract: Methods, systems, and computer program products for executing a protected function are provided. A computer-implemented method may include storing a first virtual machine function instruction as the last instruction on the first trampoline page that is executable to configure access privileges according to a trampoline view, storing a page table setup instruction on the second trampoline page, and storing a second virtual machine function instruction as a last instruction on the second trampoline page that is executable to configure access privileges according to a protected view.
    Type: Grant
    Filed: January 14, 2015
    Date of Patent: March 20, 2018
    Assignee: Red Hat Israel, Ltd.
    Inventors: Michael Tsirkin, Paolo Bonzini
  • Patent number: 9910597
    Abstract: According to one embodiment, a memory system includes a non-volatile semiconductor memory, a block management unit, and a transcription unit. The semiconductor memory includes a plurality of blocks to which data can be written in both the first mode and the second mode. The block management unit manages a block that stores therein no valid data as a free block. When the number of free blocks managed by the block management unit is smaller than or equal to a predetermined threshold value, the transcription unit selects one or more used blocks that stores therein valid data as transcription source blocks and transcribes valid data stored in the transcription source blocks to free blocks in the second mode.
    Type: Grant
    Filed: December 27, 2016
    Date of Patent: March 6, 2018
    Assignee: TOSHIBA MEMORY CORPORATION
    Inventors: Hiroshi Yao, Shinichi Kanno, Kazuhiro Fukutomi
  • Patent number: 9904528
    Abstract: An approach to selecting statements for inlining in a COBOL program involving creating a PERFORM Graph (PG), determining whether the PG is a Directed Acyclic Graph (DAG), responsive to determining the PG is not a DAG, identifying a maximum sub-graph DAG corresponding to the PG, computing one or more infeasible paths associated with a Control Flow Graph (CFG), wherein the infeasible paths are induced by PERFORM range calls associated with a plurality of edges corresponding to the PG or the maximum sub-graph DAG, ordering the plurality of edges corresponding to the PG or the maximum sub-graph DAG in a list, selecting one or more edges, based on traversing the list of the plurality of edges and generating an indicator of the one or more selected edges.
    Type: Grant
    Filed: January 23, 2017
    Date of Patent: February 27, 2018
    Assignee: International Business Machines Corporation
    Inventors: Iain A. Ireland, Allan H. Kielstra, Artur Kink, Muntasir A. Mallick
  • Patent number: 9898297
    Abstract: A single chip sequential processor comprising at least one ALU-Block, where said sequential processor is capable of maintaining its op-codes while processing data such as to overcome the necessity of requiring a new instruction in every clock cycle.
    Type: Grant
    Filed: August 19, 2015
    Date of Patent: February 20, 2018
    Assignee: Hyperion Core, Inc.
    Inventors: Martin Vorbach, Frank May, Markus Weinhardt
  • Patent number: 9891284
    Abstract: This disclosure describes a reduced pin bus that can be used on integrated circuits or embedded cores within integrated circuits. The bus may be used for serial access to circuits where the availability of pins on ICs or terminals on cores is limited. The bus may be used for a variety of serial communication operations such as, but not limited to, serial communication related test, emulation, debug, and/or trace operations of an IC or core design. Other aspects of the disclosure include the use of reduced pin buses for emulation, debug, and trace operations and for functional operations. In a fifth aspect of the present disclosure, an interface select circuit, FIGS. 41-49, provides for selectively using either the 5 signal interface of FIG. 41 or the 3 signal interface of FIG. 8.
    Type: Grant
    Filed: February 6, 2017
    Date of Patent: February 13, 2018
    Assignee: Texas Instruments Incorporated
    Inventor: Lee D. Whetsel
  • Patent number: 9886373
    Abstract: More robust testing of computer module responses to processing errors using a flexible, lightweight solution that does not alter the computer module. Through modification of processing pointers, a wide variety of processing errors and delays are injected into a computer module without modifying the computer module.
    Type: Grant
    Filed: September 23, 2016
    Date of Patent: February 6, 2018
    Assignee: International Business Machines Corporation
    Inventors: Joseph A. Griesemer, Steven M. Partlow, David A. Stilwell
  • Patent number: 9880841
    Abstract: A computation method includes: obtaining one or more first performance values of one or more instructions in a specific code for each of a plurality of first combinations of behavior result of a cache memory when a plurality of accesses to a memory area are executed; obtaining a second combination of behavior result of the cache memory when the plurality of accesses are executed based on an execution result of behavior simulation of the cache memory for a case where a processor executes a program including the specific code; and computing, by a computer, a third performance value when the processor executes the specific code based on one or more second performance values of the one or more instructions corresponding to the second combination among the one or more first performance values when the second combination is included in the plurality of first combinations.
    Type: Grant
    Filed: November 6, 2014
    Date of Patent: January 30, 2018
    Assignee: FUJITSU LIMITED
    Inventor: Atsushi Ike
  • Patent number: 9870301
    Abstract: A processing device comprises a debug port controller to monitor operations of the processing device to determine whether the processing device is operating in a first mode or a second mode and to collect trace information comprising operating characteristics of the processing device. The processing device further comprises a display engine logic to process display data for output to a display device. In addition, the processing device comprises a display engine interface to provide, to a plurality of existing platform connectors, the display data from the display engine logic when the processing device is operating in the first primary mode and the trace information from the debug port controller when the processing device is operating in the second mode as determined by the debug port controller.
    Type: Grant
    Filed: March 31, 2014
    Date of Patent: January 16, 2018
    Assignee: Intel Corporation
    Inventors: Tsvika Kurts, Eilon Hazan, Sean T. Baartmans, Marcus R. Winston, Rony Ghattas, Arie Bernstein, Todd M. Witter, Marcelo Yuffe
  • Patent number: 9858189
    Abstract: Embodiments of the invention relate to tracking processor transactional read and write sets, thereby eliminating speculative mis-predictions. Both non-speculative read set and write set indications are maintained for a transaction. The indications are stored in cache. In addition, load and write queues of addresses are maintained. The load queue of addresses relates to speculative members of a read set and the write queue of addresses relates to speculating member of a write set. For a received read request, a transaction resolution process takes place, and a resolution is performed if an address match in the write queue is detected. Similarly, for a receive write request the transaction interference additionally checks the load queue and the non-speculative read set for the pending address.
    Type: Grant
    Filed: June 24, 2015
    Date of Patent: January 2, 2018
    Assignee: International Business Machines Corporation
    Inventors: Michael Karl Gschwind, Valentina Salapura, Chung-Lung K. Shum
  • Patent number: 9798645
    Abstract: An electronic tracing process includes packing both stall (215) and reason (219) data into a single high priority timing information stream. An integrated circuit includes an electronic processor (110), and a tracing circuit (120) operable to pack both stall and events data into a single timing information stream. Other circuits, processes and systems are also disclosed.
    Type: Grant
    Filed: November 10, 2015
    Date of Patent: October 24, 2017
    Assignee: Texas Instruments Incorporated
    Inventors: Kanika Ghai Bansal, Dipan Kumar Mandal, Gary A. Cooper, Bryan J. Thome
  • Patent number: 9791509
    Abstract: Embodiments of the present invention, which relate to the field of electronic technologies, provide a monitoring method, a monitoring apparatus, and an electronic device, which can accurately locate an error point in MPI information delivered by a system chip. The apparatus may include: an address filter, a read/write controller connected to the address filter, and a memory connected to the read/write controller, where the address filter is configured to acquire multiple pieces of MPI information, and obtain, by filtering the multiple pieces of MPI information, first MPI information corresponding to a first service that is preset; the read/write controller is configured to write, into the memory according to a time sequence of receiving the first MPI information, the first MPI information that is obtained by the address filter by filtering; and the memory is configured to store the first MPI information written by the read/write controller.
    Type: Grant
    Filed: April 29, 2015
    Date of Patent: October 17, 2017
    Assignee: Huawei Technologies Co., Ltd.
    Inventors: Shichun Zhong, Yanbin Luo
  • Patent number: 9753444
    Abstract: A control program execution unit, when a callee control program is called, stores a return address in a stack and stores input data for the callee control program in a data storage unit. An execution error information management unit, when an execution error occurs, acquires execution error information that includes the return address stored in the stack, the input data stored in the data storage unit, and a program name that corresponds to the return address and is obtained by using mapping information that indicates the storing positions of a control program and the callee control program in a user program storage unit.
    Type: Grant
    Filed: March 6, 2013
    Date of Patent: September 5, 2017
    Assignee: Mitsubishi Electric Corporation
    Inventor: Tetsushi Nakagawa
  • Patent number: 9740593
    Abstract: According to embodiments of the present invention, machines, systems, methods and computer program products for controlling two or more remote sessions are provided. Two or more remote sessions are synchronized to control each session using a common interface. One or more executable commands are sent to each remote session at substantially the same time using the common interface to control operation of that remote session. Data generated by each remote session from executing the commands is received and analyzed to identify one or more differences in data generated by each remote session. The one or more identified differences in the data are displayed on the common interface. An indication may be provided regarding possible root causes of the differences in the data generated by each remote session. Each remote session includes a program debug session. A report comprising the one or more identified differences in the data may be generated.
    Type: Grant
    Filed: January 8, 2015
    Date of Patent: August 22, 2017
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Alan S. Boxall, James T. Guan, Roger H. E. Pett, Trong Truong
  • Patent number: 9733946
    Abstract: A method comprises identifying a number of branches (Nb) and a number of iterations (Ni) in a loop in an instruction stream, generating a number of forward branches until the number of forward branches equals Nb, generating a non-branch instruction in between the forward branch instruction, recording in a memory, instruction stream generated and a history of each branch, an associated target address of each branch, and whether the branch is a taken branch or a not taken branch, determining whether a loop iterator number (i) is less than Ni?1, generating a backward branch with a target address which is greater than or equal to the start address and is lesser than the current address responsive to determining that (i) is less than Ni, and recording in the memory, a branch instruction of the generated backward branch and the associated target address of the backward branch.
    Type: Grant
    Filed: December 9, 2016
    Date of Patent: August 15, 2017
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Narasimha R. Adiga, Jatin Bhartia, Akash V. Giri, Matthias Heizmann
  • Patent number: 9727735
    Abstract: Methods and systems of simulating the effects of an attack seeking fraudulently to modify target code that is interpretable by a processor are disclosed. Various implementations may include means and operations for searching for a set of sensitive instructions in the target code; generating an interpretable “simulation” code having instructions representing the result of said attack on the set of instructions; selecting memory registers that might be accessed during the interpretation of the simulation code; interpreting at least a portion of the simulation code; and storing at least one value of the registers during the interpretation in order to enable the effects of the attack to be analyzed.
    Type: Grant
    Filed: April 25, 2014
    Date of Patent: August 8, 2017
    Assignee: OBERTHUR TECHNOLOGIES
    Inventor: Antoine Schweitzer
  • Patent number: 9720802
    Abstract: A stream of tuples is received to be processed by processing elements operating on one or more computer processors with each processing element having one or more stream operators. A breakpoint is identified for a stream operator that is configured to be triggered when time for processing of a tuple by the first stream operator is predicted to exceed a threshold time. A tuple is received at the stream operator having a set of attributes. A predicted time to process the tuple is determined based on the set of attributes. It is determined that the predicted time exceeds the threshold time. The breakpoint is triggered, in response to determining that the predicted time exceeds the threshold time, to pause processing of the tuple by the first stream operator.
    Type: Grant
    Filed: October 25, 2016
    Date of Patent: August 1, 2017
    Assignee: International Business Machines Corporation
    Inventors: Eric L. Barsness, Michael J. Branson, John M. Santosuosso
  • Patent number: 9720797
    Abstract: The present application relates to a flash memory controller and a method of operating thereof. A system bus interface is provided to interface with a system bus and a debug bus interface is provided to interface with a debug bus. A flash access control block is provided to perform storage I/O operations on a flash memory array. A debug control block is provided to monitor debug related information. The flash memory controller is configured to selectively operate in one or storage operating mode or debug operating mode. In the debug operating mode: the storage control block is configured to serve only read data access requests; and the debug control block is configured to store trace messages in an allocated part of the storage resources of the flash memory controller in response to trace events. The trace messages are generated on the basis of the monitored debug related information.
    Type: Grant
    Filed: June 30, 2015
    Date of Patent: August 1, 2017
    Assignee: NXP USA, Inc.
    Inventors: Damon Peter Broderick, Dirk Heisswolf, Andreas Ralph Pachl
  • Patent number: 9720756
    Abstract: A computing system includes: a volatile memory configured to: store a debug assert flag mask including bits; cores, coupled to the volatile memory, configured to: detect an error in at least one of the cores, set at least one of the bits corresponding to the cores with the error detected, collect debug information for each of the cores with the error detected, collect operating information for each of the cores without the error detected, generate assert dump information based on compiling the debug information; and a nonvolatile memory, coupled to at least one of the cores, configured to: store the assert dump information, the operating information, configured to by at least one of the cores.
    Type: Grant
    Filed: October 23, 2015
    Date of Patent: August 1, 2017
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Alexei Frolikov, Hwan Kim, Yangsup Lee
  • Patent number: 9710387
    Abstract: A method for translating instructions for a processor. The method includes accessing a plurality of guest instructions that comprise multiple guest branch instructions, and assembling the plurality of guest instructions into a guest instruction block. The guest instruction block is converted into a corresponding native conversion block. The native conversion block is stored into a native cache. A mapping of the guest instruction block to corresponding native conversion block is stored in a conversion look aside buffer. Upon a subsequent request for a guest instruction, the conversion look aside buffer is indexed to determine whether a hit occurred, wherein the mapping indicates whether the guest instruction has a corresponding converted native instruction in the native cache. The converted native instruction is forwarded for execution in response to the hit.
    Type: Grant
    Filed: January 27, 2012
    Date of Patent: July 18, 2017
    Assignee: INTEL CORPORATION
    Inventor: Mohammad Abdallah
  • Patent number: 9684585
    Abstract: More robust testing of computer module responses to processing errors using a flexible, lightweight solution that does not alter the computer module. Through modification of processing pointers, a wide variety of processing errors and delays are injected into a computer module without modifying the computer module.
    Type: Grant
    Filed: November 4, 2016
    Date of Patent: June 20, 2017
    Assignee: International Business Machines Corporation
    Inventors: Joseph A. Griesemer, Steven M. Partlow, David A. Stilwell
  • Patent number: 9684599
    Abstract: Embodiments of the invention relate to tracking processor transactional read and write sets, thereby eliminating speculative mis-predictions. Both non-speculative read set and write set indications are maintained for a transaction. The indications are stored in cache. In addition, load and write queues of addresses are maintained. The load queue of addresses relates to speculative members of a read set and the write queue of addresses relates to speculating member of a write set. For a received read request, a transaction resolution process takes place, and a resolution is performed if an address match in the write queue is detected. Similarly, for a receive write request the transaction interference additionally checks the load queue and the non-speculative read set for the pending address.
    Type: Grant
    Filed: August 20, 2015
    Date of Patent: June 20, 2017
    Assignee: International Business Machines Corporation
    Inventors: Michael Karl Gschwind, Valentina Salapura, Chung-Lung K. Shum
  • Patent number: 9684605
    Abstract: Embodiments of an invention for a guest-physical address translation lookaside buffer are disclosed. In an embodiment, a processor includes an instruction decoder, a control register, and memory address translation hardware. The instruction decoder is to receive an instruction to transfer control of the processor to guest software to execute on a virtual machine. The virtual machine is to have a plurality of resources to be controlled by a virtual machine monitor. The virtual machine monitor is to execute on a host machine having a host-physical memory to be accessed using a plurality of host-physical addresses. The plurality of resources is to include a guest-physical memory. The guest software is to access the guest-physical memory using a plurality of guest-virtual addresses. The control register is to store a pointer to a plurality of virtual address page tables.
    Type: Grant
    Filed: February 23, 2015
    Date of Patent: June 20, 2017
    Assignee: Intel Corporation
    Inventors: Vedvyas Shanbhogue, Christopher Bryant
  • Patent number: 9678157
    Abstract: The disclosure describes a novel method and apparatuses for allowing a controller to select and access different types of access ports in a device. The selecting and accessing of the access ports is achieved using only the dedicated TDI, TMS, TCK, and TDO signal terminals of the device. The selecting and accessing of device access ports can be achieved when a single device is connected to the controller, when multiple devices are placed in a daisy-chain arrangement and connected to the controller, or when multiple devices are placed in a addressable parallel arrangement and connected to the controller. Additional embodiments are also provided and described in the disclosure.
    Type: Grant
    Filed: June 6, 2016
    Date of Patent: June 13, 2017
    Assignee: Texas Instruments Incorporated
    Inventor: Lee D. Whetsel
  • Patent number: 9665461
    Abstract: A system for obtaining performance data for different performance events includes a first application monitoring performance of a second application executing on a computing system. The first application identifies the type of event to be measured with respect to the second application, issues a first system call identifying the type of event, receives an identifier corresponding to the event type, and causes the second application to begin execution. After the execution of the second application is completed, the first application issues a second system call including the identifier corresponding to the event type, and receives a value of a hardware counter corresponding to the event type from an operating system.
    Type: Grant
    Filed: December 4, 2009
    Date of Patent: May 30, 2017
    Assignee: Red Hat, Inc.
    Inventors: Ingo Molnar, Thomas Gleixner
  • Patent number: 9645911
    Abstract: A method for debugging firmware/software by generating trace data includes the following steps: running a debug module in a power-on stage in a test system, to record a load address and a branch instruction execution record set of a tested module into an area for temporary storage; accessing, by an analyzer, in an operating system stage in the area for temporary storage, the load address and the branch instruction execution record set and accessing a program debug symbol table, where the program debug symbol table is generated when source program code is compiled; and finding, by the analyzer, an original source file, a function name, and line numbers of executed codes from the program debug symbol table according to the load address and the branch instruction execution record set to generate an analysis report that includes a program execution path and a program code coverage.
    Type: Grant
    Filed: October 16, 2015
    Date of Patent: May 9, 2017
    Assignee: INSYDE SOFTWARE CORPORATION
    Inventor: Ying Chin Cheng
  • Patent number: 9647691
    Abstract: An apparatus comprising: a lower-layer decoder configured to decode a data stream formatted according to a lower-layer protocol that interleaves portions of a first data stream and one or more additional data streams to produce separated data streams comprising the first data stream and separately the one or more additional data streams; and a higher-layer decoder configured to decode the first data stream formatted according to a higher-layer protocol to produce trace data, the higher-layer decoder comprising: synchronization logic configured to process the first data stream to detect a data pattern within the first data stream as a synchronization event; and decoding logic configured to use the synchronization event to synchronize decoding of the received first data stream to produce the trace data.
    Type: Grant
    Filed: December 9, 2014
    Date of Patent: May 9, 2017
    Assignee: NXP USA, INC.
    Inventors: Radu-Marian Ivan, Razvan Lucian Ionescu, Mihai Udvuleanu, Ionut-Valentin Vicovan
  • Patent number: 9632907
    Abstract: A processing device implementing tracking of deferred data packets in a debug trace architecture is disclosed. The processing device is to determine an order number corresponding to an order in which an instruction was executed relative to other executed instructions that correspond to an instruction type within a sequence of executed instructions, identify a first data packet corresponding to a first packet type and sequentially ordered, according to the order number, with respect to data packets of the first packet type within a data trace log, identify a second data packet corresponding to a second packet type and sequentially ordered, according to the order number, with respect to data packets of the second packet type within the data trace log, and map the identified first and second data packets to the instruction, wherein at least one of the first or second data packets was generated post-retirement of the instruction.
    Type: Grant
    Filed: December 10, 2014
    Date of Patent: April 25, 2017
    Assignee: Intel Corporation
    Inventors: Beeman C. Strong, Stephen J. Robinson, Jason W. Brandt, Peter Lachner
  • Patent number: 9626279
    Abstract: A method and information processing system provide trace compression for trace messages. In response to a branch of a conditional branch instruction having not been taken or having been taken, a flag of a history buffer is set or cleared. A trace address message is generated in response to a conditional indirect branch instruction being taken, wherein the trace address message includes address information indicating the destination address of the taken branch, and an index value indicating a corresponding flag of the history buffer. In response to a return from interrupt or return from exception instruction, a predicted return address is compared to an actual return address. A trace address message is generated in response to the predicted and actual return addresses not matching. A trace address message is not generated in response to the predicted and actual return addresses matching.
    Type: Grant
    Filed: July 1, 2013
    Date of Patent: April 18, 2017
    Assignee: NXP USA, INC.
    Inventors: Robert A. McGowan, Robert N. Ehrlich
  • Patent number: 9619364
    Abstract: A method for analyzing race conditions between multiple threads of an application is disclosed. The method comprises accessing hazard records for an application under test. It further comprises creating a graph comprising a plurality of vertices and a plurality of edges using the hazard records, wherein each vertex of the graph comprises information about a code location of a hazard and wherein each edge of the graph comprises hazard information between one or more vertices. Additionally, it comprises assigning each edge with a weight, wherein the weight depends on a number and relative priority of hazards associated with a respective edge. Finally, it comprises traversing the graph to report an analysis record for each hazard represented in the graph.
    Type: Grant
    Filed: August 28, 2013
    Date of Patent: April 11, 2017
    Assignee: NVIDIA CORPORATION
    Inventor: Vyas Venkataraman
  • Patent number: 9612837
    Abstract: An information processing apparatus includes a rewriting unit and an execution unit. The rewriting unit rewrites a first instruction described at a trace point in a function defined in a program to a second instruction which gives instructions to execute a trace code, and stores the first instruction in a storage unit. The execution unit executes the trace code on the basis of the second instruction at the time of execution at the trace point in the function. If a third instruction which calls the function is included in the trace code, the execution unit replaces, at the time of executing the third instruction, the second instruction at the trace point in the function with the first instruction stored in the storage unit, and performs the function.
    Type: Grant
    Filed: September 11, 2014
    Date of Patent: April 4, 2017
    Assignee: FUJITSU LIMITED
    Inventors: Takashi Nakagawa, Yasutoshi Suzuki, Hiroyuki Yamamoto, Kazuhide Imaeda
  • Patent number: 9606820
    Abstract: A replay core ensures that references to objects are removed at the same relative times and in the same relative order within a program's execution during both record time and replay time. A register method of a Finalizer class is modified to cause the register method to pass, to a specified programmatic mechanism, an object that was passed to the register method; modifying a finalize method of a class of the object to (a) cause the object to invoke a first method of the programmatic mechanism when the finalize method is invoked by a virtual machine and (b) prevent a remainder of the finalize method from completing under specified conditions, thereby causing a call to the finalize method to remain undispatched. The first method, when invoked, (a) adds, to the object, a reference that temporarily prevents the object from being deleted and (b) records an identifier of the object.
    Type: Grant
    Filed: April 22, 2014
    Date of Patent: March 28, 2017
    Assignee: CA, Inc.
    Inventors: Jeffrey Daudel, Suman Cherukuri, Humberto Yeverino, Dickey Singh, Arpad Jakab, Marvin Justice, Jonathan Lindo