Specialized Instruction Processing In Support Of Testing, Debugging, Emulation Patents (Class 712/227)
  • Patent number: 10606498
    Abstract: A method for managing a discontinuous call stack is disclosed to more efficiently use the memory of devices without a memory management unit.
    Type: Grant
    Filed: December 23, 2016
    Date of Patent: March 31, 2020
    Assignee: Arm IP Limited
    Inventors: James Crosby, Brendan James Moran
  • Patent number: 10585668
    Abstract: A process for processor testing includes generating a set of test instructions having a first portion and a second portion. A first branch instruction is randomly generated for the first portion where the first branch instruction branches to a respective instruction in a second portion by a branching location offset. A second branch instruction is randomly generated for the second portion where the second branch instruction branches to a respective instruction in the first portion by the branching location offset. If additional instructions are to be added to the set of test instructions, a value of the branching location offset is incrementing by a predetermined amount.
    Type: Grant
    Filed: October 2, 2017
    Date of Patent: March 10, 2020
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Abhishek Bansal, Nitin P. Gupta, Brad L. Herold, Jayakumar N. Sankarannair
  • Patent number: 10572233
    Abstract: Provided is a vectorization device 30 comprising: a unit 31 that detects a configuration in which the inner loop length depends on the outer loop variable, and in which a first array indicating the results of dual-loop processing does not contain the inner loop variable as an index value; an unit 32 that, when the configuration is detected, determines a fixed value as the inner loop length; an unit 33 that expands the array size of a second array used in the calculation of the first array value, and thereby enables dual-loop processing of the inner loop; an unit 34 that sets an element value for an added element of the second array, and thereby, before and after such processing is carried out, enables the results of the dual-loop processing to be made equal; and an unit 35 that updates the software on the basis of such processing results.
    Type: Grant
    Filed: November 17, 2016
    Date of Patent: February 25, 2020
    Assignee: NEC CORPORATION
    Inventor: Yoshiyuki Ohno
  • Patent number: 10564962
    Abstract: An electronic circuit (4000) includes a bias value generator circuit (3900) operable to supply a varying bias value in a programmable range, and an instruction circuit (3625, 4010) responsive to a first instruction to program the range of the bias value generator circuit (3900) and further responsive to a second instruction having an operand to repeatedly issue the second instruction with the operand varied in an operand value range determined as a function of the varying bias value.
    Type: Grant
    Filed: November 19, 2018
    Date of Patent: February 18, 2020
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Kenichi Tashiro, Hiroyuki Mizuno, Yuji Umemoto
  • Patent number: 10558806
    Abstract: A processor receives a signal and determines whether an application has registered a signal handler therewith for handling the signal. In response to determining that the application has registered the signal handler, the processor transmits the signal directly to the signal handler of the application for handling the signal, without an operating system in relation to which the trusted application is running intervening. In response to determining that the trusted application has not registered the signal handler, the processor transmits the signal to a signal handler of the operating system for handling the signal.
    Type: Grant
    Filed: December 13, 2016
    Date of Patent: February 11, 2020
    Assignee: International Business Machines Corporation
    Inventors: Andrew D. Hilton, Brian M. Rogers
  • Patent number: 10509906
    Abstract: In an example embodiment, a system determines a set of instructions from the available instructions for a computer application. The determined set of instructions provides specific functionality of the computer application. The system may determine the set of instructions by performing functional testing and negative testing on the specific functionality. The system may reorganize and randomize the set of instructions in memory and write the reorganized set of instructions to a smaller memory space. For each available instruction not in the set of instructions, the system changes the respective instruction to inoperative to prevent execution of the respective instruction. The system may change the respective instruction to inoperative by overwriting the instruction with a NOP instruction. The system then captures a memory address of the computer application being accessed at runtime.
    Type: Grant
    Filed: July 10, 2017
    Date of Patent: December 17, 2019
    Assignee: Virsec Systems, Inc.
    Inventor: Satya Vrat Gupta
  • Patent number: 10503479
    Abstract: Examining source code repositories for indications of orthogonal technologies in actual use or of potential usefulness in the development and continuous delivery of the contents of the repositories.
    Type: Grant
    Filed: May 7, 2018
    Date of Patent: December 10, 2019
    Assignee: International Business Machines Corporation
    Inventors: Christopher Brealey, Christopher Taylor, Joel Cayne, Philippe Mulet, Ritchard L. Schacher, Thomas C. Schmidt
  • Patent number: 10496405
    Abstract: Embodiments of the present invention are directed to a computer-implemented method for generating and verifying hardware instruction traces including memory data contents. The method includes initiating an in-memory trace (IMT) data capture for a processor, the IMT data being an instruction trace collected while instructions flow through an execution pipeline of the processor. The method further includes capturing contents of architected registers of the processor by: storing the contents of the architected registers to a predetermined memory location, and causing a load-store unit (LSU) to read contents of the predetermined memory location.
    Type: Grant
    Filed: November 20, 2017
    Date of Patent: December 3, 2019
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Jane H. Bartik, Christian Jacobi, David Lee, Jang-Soo Lee, Anthony Saporito, Christian Zoellin
  • Patent number: 10484361
    Abstract: In accordance with disclosed embodiments, there are provided systems, methods, and apparatuses for implementing virtual device observation and debug network for high speed serial IOS.
    Type: Grant
    Filed: June 30, 2016
    Date of Patent: November 19, 2019
    Assignee: Intel Corporation
    Inventors: Lakshminarayana Pappu, Timothy J. Callahan, Baruch Schnarch, Hem Doshi, Suketu U. Bhatt
  • Patent number: 10467114
    Abstract: A hierarchical data processor test system (and method) is usable to configure a hierarchical plurality of similarity operators and process predetermined input test data through a data processor under test (DPUT) to produce corresponding DPUT output data. The test system is further usable to process the DPUT output data and the predetermined output test data through at least some of the plurality of similarity operators in hierarchical order, determine a highest order similarity operator that indicates a match between the DPUT output data and the predetermined output test data, and compute a confidence score based on the highest order similarity operator that indicated the match. Based on the confidence score exceeding a threshold, the test system also may include activating the DPUT for use by non-test data.
    Type: Grant
    Filed: July 14, 2016
    Date of Patent: November 5, 2019
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Neil S. Bhargava, Freddys M. Espinoza, Stefan A. Gert Van Der Stockt
  • Patent number: 10445133
    Abstract: A method for managing thread execution in a processing system is provided. The method includes setting a first watchpoint, and generating a first watchpoint trigger corresponding to the first watchpoint. In response to the first watchpoint trigger, execution of a first thread is controlled in accordance with a value stored in a first control register. Controlling the first thread may further include disabling execution of the first thread. The disabling execution of the first thread may occur within the first watchpoint region.
    Type: Grant
    Filed: March 4, 2016
    Date of Patent: October 15, 2019
    Assignee: NXP USA, Inc.
    Inventors: Jonathan J. Gamoneda, Jehoda Refaeli, Jeffrey W. Scott
  • Patent number: 10423778
    Abstract: Described herein are techniques for dealing with the problem of security vulnerabilities in computer software due to undefined behavior that may be exploited by attackers. A way of dealing with this problem is to remove an essential capability for most advanced attacks, Turing completeness. That is, a piece of software is provided the ability to specify that it does not need Turing completeness (i.e., backward computation) in order to perform a given task such as parsing. During this stage, attackers are prevented from abusing the system by performing, for example, return oriented programming.
    Type: Grant
    Filed: December 29, 2016
    Date of Patent: September 24, 2019
    Assignee: Intel Corporation
    Inventor: Rodrigo R. Branco
  • Patent number: 10423474
    Abstract: Arrangements described herein relate to performing diagnostic tracing of an executing application. A trace entry in trace data can be identified, the trace entry comprising a pointer that refers to a memory address. Whether a value that is, or has been, stored at the memory address is an erroneous value can be determined. Responsive to determining that the value that is, or has been, stored at the memory address is an erroneous value, the pointer can be indicated as being a suspicious value.
    Type: Grant
    Filed: July 29, 2015
    Date of Patent: September 24, 2019
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Stephen John Burghard, David J. Harman, Neil W. Leedham, Andrew Wright
  • Patent number: 10387191
    Abstract: A task processor includes a CPU, a save circuit, and a task control circuit. A task control circuit is provided with a task selection circuit and state storage units associated with respective tasks. When executing a predetermined system call instruction, the CPU notifies the task control circuit accordingly. When informed of the execution of a system call instruction, the task control circuit selects a task to be subsequently executed in accordance with an output from the selection circuit. When an interrupt circuit receives a high-speed interrupt request signal, the task switching circuit controls the state transition of a task by executing an interrupt handling instruction designated by the interrupt circuit.
    Type: Grant
    Filed: August 22, 2017
    Date of Patent: August 20, 2019
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventor: Naotaka Maruyama
  • Patent number: 10379998
    Abstract: According to one or more embodiments a computer-implemented method includes detecting, by a processor, an instruction to capture runtime data of a set of instructions in a computer program, the instruction detected based on a hook associated with the set of instructions. The method further includes determining whether the hook is an active expiring hook. The method further includes in response to the hook being an active expiring hook, determining a time condition associated with the expiring hook. The method further includes in response to the time condition being met, capturing the runtime data of the set of instructions in the computer program.
    Type: Grant
    Filed: November 6, 2017
    Date of Patent: August 13, 2019
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Francisco M. Anaya, Seana Hogan, Trong Truong
  • Patent number: 10379997
    Abstract: According to one or more embodiments a computer-implemented method includes detecting, by a processor, an instruction to capture runtime data of a set of instructions in a computer program, the instruction detected based on a hook associated with the set of instructions. The method further includes determining whether the hook is an active expiring hook. The method further includes in response to the hook being an active expiring hook, determining a time condition associated with the expiring hook. The method further includes in response to the time condition being met, capturing the runtime data of the set of instructions in the computer program.
    Type: Grant
    Filed: September 19, 2017
    Date of Patent: August 13, 2019
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Francisco M. Anaya, Seana Hogan, Trong Truong
  • Patent number: 10338135
    Abstract: Methods and apparatus are disclosed for programming reconfigurable logic devices such as FPGAs in a multi-tenant server environment. In one example, a computing host includes one or more processors configured to execute a supervisor process and two or more user processes and a single FPGA integrated circuit configured into a plurality of partitions. The partitions include a host logic partition that is accessible only to the supervisor process executing on the computing host, and two or more accelerator partitions. Each of the accelerator partitions is configured to include a virtual debug unit with a logic analyzer that collects logic signals generated by logic within the respective accelerator partition and sends debug data indicating values of the logic signals to one of the user processes. In some examples, the host logic partitions and/or the accelerator partitions can be independently reprogrammed of each other within their respective portions of the single FPGA.
    Type: Grant
    Filed: September 28, 2016
    Date of Patent: July 2, 2019
    Assignee: Amazon Technologies, Inc.
    Inventors: Mark Bradley Davis, Christopher Joseph Pettey, Asif Khan, Islam Mohamed Hatem Abdulfattah Mohamed Atta
  • Patent number: 10339229
    Abstract: Aspects of the present invention describe a system and method for providing a single integrated simulation interface running in a single host operating system (OS) thread to observe and control multiple, disparate software and hardware components. Control mechanisms of the present invention provide access to each of the modeled components, including the hardware models, the embedded software components modeled on the bare-hardware elements, and the software applications, processes and threads which are themselves running on embedded software.
    Type: Grant
    Filed: May 31, 2013
    Date of Patent: July 2, 2019
    Assignee: CADENCE DESIGN SYSTEMS, INC.
    Inventors: Andrew Wilmot, William W. LaRue, Jr., Neeti Bhatnagar, Dave Von Bank, Joshua Levine
  • Patent number: 10331452
    Abstract: In accordance with embodiments disclosed herein, there is provided systems and methods for tracking the mode of processing devices in an instruction tracing system. The method may include receiving an indication of a change in a current execution mode of the processing device. The method may also include determining that the current execution mode of the received indication is different than a value of an execution mode of a first execution mode (EM) packet previously-generated by the IT module. The method may also include generating, based on the determining that the current execution mode is different, a second EM packet that provides a value of the current execution mode of the processing device to indicate the change in the execution mode for an instruction in a trace generated by the IT module. The method may further include generating transactional memory (TMX) packets having n bit mode pattern in the packet log. The n is at least two and the n bit mode indicates transaction status of the TMX operation.
    Type: Grant
    Filed: June 27, 2013
    Date of Patent: June 25, 2019
    Assignee: Intel Corporation
    Inventors: Thilo Schmitt, Peter Lachner, Beeman Strong, Ofer Levy, Thomas Toll, Matthew Merten, Tong Li, Ravi Rajwar, Konrad Lai
  • Patent number: 10318356
    Abstract: Operation of a multi-slice processor that includes execution slices and a dispatch network of the multi-slice processor implementing a hardware level transfer of an execution thread between execution slices. Operation of such a multi-slice processor includes responsive to a thread switch signal: halting dispatch of one or more instructions retrieved from an instruction cache; generating a plurality of instructions to transfer an execution thread from a first execution slice to a second execution slice; and dispatching the plurality of instructions instead of the one or more instructions retrieved from the instruction cache; and transferring, in dependence upon execution of the plurality of instructions from the thread switching instruction generator, the execution thread from the first execution slice to the second execution slice.
    Type: Grant
    Filed: March 31, 2016
    Date of Patent: June 11, 2019
    Assignee: International Business Machines Corporation
    Inventors: Brian D. Barrick, James W. Bishop, Marcy E. Byers, Sundeep Chadha, Cliff Kucharski, Dung Q. Nguyen, David R. Terry, Jing Zhang
  • Patent number: 10319455
    Abstract: A semiconductor device includes a delay selection signal generation circuit, an internal read signal generation circuit, and an internal write signal generation circuit. The delay selection signal generation circuit generates a delay selection signal in response to an information code signal. The internal read signal generation circuit generates an internal read signal from a mask write signal in response to the delay selection signal and a clock. The internal write signal generation circuit delays the mask write signal by a predetermined delay period to generate an internal write signal.
    Type: Grant
    Filed: July 3, 2017
    Date of Patent: June 11, 2019
    Assignee: SK HYNIX INC.
    Inventors: Yong Mi Kim, Jae Il Kim
  • Patent number: 10318790
    Abstract: Techniques relate to fingerprint-based processor malfunction detection. A determination is made whether a fingerprint is present in software that is currently executing on the processor of the computer system. The fingerprint includes a representation of a sequence of behavior that occurs on the processor while the software is executing. The fingerprint corresponds to a type of malfunction. In response to determining that the fingerprint is not present in the software currently executing on the processor, monitoring of the software executing on the processor to determine whether the fingerprint is present continues. In response to determining that the fingerprint is present in the software executing on the processor, it is determined that the malfunction has occurred according to a type of the fingerprint that is present.
    Type: Grant
    Filed: December 14, 2016
    Date of Patent: June 11, 2019
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Giles R. Frazier, Michael Karl Gschwind, Christian Jacobi, Anthony Saporito, Chung-Lung K. Shum
  • Patent number: 10310862
    Abstract: Data processing circuitry comprises out-of-order instruction execution circuitry to execute program instructions in an instruction execution order; a data store, to store information on a set of instructions for which execution has been initiated, the data store providing ordering information indicating the relative position of each instruction in the set of instructions with respect to a program code order; commit circuitry to commit the results of instructions executed by the instruction execution circuitry; one or more cumulative status registers configured to be set in response to a respective condition generated by execution of an instruction and then to remain set until an unset instruction is executed; and an identifier store, to store for at least those of the one or more cumulative status registers which are not currently set, an identifier of an instruction which is earliest in the program code order in the set of instructions and which generated a condition to set that cumulative status register.
    Type: Grant
    Filed: March 21, 2017
    Date of Patent: June 4, 2019
    Assignee: ARM Limited
    Inventors: Robert Greg McDonald, Michael Filippo, Glen Andrew Harris
  • Patent number: 10305919
    Abstract: In accordance with some embodiments of the present invention, systems and methods that protect an application from attacks are provided. In some embodiments of the present invention, input from an input source, such as traffic from a communication network, can be routed through a filtering proxy that includes one or more filters, classifiers, and/or detectors. In response to the input passing through the filtering proxy to the application, a supervision framework monitors the input for attacks (e.g., code injection attacks). The supervision framework can provide feedback to tune the components of the filtering proxy.
    Type: Grant
    Filed: May 9, 2016
    Date of Patent: May 28, 2019
    Assignee: The Trustees of Columbia University in the City of New York
    Inventors: Michael E. Locasto, Salvatore J. Stolfo, Angelos D. Keromytis, Ke Wang
  • Patent number: 10296476
    Abstract: A method of profiling transactions on an integrated circuit chip. The method comprises, for each transaction: extracting the transaction from interconnect circuitry of the integrated circuit chip; and filtering the transaction at a filtering circuit to determine which passband a parameter of the transaction lies within; sending an increment signal to a counter of a bank of counters, the counter having a counter value indicative of a number of transactions having the parameter lying within the passband; and outputting the counter values of the bank of counters.
    Type: Grant
    Filed: August 12, 2016
    Date of Patent: May 21, 2019
    Assignee: UltraSoC Technologies Limited
    Inventors: Andrew Brian Thomas Hopkins, Michael Jonathan Thyer, Iain Craig Robertson
  • Patent number: 10289411
    Abstract: A debugging and diagnostics system allow for dynamic code generation that inserts code into a production application to identify snappoints or breakpoints that cause snapshots to be taken if predefined conditionals are satisfied. The snappoints are associated with locations in source code for the production application and include conditional statements that must be met to create a snapshot of the production application. The snappoints are used to generate a collection plan that is provided to the server running the production application. The server rewrites the code of the production application based upon the collection plan to insert instructions that create snapshots when the conditional statements are met.
    Type: Grant
    Filed: November 18, 2013
    Date of Patent: May 14, 2019
    Assignee: Microsoft Technology Licensing, LLC
    Inventor: Jackson Davis
  • Patent number: 10282276
    Abstract: Techniques relate to fingerprint-initiated trace extraction. A determination is made of whether a fingerprint is present in software that is currently executing on a processor of a computer system. The fingerprint comprises a representation of a sequence of behavior that occurs in the processor while the software is executing. In response to determining that the fingerprint is not present in the software currently executing on the processor, monitoring continues for the software executing on the processor to determine whether the fingerprint is present. In response to determining that the fingerprint is present in the software executing on the processor, a trace is triggered of a code segment of the software corresponding to when the fingerprint is recognized. The trace is for a record of instructions of the code segment of the software.
    Type: Grant
    Filed: January 16, 2017
    Date of Patent: May 7, 2019
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Jonathan D. Bradbury, Giles R. Frazier, Michael Karl Gschwind, Christian Jacobi, Anthony Saporito, Chung-Lung K. Shum
  • Patent number: 10277246
    Abstract: The present invention provides a program counter compression method and a hardware circuit thereof. The compression method of the present invention includes the following steps: step (1), acquiring execution condition of instructions sent by a processor and classifying and screening said instructions based on said execution condition of the instructions; step (2), executing differential operation on instruction count values of the objective classification and the stall periods based on the classifying and screening result and splicing the obtained differential values; step (3), dictionary encoding the valid differential slicing data segments recorded in step (2). The present invention effectively combines the architecture compression and non-architecture compression and proposes a three-stage compression scheme by organizing and applying classifying and screening, differential encoding and dictionary compression, which drastically increases the compression ratio of the program counter.
    Type: Grant
    Filed: February 17, 2017
    Date of Patent: April 30, 2019
    Assignee: HEFEI UNIVERSITY OF TECHNOLOGY
    Inventors: Duoli Zhang, Bin Zhang, Yukun Song, Can Wei
  • Patent number: 10275242
    Abstract: An apparatus and method are described for real time instruction tracing. For example, a method according to one embodiment comprises: recording user specified address ranges for which tracing is required; monitoring a next linear instruction pointer (NLIP) values and/or branch linear instruction pointer (BLIP) values to determine if address range has been entered; when the range is entered, compressing the NLIP and/or BLIP values and constructing fixed length packets containing the tracing data; and transferring the fixed length packets to a memory execution cluster.
    Type: Grant
    Filed: March 30, 2012
    Date of Patent: April 30, 2019
    Assignee: Intel Corporation
    Inventors: Huy V. Nguyen, Jason W. Brandt, Jonathan J. Tyler
  • Patent number: 10275335
    Abstract: Described is a computer-implemented method of reordering condition checks. Two or more condition checks in computer code that may be reordered within the code are identified. It is determined that the execution frequency of a later one of the condition checks is satisfied at a greater frequency than a preceding one of the condition checks. It is determined that there is an absence of side effects in the two or more condition checks. The values of the condition checks are propagated and abstract interpretation is performed on the values that are propagated. It is determined that the condition checks are exclusive of each other, and the condition checks are reordered within the computer code.
    Type: Grant
    Filed: September 15, 2017
    Date of Patent: April 30, 2019
    Assignee: International Business Machines Corporation
    Inventors: Takuya Nakaike, Takeshi Ogasawara
  • Patent number: 10192049
    Abstract: Systems, methods, and media for detecting the presence of return-oriented programming (ROP) payloads are provided, comprising: identifying a potential gadget address space; determining if a piece of the data corresponds to an address of the potential gadget address space; and in response to determining that the piece of the data corresponds to an address of the potential gadget address space: determining whether a plurality of operations, each associated one of a plurality instructions beginning at the address, indicates that an ROP payload is present in the data, and indicating that an ROP payload is present in the data in response to making a determination that a plurality of operations indicates that an ROP payload is present in the data a given number of times.
    Type: Grant
    Filed: November 11, 2016
    Date of Patent: January 29, 2019
    Assignee: The Trustees of Columbia University in the City of New York
    Inventors: Michalis Polychronakis, Angelos D. Keromytis
  • Patent number: 10176077
    Abstract: A computer implemented method for selecting breakpoints for cross-layer debugging is provided. The method includes receiving code comprising a plurality of layers, and executing a static analysis of the code to obtain a use-definition (UD) chain, alias information, and a parameter mapping for each of the plurality of layers. The method also includes determining a statement of the code that produces one of an error and a failure, and generating a table comprising a plurality of fields including a working statement field, watching variable field, and a watching function field. The method includes adding the determined statement to the working statement field and performing a cross-layer analysis includes identifying at least one used variable and its associated alias as watching variables from the added working statement, searching the code based on the watching variable field. The method includes generating cross-layer suspect code points based on the cross-layer analysis.
    Type: Grant
    Filed: February 16, 2017
    Date of Patent: January 8, 2019
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Si Bin Fan, Xiao Feng Guan, Chen Jiang, Yan Rong Shen, Chang Ning Song, Ping Xiao
  • Patent number: 10169194
    Abstract: Systems, methods and tools for identifying potential errors or inconsistencies occurring during the runtime of multi-threaded applications and reporting the errors to a user, administrator or developer for correction and adjustments to the program code or thread timings. Embodiments of the disclosure capture thread sequences during a runtime or simulation environment and store the thread sequences as a matrix or tabular representation in a file. Multi-threaded application runs having an error free thread sequence, may be used as benchmarks for identifying potential errors and mis-runs of variations to the multi-threaded application as changes occur to the application code or new threads are added to the application code. This comparison may be performed by comparing the captured thread sequences of both the passing run and the mis-run of the multi-threaded application for differences in the thread sequences that may have caused the mis-run to occur.
    Type: Grant
    Filed: March 22, 2017
    Date of Patent: January 1, 2019
    Assignee: International Business Machines Corporation
    Inventors: Vikas Chandra, Srinivasan S. Muthuswamy, Sarika Sinha
  • Patent number: 10162635
    Abstract: An apparatus includes a network interface, memory, and a processor. The processor is coupled with the network interface and memory. The processor is configured to determine that an instruction instance is a branch instruction instance. Responsive to a determination that an instruction instance is a branch instruction instance, the processor is configured to obtain a branch prediction for the branch instruction instance and a confidence value of the branch prediction. The processor is further configured to determine that the confidence for the branch prediction is low based on the confidence value, and responsive to such a determination, generate predicated instruction instances based on the branch instruction instance.
    Type: Grant
    Filed: May 17, 2016
    Date of Patent: December 25, 2018
    Assignee: International Business Machines Corporation
    Inventor: Michael Karl Gschwind
  • Patent number: 10152406
    Abstract: According to an aspect of an embodiment, one or more systems or methods may be configured to locate a fault in a software program using a test suite. The systems or methods may be further configured to modify, using a repair template, the software program in response to locating the fault. In addition, the systems or methods may be configured to determine whether the modification satisfies an anti-pattern condition. The anti-pattern condition may indicate whether the modification is improper. The systems or methods may also be configured to disallow the modification in response to the modification satisfying the anti-pattern condition or perform further testing on the software program, as modified, in response to the modification not satisfying the anti-pattern condition.
    Type: Grant
    Filed: August 25, 2015
    Date of Patent: December 11, 2018
    Assignee: FUJISTU LIMITED
    Inventors: Hiroaki Yoshida, Shin Hwei Tan, Mukul R. Prasad
  • Patent number: 10146607
    Abstract: The techniques described herein provides troubleshooting, monitoring, reporting and dynamic adjustments and virtualization to management of application delivery. A system can be completely external to an application delivery data path, or can be highly compatible for integration to the application delivery path. Entities can be billed on a per user, per application, per usage, or any combination of consumption-based billing.
    Type: Grant
    Filed: November 26, 2014
    Date of Patent: December 4, 2018
    Assignee: Anunta Technology Management Services Ltd.
    Inventors: Ananda Mukerji, Sanjiv Dalal, Vinod Jeyachandran
  • Patent number: 10140196
    Abstract: Systems and methods can use a testing framework for testing an event processing system. The testing framework operates to send a stream of input events for an event processing system, wherein each said input event is associated with a timestamp that is based on a system time, and wherein said event processing system processes the stream of input events in a batch mode with one or more sliding cycles. Furthermore, the testing framework can determine a base time for an event window in the system time, wherein said event window includes one or more input events in a sliding cycle that corresponds to a plurality of expected output events associated with a shared timestamp, and applies the event window on the stream of input events that are sent to the event processing system.
    Type: Grant
    Filed: February 9, 2015
    Date of Patent: November 27, 2018
    Assignee: ORACLE INTERNATIONAL CORPORATION
    Inventors: Guan Nan He, Ying Xi
  • Patent number: 10133569
    Abstract: An electronic circuit (4000) includes a bias value generator circuit (3900) operable to supply a varying bias value in a programmable range, and an instruction circuit (3625, 4010) responsive to a first instruction to program the range of said bias value generator circuit (3900) and further responsive to a second instruction having an operand to repeatedly issue said second instruction with said operand varied in an operand value range determined as a function of the varying bias value.
    Type: Grant
    Filed: December 15, 2016
    Date of Patent: November 20, 2018
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Kenichi Tashiro, Hiroyuki Mizuno, Yuji Umemoto
  • Patent number: 10120798
    Abstract: Technologies for field-programmable gate array (FPGA) processing include a computing device having a field-programmable gate array (FPGA) and a virtual FPGA controller (VFC). The computing device generates a user-specific platform profile (PP) that identifies one or more FPGA applications to be instantiated. The computing device synthesizes each FPGA application identified by the PP to generate a bit stream image that is associated with the PP and saves the bit stream image in a profile storage of the computing device. The computing device generates a virtual memory address that is indicative of the identified FPGA applications in response to saving the bit stream image. The VFC translates the virtual memory address to a user segment of the FPGA and a logical element (LE) offset within the user segment. The FPGA executes the bit stream associated with the PP with the FPGA at the LE offset. Other embodiments are described and claimed.
    Type: Grant
    Filed: June 12, 2017
    Date of Patent: November 6, 2018
    Assignee: Intel Corporation
    Inventors: Ned M. Smith, Rajesh Poornachandran, Abdul M. Bailey
  • Patent number: 10120770
    Abstract: Embodiments detect and group multiple failure events to enable batch processing of those failure events, such as in a virtual datacenter executing a plurality of virtual machines (VMs). A long timer, adaptive short timer, and adaptive polling frequency enable a computing device to efficiently detect and group the failure events that may be related (e.g., resulting from one failure). The grouped failure events are processed in parallel thereby reducing the time for recovery from the failure events.
    Type: Grant
    Filed: November 9, 2016
    Date of Patent: November 6, 2018
    Assignee: VMware, Inc.
    Inventors: Anjaneya Prasad Gondi, Hemanth Kalluri, Naveen Kumar Kalaskar
  • Patent number: 10114643
    Abstract: Various embodiments are generally directed to techniques to detect a return-oriented programming (ROP) attack by verifying target addresses of branch instructions during execution. An apparatus includes a processor component, and a comparison component for execution by the processor component to determine whether there is a matching valid target address for a target address of a branch instruction associated with a translated portion of a routine in a table comprising valid target addresses. Other embodiments are described and claimed.
    Type: Grant
    Filed: May 23, 2013
    Date of Patent: October 30, 2018
    Assignee: INTEL CORPORATION
    Inventors: Koichi Yamada, Palanivelra Shanmugavelayutham, Arvind Krishnaswamy, Jason M. Agron, Jiwei Lu
  • Patent number: 10102115
    Abstract: An application can include program code in multiple programming languages. Typically, a primary or host application program code will include secondary program code of at least one other programming language embedded within the primary application program code. A selective testing framework can be designed that efficiently evaluates embedded program code separately from the host application program code. The selective testing framework records specified embedded program code detected during execution of the application. Recording the embedded program code while the application executes allows the selective testing framework to incrementally construct an independently testable program in accordance with execution of the application. The testing framework can then test the constructed program code as it would run within the application, but test it external to and independent of the application. Without the overhead of executing the primary program code (e.g.
    Type: Grant
    Filed: November 15, 2016
    Date of Patent: October 16, 2018
    Assignee: CA, Inc.
    Inventor: David William Cosgrove, Jr.
  • Patent number: 10102034
    Abstract: A method and device for clearing an application process, and a mobile terminal are provided. The method for clearing an application process includes: clearing the application process; obtaining a restart interval of the application process; and clearing the application process continuously according to the restart interval, until the restart interval is greater than a predetermined time.
    Type: Grant
    Filed: August 13, 2014
    Date of Patent: October 16, 2018
    Assignee: CONEW NETWORK TECHNOLOGY CO. LTD.
    Inventors: Peng Luo, Zongliang Lin, Kangzong Zhang, Shengmo Xu, Sheng Fu
  • Patent number: 10095603
    Abstract: A method, computer program product and/or system for pre-fetching disassembly code. A breakpoint is set within an application under test (AUT). Setting of the breakpoint triggers pre-fetching of disassembly code associated with the breakpoint. The pre-fetched disassembly code is retained in a store local to a debug analysis system. When runtime processing of the AUT reaches the breakpoint, the debug analysis system retrieves the disassembly code from the local store.
    Type: Grant
    Filed: January 9, 2017
    Date of Patent: October 9, 2018
    Assignee: International Business Machines Corporation
    Inventors: Xiao Ling Chen, Chuan He, Yan Huang, Jiang Yi Liu, Jian Xu, Chong Zhou
  • Patent number: 10089262
    Abstract: A system and method for searching for and finding data across industrial time-series data is disclosed executing a series of instructions on a computer system. While executing a first instruction in the series of instructions, the virtual machine receives an interrupt signal. In response to receiving the interrupt signal, the virtual machine searches the series of instructions to identify a second instruction that is a safe point. The virtual machine replaces the second instruction in the series of instructions with one or more interrupt handler instructions that initiate an interrupt handler. The virtual machine resumes execution of the first instruction.
    Type: Grant
    Filed: June 19, 2015
    Date of Patent: October 2, 2018
    Assignee: SAP SE
    Inventor: Martin Doerr
  • Patent number: 10067851
    Abstract: A method, computer program product and/or system for pre-fetching disassembly code. A breakpoint is set within an application under test (AUT). Setting of the breakpoint triggers pre-fetching of disassembly code associated with the breakpoint. The pre-fetched disassembly code is retained in a store local to a debug analysis system. When runtime processing of the AUT reaches the breakpoint, the debug analysis system retrieves the disassembly code from the local store.
    Type: Grant
    Filed: August 22, 2017
    Date of Patent: September 4, 2018
    Assignee: International Business Machines Corporation
    Inventors: Xiao Ling Chen, Chuan He, Yan Huang, Jiang Yi Liu, Jian Xu, Chong Zhou
  • Patent number: 10042729
    Abstract: An apparatus and method are described for a scalable testing agent. For example, one embodiment of a scalable test engine comprises: an input interface to receive commands and/or data from a processor core or an external test system, the commands and/or data to specify one or more test operations to be performed on one or more intellectual property (IP) blocks of a chip; a first circuit to establish communication with an IP block over an interconnect fabric, the first circuit to transmit the one or more test operations to the IP block responsive to the received commands and/or data, the IP block to process the test operations and generate results; and a second circuit to receive the results from the IP block over the interconnect fabric, the results to be provided from the second circuit to the processor core and/or the external test system for analysis.
    Type: Grant
    Filed: April 1, 2016
    Date of Patent: August 7, 2018
    Assignee: Intel Corporation
    Inventors: Lakshminarayana Pappu, Robert De Gruijl, Suketu U. Bhatt, Robert P. Adler, R Selvakumar Raja Gopal, Rius Tanadi
  • Patent number: 10001992
    Abstract: A method includes: calculating a percentage of an instruction belonging to a certain instruction type among instruction types included in each of a plurality of blocks partitioned from a program; extracting an execution address and a number of execution instructions from an arithmetic processing unit that executes the program and performs sampling of the execution address and the number of execution instructions at a plurality of time points, calculating a first execution frequency of the instruction included in each of the plurality of blocks based on the extracted execution address and the number of execution instructions; calculating a second execution frequency of the instruction belonging to the instruction type by multiplying the first execution frequency of the block by the percentage of the instruction in the block; calculating total number of second execution frequencies calculated for each of the plurality of blocks.
    Type: Grant
    Filed: February 12, 2016
    Date of Patent: June 19, 2018
    Assignee: FUJITSU LIMITED
    Inventor: Masao Yamamoto
  • Patent number: 9971599
    Abstract: A processor includes support for executing binary-translated code including code modifications. The processor includes a processor core that includes a cache to store translation indicators from a physical map, each translation indicator to indicate whether a corresponding memory location includes translated code to be protected. The processor core also includes logic to execute a translated instruction. The translated instruction is translated from an instruction stored in a memory location. The processor core further includes logic to set a translation indicator in the cache corresponding to the memory location to indicate that it includes translated code to be protected. The processor core also includes logic to request senior store buffer drains of other processor cores of the processor based upon the execution of the translated instruction.
    Type: Grant
    Filed: May 8, 2017
    Date of Patent: May 15, 2018
    Assignee: Intel Corporation
    Inventors: John H. Kelm, David P. Keppel, David N. Mackintosh
  • Patent number: 9965280
    Abstract: A processor includes a front end to decode an instruction and pass the instruction to execution units with branch suffix information. The processor further includes execution units to execute the instruction and a retirement unit to retire the instruction. The instruction is to specify an operation to be conditionally executed based upon a branch suffix to identify previous execution. The processor further includes logic to, upon retirement of the instruction, determine the result of a series of branch operations preceding execution of the instruction, compare the result to the branch suffix information, allow execution and retirement of the instruction based on a determination that the result matches the branch suffix information, and generate a fault based on a determination that the result does not match the branch suffix information.
    Type: Grant
    Filed: September 25, 2015
    Date of Patent: May 8, 2018
    Assignee: Intel Corporation
    Inventors: Michael F. Spear, Gilles A. Pokam