Specialized Instruction Processing In Support Of Testing, Debugging, Emulation Patents (Class 712/227)
  • Patent number: 11397659
    Abstract: An information processing apparatus, includes a memory; and a first processor coupled to the memory and configured to: identify a maximum operating frequency of each of a plurality of second processors, when executing a plurality of processes to be subjected to parallel processing by the plurality of second processors, measure a load value representing a magnitude of a load of each of the plurality of processes, and determine, based on the identified maximum operating frequency of each of the plurality of second processors and the measured load value of each of the plurality of processes, a specific processor as an assignment destination of each of the plurality of processes from the plurality of second processors.
    Type: Grant
    Filed: November 24, 2020
    Date of Patent: July 26, 2022
    Assignee: FUJITSU LIMITED
    Inventor: Naoto Fukumoto
  • Patent number: 11392482
    Abstract: To set data breakpoints on properties and certain other functions, constituent data locations (CDLs) that can contribute to computation of the property value or other function result are identified, and respective constituent data breakpoints are added at one or more CDLs by data breakpoint adder code. Each constituent data breakpoint will suspend execution of an inspectable software in response to occurrence of a CDL data entry. The CDLs are identified by CDL identifier code using static data flow analysis, enhanced interpretation, or disassembly, with recursion as appropriate. Kernel or runtime routines, and other routines designated as known, can be excluded from the CDL search. Data locations marked read-only, or that are effectively read-only because they will not be written, can also be excluded.
    Type: Grant
    Filed: January 3, 2019
    Date of Patent: July 19, 2022
    Assignee: Microsoft Technology Licensing, LLC
    Inventors: Charles Joseph Ries, Patrick Nelson, Cagri Aslan, Gregory Miskelly, Isadora Sophia Garcia Rodopoulos
  • Patent number: 11385793
    Abstract: Methods, articles of manufacture, and apparatus are disclosed to manage workload memory allocation. An example method includes identifying a primary memory and a secondary memory associated with a platform, the secondary memory having first performance metrics different from second performance metrics of the primary memory, identifying access metrics associated with a plurality of data elements invoked by a workload during execution on the platform, prioritizing a list of the plurality of data elements based on the access metrics associated with corresponding ones of the plurality of data elements, and reallocating a first one of the plurality of data elements from the primary memory to the secondary memory based on the priority of the first one of the plurality of memory elements.
    Type: Grant
    Filed: May 8, 2020
    Date of Patent: July 12, 2022
    Assignee: Intel Corporation
    Inventors: Michael R. Greenfield, Roger Golliver
  • Patent number: 11366800
    Abstract: A system and method to automate validating media redirection in a virtual media redirection testing process. A computing device is provided for performing the test. During the test, the computing device executes an automated script to obtain, from a media storage device, a media file to be redirected, and then calculate a first checksum value for the media file being obtained. The computing device then executes a redirection module to perform the virtual media redirection process for the media file, and copy the media file to a local path of the computing device. Once the media file is redirected, the automated script calculates a second checksum value for the media file at the local path of the computing device. Thus, the media file may be validated by matching the two checksum values, and the redirection process is determined to be successful when the checksum values match.
    Type: Grant
    Filed: August 22, 2016
    Date of Patent: June 21, 2022
    Assignee: AMERICAN MEGATRENDS INTERNATIONAL, LLC
    Inventors: Ramachandran Arumugham, Arunprasad Rajaiah, Vinothkumar Manickavelu
  • Patent number: 11320800
    Abstract: To optimize NC program cores included in a generated machining program and expedite operation of a machine tool. An optimization device includes a block analysis unit, a code processing unit, and a program generation unit. The block analysis unit analyzes a preparatory function code and/or an auxiliary function code for each of a plurality of blocks included in a first program. The code processing unit performs a process on the preparatory function code and/or the auxiliary function code in a plurality of successive blocks based on a result of the analysis by the block analysis unit and optimizes the first program. The program generation unit generates the first program optimized by the code processing unit as a second program.
    Type: Grant
    Filed: September 2, 2020
    Date of Patent: May 3, 2022
    Assignee: FANUC CORPORATION
    Inventor: Toshifumi Muramatsu
  • Patent number: 11314623
    Abstract: Software tracing can be accomplished in a multitenant environment according to various examples of the present disclosure. In one example, a processing device can receive tracing information and a tenant identifier. The tracing information can indicate a sequence in which a group of microservices forming a software application executed in response to a request transmitted to the software application. The tenant identifier can correspond to a particular tenant among a group of tenants having access to an instance of the software application. The processing device can then select, based on the tenant identifier, a particular collector from among a group of collectors corresponding to the group of tenants. The processing device can forward the tracing information to the particular collector for causing the tracing information to be stored in a datastore corresponding to the particular tenant.
    Type: Grant
    Filed: January 23, 2019
    Date of Patent: April 26, 2022
    Assignee: Red Hat, Inc.
    Inventor: Juraci Paixao Kroehling
  • Patent number: 11294787
    Abstract: An apparatus and method are provided to control assertion of a trigger signal to processing circuitry. The apparatus has evaluation circuitry to receive program instruction execution information indicative of a program instruction executed by the processing circuitry, which is arranged to perform an evaluation operation to determine with reference to evaluation information whether the program instruction execution information indicates presence of a trigger condition. Trigger signal generation circuitry is used to assert a trigger signal to the processing circuitry in dependence on whether the trigger condition is determined to be present. Further, filter circuitry is arranged to receive event information indicative of at least one event occurring within the processing circuitry, and is arranged to determine with reference to filter control information and that event information whether a qualifying condition is present.
    Type: Grant
    Filed: August 10, 2017
    Date of Patent: April 5, 2022
    Assignee: ARM Limited
    Inventors: François Christopher Jacques Botman, Thomas Christopher Grocutt, John Michael Horley, Michael John Williams
  • Patent number: 11269647
    Abstract: A simultaneous multithreading processor and related method of operating are disclosed. The method comprises dispatching portions of a first instruction to be executed by a respective plurality of execution units of the processor; receiving, at an instruction completion table of the processor, respective finish reports responsive to execution of the portions of the first instruction; determining, using the received finish reports, that all of the portions of the first instruction have been executed; and updating the instruction completion table to indicate that the first instruction is ready for completion.
    Type: Grant
    Filed: December 18, 2017
    Date of Patent: March 8, 2022
    Assignee: International Business Machines Corporation
    Inventors: Kenneth L. Ward, Susan E. Eisen, Dung Q. Nguyen, Glenn O. Kincaid, Christopher M. Mueller, Tu-An T. Nguyen, Gaurav Mittal, Deepak K. Singh
  • Patent number: 11188355
    Abstract: A method for verifying data plane programs is provided in some embodiments. Because the behavior of a data plane program (e.g., a program written in the P4 language) is determined in part by the control plane populating match-action tables with specific forwarding rules, in some embodiments, programmers are provided with a way to document assumptions about the control plane using annotations (e.g., in the form of “assertions” or “assumptions” about the state based on the unknown control plane contribution). In some embodiments, annotations are added automatically to verify common properties, including checking that every header read or written is valid, that every expression has a well-defined value, and that all standard metadata is manipulated correctly. The method in some embodiments translates programs from a first language (e.g., P4) to a second language (e.g., Guarded Command Language (GCL)) for verification by a satisfiability modulo theory (SMT) solver.
    Type: Grant
    Filed: June 28, 2018
    Date of Patent: November 30, 2021
    Assignee: Barefoot Networks, Inc.
    Inventors: Jeongkeun Lee, Cole Nathan Schlesinger, John Nathan Foster, Han Wang, Robert Soule, William Hallahan, Steffen Julif Smolka, Mon Jed Liu
  • Patent number: 11182316
    Abstract: Interrupt code conversion for efficient computer program recovery. In response to an error being detected while processing instructions of a computer program running on a computer system, the OS receives a first program interrupt code (PIC) and interrupts the computer program. Control of the computer program is passed to a program interrupt handler and the program interrupt handler inspects the first PIC issued as a result of detecting the error. The first PIC is converted to a second PIC wherein the second PIC is associated with another error predicted when subsequent running of the computer program occurs. The second PIC is presented to a recovery routine associated with the computer program and, in response to the detected error, running of the computer program is customized based on the second PIC rather than the first PIC.
    Type: Grant
    Filed: May 20, 2019
    Date of Patent: November 23, 2021
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Steven Partlow, Elpida Tzortzatos, Peter Jeremy Relson, James H. Mulder, Christopher Lee Wood
  • Patent number: 11157280
    Abstract: Aspects of the invention include receiving, by a processor, a plurality of instructions at an instruction pipeline. The processor can further determine an operand bit field size for each of the received plurality of instructions. The processor can further compare the operand bit field size of at least a subset of the received instructions to a predetermined threshold. The processor can further fuse at least two of the received instructions that have an operand bit field size that meets the predetermined threshold. The processor can further perform an execution stage within the instruction pipeline to execute the received instructions, including the fused instructions.
    Type: Grant
    Filed: December 7, 2017
    Date of Patent: October 26, 2021
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Maarten J. Boersma, Bruce Fleischer, Robert A. Philhower, Balaram Sinharoy
  • Patent number: 11152076
    Abstract: An apparatus and method are provided for executing debug instructions. The apparatus has processing circuitry for executing instructions fetched from memory, and a debug interface. The processing circuitry is responsive to a halt event to enter a halted mode where the processing circuitry stops executing the instructions fetched from memory, and instead is arranged to execute debug instructions received from a debugger via the debug interface. The processing circuitry is responsive to detection of a trigger condition when executing a given debug instruction to exit the halted mode transparently to the debugger, and to take an exception in order to execute exception handler code comprising a sequence of instructions fetched from memory. On return from the exception, the processing circuitry then re-enters the halted mode and performs any additional processing required to complete execution of the given debug instruction.
    Type: Grant
    Filed: September 23, 2019
    Date of Patent: October 19, 2021
    Assignee: Arm Limited
    Inventor: Simon John Craske
  • Patent number: 11138134
    Abstract: A software only debug approach is provided that does not require special hardware in a target embedded system undergoing debug. Instead, already present DMA capabilities of the target system are utilized to transfer I/O operation parameters into a memory area accessible to both the target processor and a debugger executing on a host system. The debugger can thereby access and execute the I/O operations without program execution stopping on the target. A semihosting library is provided as a replacement for the standard C I/O library on the target. The semihosting library provides a range of equivalent functions to the standard C I/O API that program a DMA transfer to copy the I/O function parameters to an external memory area that is not otherwise being used by the target core processor. The external memory area is then accessed by a debug tool on the host computer.
    Type: Grant
    Filed: October 23, 2019
    Date of Patent: October 5, 2021
    Assignee: NXP USA, Inc.
    Inventors: Alexandra Dracea, Catalina D. Mitulescu
  • Patent number: 11138050
    Abstract: Operation of a multi-slice processor that includes execution slices and a dispatch network of the multi-slice processor implementing a hardware level transfer of an execution thread between execution slices. Operation of such a multi-slice processor includes responsive to a thread switch signal: halting dispatch of one or more instructions retrieved from an instruction cache; generating a plurality of instructions to transfer an execution thread from a first execution slice to a second execution slice; and dispatching the plurality of instructions instead of the one or more instructions retrieved from the instruction cache; and transferring, in dependence upon execution of the plurality of instructions from the thread switching instruction generator, the execution thread from the first execution slice to the second execution slice.
    Type: Grant
    Filed: March 14, 2019
    Date of Patent: October 5, 2021
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Brian D. Barrick, James W. Bishop, Marcy E. Byers, Sundeep Chadha, Cliff Kucharski, Dung Q. Nguyen, David R. Terry, Jing Zhang
  • Patent number: 11126537
    Abstract: A coprocessor stores at least part of an execution trace based on code execution at a primary processor. The coprocessor includes control logic that configures the coprocessor to listen to a bus that interconnects the primary processor and the coprocessor, and to receive one or more cache coherency protocol (CCP) messages from the bus (i.e., CCP message(s) sent on the bus by the primary processor, based on the primary processor having consumed data for a memory cell). Based on receiving the CCP message(s), the coprocessor initiates storing of the consumed data for the memory cell into an execution trace.
    Type: Grant
    Filed: May 2, 2019
    Date of Patent: September 21, 2021
    Assignee: Microsoft Technology Licensing, LLC
    Inventor: Jordi Mola
  • Patent number: 11119777
    Abstract: Techniques for an extended prefix including a routing bit for an extended instruction format are described herein. An aspect includes generating, by an instruction preprocessing module, a first extended instruction corresponding to an internal operation including a first routing bit. Another aspect includes generating, by the instruction preprocessing module, a second extended instruction corresponding to a prefixed instruction set architecture (ISA) instruction including a second routing bit, wherein a value of the second routing bit is opposite a value of the first routing bit. Another aspect includes providing the first extended instruction and the second extended instruction to a central processing unit (CPU). Another aspect includes, based on the value of the first routing bit, routing the internal operation directly to an execution unit of the CPU, and based on the value of the second routing bit, routing the prefixed ISA instruction to a decode/execute path of the CPU.
    Type: Grant
    Filed: April 22, 2020
    Date of Patent: September 14, 2021
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Giles Roger Frazier, Hung Q. Le
  • Patent number: 11099853
    Abstract: Digit validation check control for execution of an instruction. A process obtains an instruction to perform operation(s) using input value(s). The instruction includes a no validation indicator for controlling whether digit validation check control is enabled for execution of the instruction. The process executes the instruction, including determining, based on the no validation indicator, whether digit validation check control is enabled for execution of the instruction, and performing processing based on the determining. Based on the no validation indicator being set to a defined value, digit validation check control is enabled and the processing includes forcing a digit check error indicator output by the executing to indicate no digit check error with respect to the at least one input value.
    Type: Grant
    Filed: February 15, 2019
    Date of Patent: August 24, 2021
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Cedric Lichtenau, Reid Copeland, Petra Leber, Silvia M. Mueller, Jonathan D. Bradbury, Xin Guo
  • Patent number: 11093843
    Abstract: Embodiments of the present invention are directed to techniques for optimizing an execution mode used to process a request. A self-training storage system can determine one or more proposed execution modes based on a real-time evaluation of various factors, including a history of execution modes used to process historical requests. This history can serve as training data for a machine learning model that can predict an execution mode based on one or more request parameters. This predicted execution mode can be taken as one of a number of proposed execution modes that can be combined using a weightage system to automatically classify an ultimate execution mode used to process the request. Associated weights for combining proposed execution modes can be determined by training a machine learning model using a training set constructed based on a survey of user satisfaction with a determined execution mode.
    Type: Grant
    Filed: November 29, 2017
    Date of Patent: August 17, 2021
    Assignee: Adobe Inc.
    Inventors: Shashank Gupta, Gaurav Gupta
  • Patent number: 11068386
    Abstract: Methods and systems for performing mainframe batch testing and/or property-based validation testing using a finite-state machine are provided. According to certain aspects, a validation server may receive a set of batch data designed to validate a property under test, such as during mainframe batch testing. A validation server may validate that the set of batch data is in a proper format. The validation server may then cause a finite-state machine to process instructions contained within the set of batch data. Once the finite-state machine processes the set of batch data, the validation server may then validate that the finite-state machine adheres to the property under test. If the validation fails, the validation server may generate an error report describing the failure.
    Type: Grant
    Filed: December 2, 2019
    Date of Patent: July 20, 2021
    Assignee: STATE FARM MUTUAL AUTOMOBILE INSURANCE COMPANY
    Inventors: Joseph W. Norton, James D. Titlow, Matthew W. Holloway, Amanda J. Tolonen, Venkata R. Kongara, Timothy J. Wheeler
  • Patent number: 11039031
    Abstract: This information processing system (100) includes an information processing device (1) and a display input device (2). The display input device (2) receives settings of a first target, first processing, a second target, and second processing. The information processing device (1) takes, as a condition, the execution of the set first processing by using the set first target, and, when the condition is satisfied, generates a workflow (5) for executing the set second processing by using the set second target.
    Type: Grant
    Filed: January 25, 2018
    Date of Patent: June 15, 2021
    Assignee: KYOCERA Document Solutions Inc.
    Inventors: Lianney Deleverio, Alexander Kenneth Go, Manuel Baricuatro, Jr., Gestoni Bacalso, Gervel Giva, Eliot Emerson Uy, Dennis Arriola, Joard Saquilon, Jelousy Saga
  • Patent number: 11023584
    Abstract: A processor receives a signal and determines whether an application has registered a signal handler therewith for handling the signal. In response to determining that the application has registered the signal handler, the processor transmits the signal directly to the signal handler of the application for handling the signal, without an operating system in relation to which the trusted application is running intervening. In response to determining that the trusted application has not registered the signal handler, the processor transmits the signal to a signal handler of the operating system for handling the signal.
    Type: Grant
    Filed: August 1, 2019
    Date of Patent: June 1, 2021
    Assignee: International Business Machines Corporation
    Inventors: Andrew D. Hilton, Brian M. Rogers
  • Patent number: 10983947
    Abstract: A method and system for enabling persistence of a value by a dynamically reconfigurable processor (“DRP”) from the time of execution of an earlier executed instruction to a time of later executed instruction. The value may represent a constant a variable value of a software program. The value may be read from or written into a memory circuit, a DRP logic element, an iterator of a DRP logic element, or other value storing element or aspect of the DRP. The value may be maintained in a single logic element through the duration of one or more instruction execution cycles, or alternatively or additionally, the value may be transferred between or among one or more value storage hardware elements. The persistence of the value and transfer of the value within, into and/or out of the DRP enables later access of the value by, and/or positioning the value within, the DRP.
    Type: Grant
    Filed: September 11, 2013
    Date of Patent: April 20, 2021
    Inventor: Robert Keith Mykland
  • Patent number: 10983697
    Abstract: A method includes, in one non-limiting embodiment, sending a request from a mass memory storage device to a host device, the request being one to allocate memory in the host device; writing data from the mass memory storage device to allocated memory of the host device; and subsequently reading the data from the allocated memory to the mass memory storage device. The memory may be embodied as flash memory, and the data may be related to a file system stored in the flash memory. The method enables the mass memory storage device to extend its internal volatile RAM to include RAM of the host device, enabling the internal RAM to be powered off while preserving data and context stored in the internal RAM.
    Type: Grant
    Filed: May 25, 2018
    Date of Patent: April 20, 2021
    Assignee: Memory Technologies LLC
    Inventors: Olli Luukkainen, Kimmo Mylly, Jani Hyvonen
  • Patent number: 10970070
    Abstract: An apparatus has processing circuitry to perform, in response to decoding of an iterative-operation instruction by the instruction decoder, an iterative operation comprising at least two iterations of processing where one iteration depends on an operand generated in a previous iteration. Preliminary information generating circuitry performs a preliminary portion of processing for a given iteration to generate preliminary information. Result generating circuitry performs a remaining portion of processing for the given iteration, to generate a result value using the preliminary information. Forwarding circuitry forwards the result value as an operand for a next iteration of the iterative operation, for iterations other than the final iteration. The preliminary information generating circuitry starts performing the preliminary portion for the next iteration in parallel with the result generating circuitry completing the remaining portion for the current iteration, to improve performance.
    Type: Grant
    Filed: March 29, 2019
    Date of Patent: April 6, 2021
    Assignee: Arm Limited
    Inventors: Nicholas Andrew Pfister, Srinivas Vemuri, David Raymond Lutz
  • Patent number: 10956311
    Abstract: Provided are systems, methods, and media for concurrency conflict testing for shared resources. An example method includes identifying shared resources that are to be accessed by an application. Generating a plurality of concurrency test scenarios based on the shared resources. Analyzing a plurality of concurrency test cases to detect which concurrency test cases include a reference to the shared resources. Executing a concurrency test scenario.
    Type: Grant
    Filed: July 24, 2019
    Date of Patent: March 23, 2021
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Li Li, Li Xiang, Chang Zhi GZ Zhang, Ting Xie, Xin Zheng, Yan Wang, Hai He, Si Bin Fan
  • Patent number: 10942945
    Abstract: Techniques are described herein for isolating runtime environments in a multitenant container DBMS. A CDB may contain a database dictionary that defines a plurality of pluggable databases and a respective database nest for each pluggable database. Each respective database nest of said each pluggable database is associated with different operating system privileges. When database sessions are established on a container DBMS, each database session is given access to a pluggable database by attaching the respective database nest of the pluggable database to each database session.
    Type: Grant
    Filed: October 19, 2018
    Date of Patent: March 9, 2021
    Assignee: ORACLE INTERNATIONAL CORPORATION
    Inventors: Santosh Shilimkar, Nagarajan Muthukrishnan, Ravi Thammaiah, Sumanta Chatterjee, Binoy Sukumaran
  • Patent number: 10904238
    Abstract: Techniques are described for managing access tokens in a computing environment. A proxy service can be configured to issue a first token to a workflow engine, the first token having a substantially unlimited lifetime to not time out during the workflow duration. The first token may be provided to the workflow in place of a shorter-lifetime token that may have otherwise been requested from a backend service. The first token may be used by the workflow engine to provide authorization for operations of the workflow. On completion of the workflow, the workflow engine may send an indication to the proxy service to request interactions with the backend service. The proxy service may request a second (e.g., limited-lifetime) token from the backend service, and use the second token to interact with the backend service on behalf of the workflow, thus acting as an intermediary between the workflow and the backend service.
    Type: Grant
    Filed: July 13, 2018
    Date of Patent: January 26, 2021
    Assignee: SAP SE
    Inventor: Krassimir Kondarev
  • Patent number: 10896081
    Abstract: A method and a circuit for implementing single event upset (SEU) parity detection, and a design structure on which the subject circuit resides are provided. The circuit implements detection of unwanted state changes due to SEUs, noise or other event in a latch having a default state of zero. The latch includes an L1 latch and an L2 latch with the L2 latch having the connected output and is used and monitored for a flip. A pair of series-connected field effect transistors (FETs) is connected between a drive input of a parity control circuit and ground potential. An inverted output of the L1 latch and a true output of the L2 latch is applied to a respective gate of the pair of series-connected FETs.
    Type: Grant
    Filed: December 13, 2018
    Date of Patent: January 19, 2021
    Assignee: International Business Machines Corporation
    Inventors: David D. Cadigan, William V. Huott, Anuwat Saetow, Adam J. McPadden
  • Patent number: 10885015
    Abstract: Systems, methods, and products for database system transaction management are provided herein. One aspect provides for annotating via a computing device at least one data object residing on the computing device utilizing at least one transaction tag, the at least one transaction tag being configured to indicate a status of an associated data object; processing at least one database transaction utilizing a transactional memory process, wherein access to the at least one data object is determined based on the status of the at least one data object; and updating the status of the at least one data object responsive to an attempted access of the at least one data object by the at least one database transaction. Other embodiments and aspects are also described herein.
    Type: Grant
    Filed: December 21, 2017
    Date of Patent: January 5, 2021
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Harold Wade Cain, III, Donna N. Dillenberger, Michel H. T. Hack, Hong Min, Gong Su, James Zu-Chia Teng
  • Patent number: 10821958
    Abstract: A computation unit having at least one computation core, a primary memory device, and at least one main connecting unit for connecting the at least one computation core to the primary memory device, the computation unit having at least two functional units, at least a first functional unit of the at least two functional units being embodied a) to receive first data from at least one further functional unit of the at least two functional units, and/or b) to transmit second data to at least one further functional unit of the at least two functional units.
    Type: Grant
    Filed: June 8, 2018
    Date of Patent: November 3, 2020
    Assignee: Robert Bosch GmbH
    Inventors: Matthias Schreiber, Axel Aue, Nico Bannow
  • Patent number: 10754953
    Abstract: The present invention provides a TrustZone-based security isolation system for shared library, the system at least comprising: a sandbox creator, a library controller, and an interceptor, the sandbox creator, in a normal world, dynamically creating a sandbox isolated from a Rich OS, the interceptor, intercepting corresponding system-calling information and/or Android framework APIs by means of inter-process stack inspection, the library controller, performing analysis based on the intercepted system-calling information and/or Android framework APIs, redirecting a library function to the sandbox, and switching calling states of the library function in the sandbox as well as setting up a library authority. The present invention has good versatility, low cost and high security. It realizes isolation of the library without increasing the trusted bases in the Secure World of the TrustZone, effectively reducing the risk of being attacked.
    Type: Grant
    Filed: August 23, 2018
    Date of Patent: August 25, 2020
    Assignee: Huazhong University of Science and Technology
    Inventors: Hai Jin, Weiqi Dai, Jun Deng, Deqing Zou
  • Patent number: 10747645
    Abstract: Expressly turning tracing on and off at each juncture between code that a developer wants to have traced and other code may reduce trace file size but adds computational cost. Described technologies support selectively tracing a process's execution, with some extra tracing done beyond the code the developer wanted traced, but with significantly reduced computational cost, by reducing the number of trace enablement and disablement operations. A trace controller uses a tracing disablement distance variable whose values indicate the computational distance from trace disablement. A distance variable modifier automatically moves the distance variable closer to a stop-tracing value as the process executes. The amount of extra tracing is balanced against the reduction in trace enablement/disablement operations by tuning thresholds, based on information about routine size and computational cost.
    Type: Grant
    Filed: April 27, 2018
    Date of Patent: August 18, 2020
    Assignee: MICROSOFT TECHNOLOGY LICENSING, LLC
    Inventors: Del Myers, Jackson Davis, Thomas Lai, Patrick Nelson, Jordi Mola, Juan Carlos Arevalo Baeza
  • Patent number: 10740219
    Abstract: Described technologies support selectively tracing a process's execution, with some extra tracing done beyond the code the developer wanted traced, but with significantly reduced computational cost, by reducing the number of trace enablement and disablement operations. A trace controller uses a tracing disablement distance variable whose values indicate the computational distance from trace disablement. A distance variable modifier automatically moves the distance variable closer to a stop-tracing value as the process executes. A create task function is modified to include the setting of an indicator that a newly created task is to be traced if a current task or thread is being traced. An execute task function is modified to request the tracing of the newly created task when it is executed based on the indicator, thereby enabling selective tracing that operates across process boundaries and traces asynchronous code execution.
    Type: Grant
    Filed: October 29, 2018
    Date of Patent: August 11, 2020
    Assignee: WORKMAN NYDEGGER
    Inventors: Del Myers, Thomas Lai, Patrick Nelson, Jordi Mola, Juan Carlos Arevalo Baeza, Stephen Harris Toub
  • Patent number: 10691576
    Abstract: An integrated circuit can include a functional unit and a local debug unit. The local debug unit can include a trace buffer, and the local debug unit is configured to track and store operation information of the functional unit in the trace buffer. The integrated circuit can also include a global debug unit coupled to the local debug unit. The integrated circuit is configured to send a debug reset command to reset the functional unit, without sending the debug reset command to the local debug unit, thereby retaining information stored in the trace buffer. The integrated circuit is also configured to send a power-up reset command to reset the local debug unit and the functional unit, thereby causing the local debug unit to clear the trace buffer.
    Type: Grant
    Filed: September 26, 2017
    Date of Patent: June 23, 2020
    Assignee: Amazon Technologies, Inc.
    Inventors: Yaniv Shapira, Gil Stoler, Adi Habusha
  • Patent number: 10636112
    Abstract: A processing apparatus is described. The apparatus includes a graphics processing unit (GPU), including a plurality of execution units to process graphics context data and a register file having a plurality of registers to store the graphics context data; and register renaming logic to facilitate re-use of register data by partitioning a first part and a second part, the first part to include thread-independent code and the second part to include thread-dependent code.
    Type: Grant
    Filed: March 28, 2018
    Date of Patent: April 28, 2020
    Assignee: Intel Corporation
    Inventors: Slawomir Grajewski, Kaiyu Chen, Guei-Yuan Lueh, Subramaniam Maiyuran
  • Patent number: 10628335
    Abstract: Processing circuitry 2 includes data storage circuitry 18 for storing one or more ordered sets of data entries. Access control circuitry 20 controls access during a given access cycle to a given ordered set of data entries in dependence upon, for that given set of data entries, a head-entry flag, a next-following-entry flag and preceding-cycle data. The head-entry flag indicates the oldest data entry for the given ordered set, the next-following-entry flag indicates the next oldest entry and the preceding-cycle flag indicates whether the given ordered set was accessed during a preceding access cycle. If the given ordered set was accessed during the preceding access cycle, then the next-following entry corresponding to the next-following flag is accessed during the current access cycle instead of that indicated by the head flag.
    Type: Grant
    Filed: July 18, 2018
    Date of Patent: April 21, 2020
    Assignee: ARM Limited
    Inventors: Jaume Cabecerans Betran, Eduard Vardanyan
  • Patent number: 10606498
    Abstract: A method for managing a discontinuous call stack is disclosed to more efficiently use the memory of devices without a memory management unit.
    Type: Grant
    Filed: December 23, 2016
    Date of Patent: March 31, 2020
    Assignee: Arm IP Limited
    Inventors: James Crosby, Brendan James Moran
  • Patent number: 10585668
    Abstract: A process for processor testing includes generating a set of test instructions having a first portion and a second portion. A first branch instruction is randomly generated for the first portion where the first branch instruction branches to a respective instruction in a second portion by a branching location offset. A second branch instruction is randomly generated for the second portion where the second branch instruction branches to a respective instruction in the first portion by the branching location offset. If additional instructions are to be added to the set of test instructions, a value of the branching location offset is incrementing by a predetermined amount.
    Type: Grant
    Filed: October 2, 2017
    Date of Patent: March 10, 2020
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Abhishek Bansal, Nitin P. Gupta, Brad L. Herold, Jayakumar N. Sankarannair
  • Patent number: 10572233
    Abstract: Provided is a vectorization device 30 comprising: a unit 31 that detects a configuration in which the inner loop length depends on the outer loop variable, and in which a first array indicating the results of dual-loop processing does not contain the inner loop variable as an index value; an unit 32 that, when the configuration is detected, determines a fixed value as the inner loop length; an unit 33 that expands the array size of a second array used in the calculation of the first array value, and thereby enables dual-loop processing of the inner loop; an unit 34 that sets an element value for an added element of the second array, and thereby, before and after such processing is carried out, enables the results of the dual-loop processing to be made equal; and an unit 35 that updates the software on the basis of such processing results.
    Type: Grant
    Filed: November 17, 2016
    Date of Patent: February 25, 2020
    Assignee: NEC CORPORATION
    Inventor: Yoshiyuki Ohno
  • Patent number: 10564962
    Abstract: An electronic circuit (4000) includes a bias value generator circuit (3900) operable to supply a varying bias value in a programmable range, and an instruction circuit (3625, 4010) responsive to a first instruction to program the range of the bias value generator circuit (3900) and further responsive to a second instruction having an operand to repeatedly issue the second instruction with the operand varied in an operand value range determined as a function of the varying bias value.
    Type: Grant
    Filed: November 19, 2018
    Date of Patent: February 18, 2020
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Kenichi Tashiro, Hiroyuki Mizuno, Yuji Umemoto
  • Patent number: 10558806
    Abstract: A processor receives a signal and determines whether an application has registered a signal handler therewith for handling the signal. In response to determining that the application has registered the signal handler, the processor transmits the signal directly to the signal handler of the application for handling the signal, without an operating system in relation to which the trusted application is running intervening. In response to determining that the trusted application has not registered the signal handler, the processor transmits the signal to a signal handler of the operating system for handling the signal.
    Type: Grant
    Filed: December 13, 2016
    Date of Patent: February 11, 2020
    Assignee: International Business Machines Corporation
    Inventors: Andrew D. Hilton, Brian M. Rogers
  • Patent number: 10509906
    Abstract: In an example embodiment, a system determines a set of instructions from the available instructions for a computer application. The determined set of instructions provides specific functionality of the computer application. The system may determine the set of instructions by performing functional testing and negative testing on the specific functionality. The system may reorganize and randomize the set of instructions in memory and write the reorganized set of instructions to a smaller memory space. For each available instruction not in the set of instructions, the system changes the respective instruction to inoperative to prevent execution of the respective instruction. The system may change the respective instruction to inoperative by overwriting the instruction with a NOP instruction. The system then captures a memory address of the computer application being accessed at runtime.
    Type: Grant
    Filed: July 10, 2017
    Date of Patent: December 17, 2019
    Assignee: Virsec Systems, Inc.
    Inventor: Satya Vrat Gupta
  • Patent number: 10503479
    Abstract: Examining source code repositories for indications of orthogonal technologies in actual use or of potential usefulness in the development and continuous delivery of the contents of the repositories.
    Type: Grant
    Filed: May 7, 2018
    Date of Patent: December 10, 2019
    Assignee: International Business Machines Corporation
    Inventors: Christopher Brealey, Christopher Taylor, Joel Cayne, Philippe Mulet, Ritchard L. Schacher, Thomas C. Schmidt
  • Patent number: 10496405
    Abstract: Embodiments of the present invention are directed to a computer-implemented method for generating and verifying hardware instruction traces including memory data contents. The method includes initiating an in-memory trace (IMT) data capture for a processor, the IMT data being an instruction trace collected while instructions flow through an execution pipeline of the processor. The method further includes capturing contents of architected registers of the processor by: storing the contents of the architected registers to a predetermined memory location, and causing a load-store unit (LSU) to read contents of the predetermined memory location.
    Type: Grant
    Filed: November 20, 2017
    Date of Patent: December 3, 2019
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Jane H. Bartik, Christian Jacobi, David Lee, Jang-Soo Lee, Anthony Saporito, Christian Zoellin
  • Patent number: 10484361
    Abstract: In accordance with disclosed embodiments, there are provided systems, methods, and apparatuses for implementing virtual device observation and debug network for high speed serial IOS.
    Type: Grant
    Filed: June 30, 2016
    Date of Patent: November 19, 2019
    Assignee: Intel Corporation
    Inventors: Lakshminarayana Pappu, Timothy J. Callahan, Baruch Schnarch, Hem Doshi, Suketu U. Bhatt
  • Patent number: 10467114
    Abstract: A hierarchical data processor test system (and method) is usable to configure a hierarchical plurality of similarity operators and process predetermined input test data through a data processor under test (DPUT) to produce corresponding DPUT output data. The test system is further usable to process the DPUT output data and the predetermined output test data through at least some of the plurality of similarity operators in hierarchical order, determine a highest order similarity operator that indicates a match between the DPUT output data and the predetermined output test data, and compute a confidence score based on the highest order similarity operator that indicated the match. Based on the confidence score exceeding a threshold, the test system also may include activating the DPUT for use by non-test data.
    Type: Grant
    Filed: July 14, 2016
    Date of Patent: November 5, 2019
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Neil S. Bhargava, Freddys M. Espinoza, Stefan A. Gert Van Der Stockt
  • Patent number: 10445133
    Abstract: A method for managing thread execution in a processing system is provided. The method includes setting a first watchpoint, and generating a first watchpoint trigger corresponding to the first watchpoint. In response to the first watchpoint trigger, execution of a first thread is controlled in accordance with a value stored in a first control register. Controlling the first thread may further include disabling execution of the first thread. The disabling execution of the first thread may occur within the first watchpoint region.
    Type: Grant
    Filed: March 4, 2016
    Date of Patent: October 15, 2019
    Assignee: NXP USA, Inc.
    Inventors: Jonathan J. Gamoneda, Jehoda Refaeli, Jeffrey W. Scott
  • Patent number: 10423778
    Abstract: Described herein are techniques for dealing with the problem of security vulnerabilities in computer software due to undefined behavior that may be exploited by attackers. A way of dealing with this problem is to remove an essential capability for most advanced attacks, Turing completeness. That is, a piece of software is provided the ability to specify that it does not need Turing completeness (i.e., backward computation) in order to perform a given task such as parsing. During this stage, attackers are prevented from abusing the system by performing, for example, return oriented programming.
    Type: Grant
    Filed: December 29, 2016
    Date of Patent: September 24, 2019
    Assignee: Intel Corporation
    Inventor: Rodrigo R. Branco
  • Patent number: 10423474
    Abstract: Arrangements described herein relate to performing diagnostic tracing of an executing application. A trace entry in trace data can be identified, the trace entry comprising a pointer that refers to a memory address. Whether a value that is, or has been, stored at the memory address is an erroneous value can be determined. Responsive to determining that the value that is, or has been, stored at the memory address is an erroneous value, the pointer can be indicated as being a suspicious value.
    Type: Grant
    Filed: July 29, 2015
    Date of Patent: September 24, 2019
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Stephen John Burghard, David J. Harman, Neil W. Leedham, Andrew Wright
  • Patent number: 10387191
    Abstract: A task processor includes a CPU, a save circuit, and a task control circuit. A task control circuit is provided with a task selection circuit and state storage units associated with respective tasks. When executing a predetermined system call instruction, the CPU notifies the task control circuit accordingly. When informed of the execution of a system call instruction, the task control circuit selects a task to be subsequently executed in accordance with an output from the selection circuit. When an interrupt circuit receives a high-speed interrupt request signal, the task switching circuit controls the state transition of a task by executing an interrupt handling instruction designated by the interrupt circuit.
    Type: Grant
    Filed: August 22, 2017
    Date of Patent: August 20, 2019
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventor: Naotaka Maruyama