Specialized Instruction Processing In Support Of Testing, Debugging, Emulation Patents (Class 712/227)
  • Patent number: 10983947
    Abstract: A method and system for enabling persistence of a value by a dynamically reconfigurable processor (“DRP”) from the time of execution of an earlier executed instruction to a time of later executed instruction. The value may represent a constant a variable value of a software program. The value may be read from or written into a memory circuit, a DRP logic element, an iterator of a DRP logic element, or other value storing element or aspect of the DRP. The value may be maintained in a single logic element through the duration of one or more instruction execution cycles, or alternatively or additionally, the value may be transferred between or among one or more value storage hardware elements. The persistence of the value and transfer of the value within, into and/or out of the DRP enables later access of the value by, and/or positioning the value within, the DRP.
    Type: Grant
    Filed: September 11, 2013
    Date of Patent: April 20, 2021
    Inventor: Robert Keith Mykland
  • Patent number: 10983697
    Abstract: A method includes, in one non-limiting embodiment, sending a request from a mass memory storage device to a host device, the request being one to allocate memory in the host device; writing data from the mass memory storage device to allocated memory of the host device; and subsequently reading the data from the allocated memory to the mass memory storage device. The memory may be embodied as flash memory, and the data may be related to a file system stored in the flash memory. The method enables the mass memory storage device to extend its internal volatile RAM to include RAM of the host device, enabling the internal RAM to be powered off while preserving data and context stored in the internal RAM.
    Type: Grant
    Filed: May 25, 2018
    Date of Patent: April 20, 2021
    Assignee: Memory Technologies LLC
    Inventors: Olli Luukkainen, Kimmo Mylly, Jani Hyvonen
  • Patent number: 10970070
    Abstract: An apparatus has processing circuitry to perform, in response to decoding of an iterative-operation instruction by the instruction decoder, an iterative operation comprising at least two iterations of processing where one iteration depends on an operand generated in a previous iteration. Preliminary information generating circuitry performs a preliminary portion of processing for a given iteration to generate preliminary information. Result generating circuitry performs a remaining portion of processing for the given iteration, to generate a result value using the preliminary information. Forwarding circuitry forwards the result value as an operand for a next iteration of the iterative operation, for iterations other than the final iteration. The preliminary information generating circuitry starts performing the preliminary portion for the next iteration in parallel with the result generating circuitry completing the remaining portion for the current iteration, to improve performance.
    Type: Grant
    Filed: March 29, 2019
    Date of Patent: April 6, 2021
    Assignee: Arm Limited
    Inventors: Nicholas Andrew Pfister, Srinivas Vemuri, David Raymond Lutz
  • Patent number: 10956311
    Abstract: Provided are systems, methods, and media for concurrency conflict testing for shared resources. An example method includes identifying shared resources that are to be accessed by an application. Generating a plurality of concurrency test scenarios based on the shared resources. Analyzing a plurality of concurrency test cases to detect which concurrency test cases include a reference to the shared resources. Executing a concurrency test scenario.
    Type: Grant
    Filed: July 24, 2019
    Date of Patent: March 23, 2021
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Li Li, Li Xiang, Chang Zhi GZ Zhang, Ting Xie, Xin Zheng, Yan Wang, Hai He, Si Bin Fan
  • Patent number: 10942945
    Abstract: Techniques are described herein for isolating runtime environments in a multitenant container DBMS. A CDB may contain a database dictionary that defines a plurality of pluggable databases and a respective database nest for each pluggable database. Each respective database nest of said each pluggable database is associated with different operating system privileges. When database sessions are established on a container DBMS, each database session is given access to a pluggable database by attaching the respective database nest of the pluggable database to each database session.
    Type: Grant
    Filed: October 19, 2018
    Date of Patent: March 9, 2021
    Assignee: ORACLE INTERNATIONAL CORPORATION
    Inventors: Santosh Shilimkar, Nagarajan Muthukrishnan, Ravi Thammaiah, Sumanta Chatterjee, Binoy Sukumaran
  • Patent number: 10904238
    Abstract: Techniques are described for managing access tokens in a computing environment. A proxy service can be configured to issue a first token to a workflow engine, the first token having a substantially unlimited lifetime to not time out during the workflow duration. The first token may be provided to the workflow in place of a shorter-lifetime token that may have otherwise been requested from a backend service. The first token may be used by the workflow engine to provide authorization for operations of the workflow. On completion of the workflow, the workflow engine may send an indication to the proxy service to request interactions with the backend service. The proxy service may request a second (e.g., limited-lifetime) token from the backend service, and use the second token to interact with the backend service on behalf of the workflow, thus acting as an intermediary between the workflow and the backend service.
    Type: Grant
    Filed: July 13, 2018
    Date of Patent: January 26, 2021
    Assignee: SAP SE
    Inventor: Krassimir Kondarev
  • Patent number: 10896081
    Abstract: A method and a circuit for implementing single event upset (SEU) parity detection, and a design structure on which the subject circuit resides are provided. The circuit implements detection of unwanted state changes due to SEUs, noise or other event in a latch having a default state of zero. The latch includes an L1 latch and an L2 latch with the L2 latch having the connected output and is used and monitored for a flip. A pair of series-connected field effect transistors (FETs) is connected between a drive input of a parity control circuit and ground potential. An inverted output of the L1 latch and a true output of the L2 latch is applied to a respective gate of the pair of series-connected FETs.
    Type: Grant
    Filed: December 13, 2018
    Date of Patent: January 19, 2021
    Assignee: International Business Machines Corporation
    Inventors: David D. Cadigan, William V. Huott, Anuwat Saetow, Adam J. McPadden
  • Patent number: 10885015
    Abstract: Systems, methods, and products for database system transaction management are provided herein. One aspect provides for annotating via a computing device at least one data object residing on the computing device utilizing at least one transaction tag, the at least one transaction tag being configured to indicate a status of an associated data object; processing at least one database transaction utilizing a transactional memory process, wherein access to the at least one data object is determined based on the status of the at least one data object; and updating the status of the at least one data object responsive to an attempted access of the at least one data object by the at least one database transaction. Other embodiments and aspects are also described herein.
    Type: Grant
    Filed: December 21, 2017
    Date of Patent: January 5, 2021
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Harold Wade Cain, III, Donna N. Dillenberger, Michel H. T. Hack, Hong Min, Gong Su, James Zu-Chia Teng
  • Patent number: 10821958
    Abstract: A computation unit having at least one computation core, a primary memory device, and at least one main connecting unit for connecting the at least one computation core to the primary memory device, the computation unit having at least two functional units, at least a first functional unit of the at least two functional units being embodied a) to receive first data from at least one further functional unit of the at least two functional units, and/or b) to transmit second data to at least one further functional unit of the at least two functional units.
    Type: Grant
    Filed: June 8, 2018
    Date of Patent: November 3, 2020
    Assignee: Robert Bosch GmbH
    Inventors: Matthias Schreiber, Axel Aue, Nico Bannow
  • Patent number: 10754953
    Abstract: The present invention provides a TrustZone-based security isolation system for shared library, the system at least comprising: a sandbox creator, a library controller, and an interceptor, the sandbox creator, in a normal world, dynamically creating a sandbox isolated from a Rich OS, the interceptor, intercepting corresponding system-calling information and/or Android framework APIs by means of inter-process stack inspection, the library controller, performing analysis based on the intercepted system-calling information and/or Android framework APIs, redirecting a library function to the sandbox, and switching calling states of the library function in the sandbox as well as setting up a library authority. The present invention has good versatility, low cost and high security. It realizes isolation of the library without increasing the trusted bases in the Secure World of the TrustZone, effectively reducing the risk of being attacked.
    Type: Grant
    Filed: August 23, 2018
    Date of Patent: August 25, 2020
    Assignee: Huazhong University of Science and Technology
    Inventors: Hai Jin, Weiqi Dai, Jun Deng, Deqing Zou
  • Patent number: 10747645
    Abstract: Expressly turning tracing on and off at each juncture between code that a developer wants to have traced and other code may reduce trace file size but adds computational cost. Described technologies support selectively tracing a process's execution, with some extra tracing done beyond the code the developer wanted traced, but with significantly reduced computational cost, by reducing the number of trace enablement and disablement operations. A trace controller uses a tracing disablement distance variable whose values indicate the computational distance from trace disablement. A distance variable modifier automatically moves the distance variable closer to a stop-tracing value as the process executes. The amount of extra tracing is balanced against the reduction in trace enablement/disablement operations by tuning thresholds, based on information about routine size and computational cost.
    Type: Grant
    Filed: April 27, 2018
    Date of Patent: August 18, 2020
    Assignee: MICROSOFT TECHNOLOGY LICENSING, LLC
    Inventors: Del Myers, Jackson Davis, Thomas Lai, Patrick Nelson, Jordi Mola, Juan Carlos Arevalo Baeza
  • Patent number: 10740219
    Abstract: Described technologies support selectively tracing a process's execution, with some extra tracing done beyond the code the developer wanted traced, but with significantly reduced computational cost, by reducing the number of trace enablement and disablement operations. A trace controller uses a tracing disablement distance variable whose values indicate the computational distance from trace disablement. A distance variable modifier automatically moves the distance variable closer to a stop-tracing value as the process executes. A create task function is modified to include the setting of an indicator that a newly created task is to be traced if a current task or thread is being traced. An execute task function is modified to request the tracing of the newly created task when it is executed based on the indicator, thereby enabling selective tracing that operates across process boundaries and traces asynchronous code execution.
    Type: Grant
    Filed: October 29, 2018
    Date of Patent: August 11, 2020
    Assignee: WORKMAN NYDEGGER
    Inventors: Del Myers, Thomas Lai, Patrick Nelson, Jordi Mola, Juan Carlos Arevalo Baeza, Stephen Harris Toub
  • Patent number: 10691576
    Abstract: An integrated circuit can include a functional unit and a local debug unit. The local debug unit can include a trace buffer, and the local debug unit is configured to track and store operation information of the functional unit in the trace buffer. The integrated circuit can also include a global debug unit coupled to the local debug unit. The integrated circuit is configured to send a debug reset command to reset the functional unit, without sending the debug reset command to the local debug unit, thereby retaining information stored in the trace buffer. The integrated circuit is also configured to send a power-up reset command to reset the local debug unit and the functional unit, thereby causing the local debug unit to clear the trace buffer.
    Type: Grant
    Filed: September 26, 2017
    Date of Patent: June 23, 2020
    Assignee: Amazon Technologies, Inc.
    Inventors: Yaniv Shapira, Gil Stoler, Adi Habusha
  • Patent number: 10636112
    Abstract: A processing apparatus is described. The apparatus includes a graphics processing unit (GPU), including a plurality of execution units to process graphics context data and a register file having a plurality of registers to store the graphics context data; and register renaming logic to facilitate re-use of register data by partitioning a first part and a second part, the first part to include thread-independent code and the second part to include thread-dependent code.
    Type: Grant
    Filed: March 28, 2018
    Date of Patent: April 28, 2020
    Assignee: Intel Corporation
    Inventors: Slawomir Grajewski, Kaiyu Chen, Guei-Yuan Lueh, Subramaniam Maiyuran
  • Patent number: 10628335
    Abstract: Processing circuitry 2 includes data storage circuitry 18 for storing one or more ordered sets of data entries. Access control circuitry 20 controls access during a given access cycle to a given ordered set of data entries in dependence upon, for that given set of data entries, a head-entry flag, a next-following-entry flag and preceding-cycle data. The head-entry flag indicates the oldest data entry for the given ordered set, the next-following-entry flag indicates the next oldest entry and the preceding-cycle flag indicates whether the given ordered set was accessed during a preceding access cycle. If the given ordered set was accessed during the preceding access cycle, then the next-following entry corresponding to the next-following flag is accessed during the current access cycle instead of that indicated by the head flag.
    Type: Grant
    Filed: July 18, 2018
    Date of Patent: April 21, 2020
    Assignee: ARM Limited
    Inventors: Jaume Cabecerans Betran, Eduard Vardanyan
  • Patent number: 10606498
    Abstract: A method for managing a discontinuous call stack is disclosed to more efficiently use the memory of devices without a memory management unit.
    Type: Grant
    Filed: December 23, 2016
    Date of Patent: March 31, 2020
    Assignee: Arm IP Limited
    Inventors: James Crosby, Brendan James Moran
  • Patent number: 10585668
    Abstract: A process for processor testing includes generating a set of test instructions having a first portion and a second portion. A first branch instruction is randomly generated for the first portion where the first branch instruction branches to a respective instruction in a second portion by a branching location offset. A second branch instruction is randomly generated for the second portion where the second branch instruction branches to a respective instruction in the first portion by the branching location offset. If additional instructions are to be added to the set of test instructions, a value of the branching location offset is incrementing by a predetermined amount.
    Type: Grant
    Filed: October 2, 2017
    Date of Patent: March 10, 2020
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Abhishek Bansal, Nitin P. Gupta, Brad L. Herold, Jayakumar N. Sankarannair
  • Patent number: 10572233
    Abstract: Provided is a vectorization device 30 comprising: a unit 31 that detects a configuration in which the inner loop length depends on the outer loop variable, and in which a first array indicating the results of dual-loop processing does not contain the inner loop variable as an index value; an unit 32 that, when the configuration is detected, determines a fixed value as the inner loop length; an unit 33 that expands the array size of a second array used in the calculation of the first array value, and thereby enables dual-loop processing of the inner loop; an unit 34 that sets an element value for an added element of the second array, and thereby, before and after such processing is carried out, enables the results of the dual-loop processing to be made equal; and an unit 35 that updates the software on the basis of such processing results.
    Type: Grant
    Filed: November 17, 2016
    Date of Patent: February 25, 2020
    Assignee: NEC CORPORATION
    Inventor: Yoshiyuki Ohno
  • Patent number: 10564962
    Abstract: An electronic circuit (4000) includes a bias value generator circuit (3900) operable to supply a varying bias value in a programmable range, and an instruction circuit (3625, 4010) responsive to a first instruction to program the range of the bias value generator circuit (3900) and further responsive to a second instruction having an operand to repeatedly issue the second instruction with the operand varied in an operand value range determined as a function of the varying bias value.
    Type: Grant
    Filed: November 19, 2018
    Date of Patent: February 18, 2020
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Kenichi Tashiro, Hiroyuki Mizuno, Yuji Umemoto
  • Patent number: 10558806
    Abstract: A processor receives a signal and determines whether an application has registered a signal handler therewith for handling the signal. In response to determining that the application has registered the signal handler, the processor transmits the signal directly to the signal handler of the application for handling the signal, without an operating system in relation to which the trusted application is running intervening. In response to determining that the trusted application has not registered the signal handler, the processor transmits the signal to a signal handler of the operating system for handling the signal.
    Type: Grant
    Filed: December 13, 2016
    Date of Patent: February 11, 2020
    Assignee: International Business Machines Corporation
    Inventors: Andrew D. Hilton, Brian M. Rogers
  • Patent number: 10509906
    Abstract: In an example embodiment, a system determines a set of instructions from the available instructions for a computer application. The determined set of instructions provides specific functionality of the computer application. The system may determine the set of instructions by performing functional testing and negative testing on the specific functionality. The system may reorganize and randomize the set of instructions in memory and write the reorganized set of instructions to a smaller memory space. For each available instruction not in the set of instructions, the system changes the respective instruction to inoperative to prevent execution of the respective instruction. The system may change the respective instruction to inoperative by overwriting the instruction with a NOP instruction. The system then captures a memory address of the computer application being accessed at runtime.
    Type: Grant
    Filed: July 10, 2017
    Date of Patent: December 17, 2019
    Assignee: Virsec Systems, Inc.
    Inventor: Satya Vrat Gupta
  • Patent number: 10503479
    Abstract: Examining source code repositories for indications of orthogonal technologies in actual use or of potential usefulness in the development and continuous delivery of the contents of the repositories.
    Type: Grant
    Filed: May 7, 2018
    Date of Patent: December 10, 2019
    Assignee: International Business Machines Corporation
    Inventors: Christopher Brealey, Christopher Taylor, Joel Cayne, Philippe Mulet, Ritchard L. Schacher, Thomas C. Schmidt
  • Patent number: 10496405
    Abstract: Embodiments of the present invention are directed to a computer-implemented method for generating and verifying hardware instruction traces including memory data contents. The method includes initiating an in-memory trace (IMT) data capture for a processor, the IMT data being an instruction trace collected while instructions flow through an execution pipeline of the processor. The method further includes capturing contents of architected registers of the processor by: storing the contents of the architected registers to a predetermined memory location, and causing a load-store unit (LSU) to read contents of the predetermined memory location.
    Type: Grant
    Filed: November 20, 2017
    Date of Patent: December 3, 2019
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Jane H. Bartik, Christian Jacobi, David Lee, Jang-Soo Lee, Anthony Saporito, Christian Zoellin
  • Patent number: 10484361
    Abstract: In accordance with disclosed embodiments, there are provided systems, methods, and apparatuses for implementing virtual device observation and debug network for high speed serial IOS.
    Type: Grant
    Filed: June 30, 2016
    Date of Patent: November 19, 2019
    Assignee: Intel Corporation
    Inventors: Lakshminarayana Pappu, Timothy J. Callahan, Baruch Schnarch, Hem Doshi, Suketu U. Bhatt
  • Patent number: 10467114
    Abstract: A hierarchical data processor test system (and method) is usable to configure a hierarchical plurality of similarity operators and process predetermined input test data through a data processor under test (DPUT) to produce corresponding DPUT output data. The test system is further usable to process the DPUT output data and the predetermined output test data through at least some of the plurality of similarity operators in hierarchical order, determine a highest order similarity operator that indicates a match between the DPUT output data and the predetermined output test data, and compute a confidence score based on the highest order similarity operator that indicated the match. Based on the confidence score exceeding a threshold, the test system also may include activating the DPUT for use by non-test data.
    Type: Grant
    Filed: July 14, 2016
    Date of Patent: November 5, 2019
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Neil S. Bhargava, Freddys M. Espinoza, Stefan A. Gert Van Der Stockt
  • Patent number: 10445133
    Abstract: A method for managing thread execution in a processing system is provided. The method includes setting a first watchpoint, and generating a first watchpoint trigger corresponding to the first watchpoint. In response to the first watchpoint trigger, execution of a first thread is controlled in accordance with a value stored in a first control register. Controlling the first thread may further include disabling execution of the first thread. The disabling execution of the first thread may occur within the first watchpoint region.
    Type: Grant
    Filed: March 4, 2016
    Date of Patent: October 15, 2019
    Assignee: NXP USA, Inc.
    Inventors: Jonathan J. Gamoneda, Jehoda Refaeli, Jeffrey W. Scott
  • Patent number: 10423474
    Abstract: Arrangements described herein relate to performing diagnostic tracing of an executing application. A trace entry in trace data can be identified, the trace entry comprising a pointer that refers to a memory address. Whether a value that is, or has been, stored at the memory address is an erroneous value can be determined. Responsive to determining that the value that is, or has been, stored at the memory address is an erroneous value, the pointer can be indicated as being a suspicious value.
    Type: Grant
    Filed: July 29, 2015
    Date of Patent: September 24, 2019
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Stephen John Burghard, David J. Harman, Neil W. Leedham, Andrew Wright
  • Patent number: 10423778
    Abstract: Described herein are techniques for dealing with the problem of security vulnerabilities in computer software due to undefined behavior that may be exploited by attackers. A way of dealing with this problem is to remove an essential capability for most advanced attacks, Turing completeness. That is, a piece of software is provided the ability to specify that it does not need Turing completeness (i.e., backward computation) in order to perform a given task such as parsing. During this stage, attackers are prevented from abusing the system by performing, for example, return oriented programming.
    Type: Grant
    Filed: December 29, 2016
    Date of Patent: September 24, 2019
    Assignee: Intel Corporation
    Inventor: Rodrigo R. Branco
  • Patent number: 10387191
    Abstract: A task processor includes a CPU, a save circuit, and a task control circuit. A task control circuit is provided with a task selection circuit and state storage units associated with respective tasks. When executing a predetermined system call instruction, the CPU notifies the task control circuit accordingly. When informed of the execution of a system call instruction, the task control circuit selects a task to be subsequently executed in accordance with an output from the selection circuit. When an interrupt circuit receives a high-speed interrupt request signal, the task switching circuit controls the state transition of a task by executing an interrupt handling instruction designated by the interrupt circuit.
    Type: Grant
    Filed: August 22, 2017
    Date of Patent: August 20, 2019
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventor: Naotaka Maruyama
  • Patent number: 10379998
    Abstract: According to one or more embodiments a computer-implemented method includes detecting, by a processor, an instruction to capture runtime data of a set of instructions in a computer program, the instruction detected based on a hook associated with the set of instructions. The method further includes determining whether the hook is an active expiring hook. The method further includes in response to the hook being an active expiring hook, determining a time condition associated with the expiring hook. The method further includes in response to the time condition being met, capturing the runtime data of the set of instructions in the computer program.
    Type: Grant
    Filed: November 6, 2017
    Date of Patent: August 13, 2019
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Francisco M. Anaya, Seana Hogan, Trong Truong
  • Patent number: 10379997
    Abstract: According to one or more embodiments a computer-implemented method includes detecting, by a processor, an instruction to capture runtime data of a set of instructions in a computer program, the instruction detected based on a hook associated with the set of instructions. The method further includes determining whether the hook is an active expiring hook. The method further includes in response to the hook being an active expiring hook, determining a time condition associated with the expiring hook. The method further includes in response to the time condition being met, capturing the runtime data of the set of instructions in the computer program.
    Type: Grant
    Filed: September 19, 2017
    Date of Patent: August 13, 2019
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Francisco M. Anaya, Seana Hogan, Trong Truong
  • Patent number: 10339229
    Abstract: Aspects of the present invention describe a system and method for providing a single integrated simulation interface running in a single host operating system (OS) thread to observe and control multiple, disparate software and hardware components. Control mechanisms of the present invention provide access to each of the modeled components, including the hardware models, the embedded software components modeled on the bare-hardware elements, and the software applications, processes and threads which are themselves running on embedded software.
    Type: Grant
    Filed: May 31, 2013
    Date of Patent: July 2, 2019
    Assignee: CADENCE DESIGN SYSTEMS, INC.
    Inventors: Andrew Wilmot, William W. LaRue, Jr., Neeti Bhatnagar, Dave Von Bank, Joshua Levine
  • Patent number: 10338135
    Abstract: Methods and apparatus are disclosed for programming reconfigurable logic devices such as FPGAs in a multi-tenant server environment. In one example, a computing host includes one or more processors configured to execute a supervisor process and two or more user processes and a single FPGA integrated circuit configured into a plurality of partitions. The partitions include a host logic partition that is accessible only to the supervisor process executing on the computing host, and two or more accelerator partitions. Each of the accelerator partitions is configured to include a virtual debug unit with a logic analyzer that collects logic signals generated by logic within the respective accelerator partition and sends debug data indicating values of the logic signals to one of the user processes. In some examples, the host logic partitions and/or the accelerator partitions can be independently reprogrammed of each other within their respective portions of the single FPGA.
    Type: Grant
    Filed: September 28, 2016
    Date of Patent: July 2, 2019
    Assignee: Amazon Technologies, Inc.
    Inventors: Mark Bradley Davis, Christopher Joseph Pettey, Asif Khan, Islam Mohamed Hatem Abdulfattah Mohamed Atta
  • Patent number: 10331452
    Abstract: In accordance with embodiments disclosed herein, there is provided systems and methods for tracking the mode of processing devices in an instruction tracing system. The method may include receiving an indication of a change in a current execution mode of the processing device. The method may also include determining that the current execution mode of the received indication is different than a value of an execution mode of a first execution mode (EM) packet previously-generated by the IT module. The method may also include generating, based on the determining that the current execution mode is different, a second EM packet that provides a value of the current execution mode of the processing device to indicate the change in the execution mode for an instruction in a trace generated by the IT module. The method may further include generating transactional memory (TMX) packets having n bit mode pattern in the packet log. The n is at least two and the n bit mode indicates transaction status of the TMX operation.
    Type: Grant
    Filed: June 27, 2013
    Date of Patent: June 25, 2019
    Assignee: Intel Corporation
    Inventors: Thilo Schmitt, Peter Lachner, Beeman Strong, Ofer Levy, Thomas Toll, Matthew Merten, Tong Li, Ravi Rajwar, Konrad Lai
  • Patent number: 10318356
    Abstract: Operation of a multi-slice processor that includes execution slices and a dispatch network of the multi-slice processor implementing a hardware level transfer of an execution thread between execution slices. Operation of such a multi-slice processor includes responsive to a thread switch signal: halting dispatch of one or more instructions retrieved from an instruction cache; generating a plurality of instructions to transfer an execution thread from a first execution slice to a second execution slice; and dispatching the plurality of instructions instead of the one or more instructions retrieved from the instruction cache; and transferring, in dependence upon execution of the plurality of instructions from the thread switching instruction generator, the execution thread from the first execution slice to the second execution slice.
    Type: Grant
    Filed: March 31, 2016
    Date of Patent: June 11, 2019
    Assignee: International Business Machines Corporation
    Inventors: Brian D. Barrick, James W. Bishop, Marcy E. Byers, Sundeep Chadha, Cliff Kucharski, Dung Q. Nguyen, David R. Terry, Jing Zhang
  • Patent number: 10318790
    Abstract: Techniques relate to fingerprint-based processor malfunction detection. A determination is made whether a fingerprint is present in software that is currently executing on the processor of the computer system. The fingerprint includes a representation of a sequence of behavior that occurs on the processor while the software is executing. The fingerprint corresponds to a type of malfunction. In response to determining that the fingerprint is not present in the software currently executing on the processor, monitoring of the software executing on the processor to determine whether the fingerprint is present continues. In response to determining that the fingerprint is present in the software executing on the processor, it is determined that the malfunction has occurred according to a type of the fingerprint that is present.
    Type: Grant
    Filed: December 14, 2016
    Date of Patent: June 11, 2019
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Giles R. Frazier, Michael Karl Gschwind, Christian Jacobi, Anthony Saporito, Chung-Lung K. Shum
  • Patent number: 10319455
    Abstract: A semiconductor device includes a delay selection signal generation circuit, an internal read signal generation circuit, and an internal write signal generation circuit. The delay selection signal generation circuit generates a delay selection signal in response to an information code signal. The internal read signal generation circuit generates an internal read signal from a mask write signal in response to the delay selection signal and a clock. The internal write signal generation circuit delays the mask write signal by a predetermined delay period to generate an internal write signal.
    Type: Grant
    Filed: July 3, 2017
    Date of Patent: June 11, 2019
    Assignee: SK HYNIX INC.
    Inventors: Yong Mi Kim, Jae Il Kim
  • Patent number: 10310862
    Abstract: Data processing circuitry comprises out-of-order instruction execution circuitry to execute program instructions in an instruction execution order; a data store, to store information on a set of instructions for which execution has been initiated, the data store providing ordering information indicating the relative position of each instruction in the set of instructions with respect to a program code order; commit circuitry to commit the results of instructions executed by the instruction execution circuitry; one or more cumulative status registers configured to be set in response to a respective condition generated by execution of an instruction and then to remain set until an unset instruction is executed; and an identifier store, to store for at least those of the one or more cumulative status registers which are not currently set, an identifier of an instruction which is earliest in the program code order in the set of instructions and which generated a condition to set that cumulative status register.
    Type: Grant
    Filed: March 21, 2017
    Date of Patent: June 4, 2019
    Assignee: ARM Limited
    Inventors: Robert Greg McDonald, Michael Filippo, Glen Andrew Harris
  • Patent number: 10305919
    Abstract: In accordance with some embodiments of the present invention, systems and methods that protect an application from attacks are provided. In some embodiments of the present invention, input from an input source, such as traffic from a communication network, can be routed through a filtering proxy that includes one or more filters, classifiers, and/or detectors. In response to the input passing through the filtering proxy to the application, a supervision framework monitors the input for attacks (e.g., code injection attacks). The supervision framework can provide feedback to tune the components of the filtering proxy.
    Type: Grant
    Filed: May 9, 2016
    Date of Patent: May 28, 2019
    Assignee: The Trustees of Columbia University in the City of New York
    Inventors: Michael E. Locasto, Salvatore J. Stolfo, Angelos D. Keromytis, Ke Wang
  • Patent number: 10296476
    Abstract: A method of profiling transactions on an integrated circuit chip. The method comprises, for each transaction: extracting the transaction from interconnect circuitry of the integrated circuit chip; and filtering the transaction at a filtering circuit to determine which passband a parameter of the transaction lies within; sending an increment signal to a counter of a bank of counters, the counter having a counter value indicative of a number of transactions having the parameter lying within the passband; and outputting the counter values of the bank of counters.
    Type: Grant
    Filed: August 12, 2016
    Date of Patent: May 21, 2019
    Assignee: UltraSoC Technologies Limited
    Inventors: Andrew Brian Thomas Hopkins, Michael Jonathan Thyer, Iain Craig Robertson
  • Patent number: 10289411
    Abstract: A debugging and diagnostics system allow for dynamic code generation that inserts code into a production application to identify snappoints or breakpoints that cause snapshots to be taken if predefined conditionals are satisfied. The snappoints are associated with locations in source code for the production application and include conditional statements that must be met to create a snapshot of the production application. The snappoints are used to generate a collection plan that is provided to the server running the production application. The server rewrites the code of the production application based upon the collection plan to insert instructions that create snapshots when the conditional statements are met.
    Type: Grant
    Filed: November 18, 2013
    Date of Patent: May 14, 2019
    Assignee: Microsoft Technology Licensing, LLC
    Inventor: Jackson Davis
  • Patent number: 10282276
    Abstract: Techniques relate to fingerprint-initiated trace extraction. A determination is made of whether a fingerprint is present in software that is currently executing on a processor of a computer system. The fingerprint comprises a representation of a sequence of behavior that occurs in the processor while the software is executing. In response to determining that the fingerprint is not present in the software currently executing on the processor, monitoring continues for the software executing on the processor to determine whether the fingerprint is present. In response to determining that the fingerprint is present in the software executing on the processor, a trace is triggered of a code segment of the software corresponding to when the fingerprint is recognized. The trace is for a record of instructions of the code segment of the software.
    Type: Grant
    Filed: January 16, 2017
    Date of Patent: May 7, 2019
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Jonathan D. Bradbury, Giles R. Frazier, Michael Karl Gschwind, Christian Jacobi, Anthony Saporito, Chung-Lung K. Shum
  • Patent number: 10275242
    Abstract: An apparatus and method are described for real time instruction tracing. For example, a method according to one embodiment comprises: recording user specified address ranges for which tracing is required; monitoring a next linear instruction pointer (NLIP) values and/or branch linear instruction pointer (BLIP) values to determine if address range has been entered; when the range is entered, compressing the NLIP and/or BLIP values and constructing fixed length packets containing the tracing data; and transferring the fixed length packets to a memory execution cluster.
    Type: Grant
    Filed: March 30, 2012
    Date of Patent: April 30, 2019
    Assignee: Intel Corporation
    Inventors: Huy V. Nguyen, Jason W. Brandt, Jonathan J. Tyler
  • Patent number: 10277246
    Abstract: The present invention provides a program counter compression method and a hardware circuit thereof. The compression method of the present invention includes the following steps: step (1), acquiring execution condition of instructions sent by a processor and classifying and screening said instructions based on said execution condition of the instructions; step (2), executing differential operation on instruction count values of the objective classification and the stall periods based on the classifying and screening result and splicing the obtained differential values; step (3), dictionary encoding the valid differential slicing data segments recorded in step (2). The present invention effectively combines the architecture compression and non-architecture compression and proposes a three-stage compression scheme by organizing and applying classifying and screening, differential encoding and dictionary compression, which drastically increases the compression ratio of the program counter.
    Type: Grant
    Filed: February 17, 2017
    Date of Patent: April 30, 2019
    Assignee: HEFEI UNIVERSITY OF TECHNOLOGY
    Inventors: Duoli Zhang, Bin Zhang, Yukun Song, Can Wei
  • Patent number: 10275335
    Abstract: Described is a computer-implemented method of reordering condition checks. Two or more condition checks in computer code that may be reordered within the code are identified. It is determined that the execution frequency of a later one of the condition checks is satisfied at a greater frequency than a preceding one of the condition checks. It is determined that there is an absence of side effects in the two or more condition checks. The values of the condition checks are propagated and abstract interpretation is performed on the values that are propagated. It is determined that the condition checks are exclusive of each other, and the condition checks are reordered within the computer code.
    Type: Grant
    Filed: September 15, 2017
    Date of Patent: April 30, 2019
    Assignee: International Business Machines Corporation
    Inventors: Takuya Nakaike, Takeshi Ogasawara
  • Patent number: 10192049
    Abstract: Systems, methods, and media for detecting the presence of return-oriented programming (ROP) payloads are provided, comprising: identifying a potential gadget address space; determining if a piece of the data corresponds to an address of the potential gadget address space; and in response to determining that the piece of the data corresponds to an address of the potential gadget address space: determining whether a plurality of operations, each associated one of a plurality instructions beginning at the address, indicates that an ROP payload is present in the data, and indicating that an ROP payload is present in the data in response to making a determination that a plurality of operations indicates that an ROP payload is present in the data a given number of times.
    Type: Grant
    Filed: November 11, 2016
    Date of Patent: January 29, 2019
    Assignee: The Trustees of Columbia University in the City of New York
    Inventors: Michalis Polychronakis, Angelos D. Keromytis
  • Patent number: 10176077
    Abstract: A computer implemented method for selecting breakpoints for cross-layer debugging is provided. The method includes receiving code comprising a plurality of layers, and executing a static analysis of the code to obtain a use-definition (UD) chain, alias information, and a parameter mapping for each of the plurality of layers. The method also includes determining a statement of the code that produces one of an error and a failure, and generating a table comprising a plurality of fields including a working statement field, watching variable field, and a watching function field. The method includes adding the determined statement to the working statement field and performing a cross-layer analysis includes identifying at least one used variable and its associated alias as watching variables from the added working statement, searching the code based on the watching variable field. The method includes generating cross-layer suspect code points based on the cross-layer analysis.
    Type: Grant
    Filed: February 16, 2017
    Date of Patent: January 8, 2019
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Si Bin Fan, Xiao Feng Guan, Chen Jiang, Yan Rong Shen, Chang Ning Song, Ping Xiao
  • Patent number: 10169194
    Abstract: Systems, methods and tools for identifying potential errors or inconsistencies occurring during the runtime of multi-threaded applications and reporting the errors to a user, administrator or developer for correction and adjustments to the program code or thread timings. Embodiments of the disclosure capture thread sequences during a runtime or simulation environment and store the thread sequences as a matrix or tabular representation in a file. Multi-threaded application runs having an error free thread sequence, may be used as benchmarks for identifying potential errors and mis-runs of variations to the multi-threaded application as changes occur to the application code or new threads are added to the application code. This comparison may be performed by comparing the captured thread sequences of both the passing run and the mis-run of the multi-threaded application for differences in the thread sequences that may have caused the mis-run to occur.
    Type: Grant
    Filed: March 22, 2017
    Date of Patent: January 1, 2019
    Assignee: International Business Machines Corporation
    Inventors: Vikas Chandra, Srinivasan S. Muthuswamy, Sarika Sinha
  • Patent number: 10162635
    Abstract: An apparatus includes a network interface, memory, and a processor. The processor is coupled with the network interface and memory. The processor is configured to determine that an instruction instance is a branch instruction instance. Responsive to a determination that an instruction instance is a branch instruction instance, the processor is configured to obtain a branch prediction for the branch instruction instance and a confidence value of the branch prediction. The processor is further configured to determine that the confidence for the branch prediction is low based on the confidence value, and responsive to such a determination, generate predicated instruction instances based on the branch instruction instance.
    Type: Grant
    Filed: May 17, 2016
    Date of Patent: December 25, 2018
    Assignee: International Business Machines Corporation
    Inventor: Michael Karl Gschwind
  • Patent number: 10152406
    Abstract: According to an aspect of an embodiment, one or more systems or methods may be configured to locate a fault in a software program using a test suite. The systems or methods may be further configured to modify, using a repair template, the software program in response to locating the fault. In addition, the systems or methods may be configured to determine whether the modification satisfies an anti-pattern condition. The anti-pattern condition may indicate whether the modification is improper. The systems or methods may also be configured to disallow the modification in response to the modification satisfying the anti-pattern condition or perform further testing on the software program, as modified, in response to the modification not satisfying the anti-pattern condition.
    Type: Grant
    Filed: August 25, 2015
    Date of Patent: December 11, 2018
    Assignee: FUJISTU LIMITED
    Inventors: Hiroaki Yoshida, Shin Hwei Tan, Mukul R. Prasad