Abstract: A processing apparatus having a programmable circuit including a plurality of ALUs, comprises a holding unit which holds configuration information for switching the programmable circuit from a first circuit setting to a second circuit setting, and timing information; and an updating unit which updates each ALU so as to switch the programmable circuit from the first circuit setting to the second circuit setting, wherein in switching from the first circuit setting to the second circuit setting after the programmable circuit has executed the first data processing, the updating unit, using the timing information, updates the first ALU at a timing at which last data of the first data processing is output from the first ALU, and updates the second ALU at a timing at which the last data is output from the second ALU.

Abstract: The system creates, in a scheduler data structure, a first entry for a consumer instruction associated with a logical register ID. The first entry includes: a scheduler entry ID; a physical register ID allocated for the logical register ID; a checkpoint ID; one or more scheduler entry IDs for one or more prior producer instructions; and a release field which indicates whether to early release a physical register. The system updates a register alias table entry to include the scheduler entry ID and the checkpoint ID of the consumer instruction. The system receives the scheduler entry ID and a checkpoint ID for a respective prior producer instruction. Responsive to determining that the received checkpoint ID does not match the checkpoint ID associated with the consumer instruction, the system sets a release field to indicate that a physical register is to remain allocated.

Abstract: An integrated circuit including control/configure circuitry which interfaces with a plurality of interconnected (e.g., serially) multiplier-accumulator circuits and/or one or more rows of interconnected (e.g., serially) multiplier-accumulator circuits. The control/configure circuitry may include a plurality of control/configure circuits, each control/configure circuit interfaces with at least one multi-bit MAC execution pipeline, wherein each pipeline includes a plurality of interconnected (e.g., serially) multiplier-accumulator circuits. Each control/configure circuit may include one or more (or all) of (i) a configurable input data signal path to provide data to the MACs of the pipeline during the execution sequence(s), (ii) a configurable accumulation data path for the ongoing/accumulating MAC accumulation totals generated by the MACs during an execution sequence, and (iii) a configurable output data path for the output data generated by execution sequence (i.e.

Abstract: In one embodiment, a method includes generating a handle that references a checkpoint for a service, sending the handle to the service, wherein the handle is configured to be used by the service to store one or more states of the service in the checkpoint, determining that the service needs to be restarted, restarting the service, accessing the handle for the checkpoint, and sending the handle for the checkpoint to the restarted service, wherein the handle for the checkpoint is configured to be used by the restarted service to restore the one or more states.

Abstract: In an apparatus (2) with transactional memory support, a predetermined type of transaction start instruction or a subsequent instruction following the predetermined type of transaction start instruction triggers capture of a lock identifier which identifies a lock variable for controlling exclusive access to at least one resource. In response to a predetermined type of transaction end instruction which follows the predetermined type of transaction start instruction, the lock variable is checked and commitment of results of speculatively executed instructions of the transaction is prevented or deferred when the lock variable indicates that another thread holds the exclusive access to the target resource. This approach can improve performance when executing transactions in a transactional memory based system.

Abstract: In accordance with an embodiment, a method verifies contents of a plurality of registers having two first registers, where each of the plurality of registers is configured to store a data word and a verification bit. The method includes determining whether a value of the verification bit of each respective register of the plurality of registers corresponds to the data word of its respective register. The data words stored in the two first registers are selected so that the bits of a same rank of the two first registers include two complementary bits, each bit of a common binary word is associated with a respective register of the plurality of registers, and the value of the verification bit of each respective register depends on the data word of the respective register and the bit of the common binary word associated with the respective register.

Abstract: A save and restore (SR) register system is disclosed. Some embodiments include a first memory state element (MSE), a second MSE, and a control circuit. The first MSE is configured to: clock in a first data value during a normal mode and hold the first data value during a first testing mode; and clock in a first test sequence during a second testing mode. The second MSE is configured to: clock in the first data value during the normal mode; and clock in a second test sequence during the first testing mode. The control circuit configured to: restore the second MSE to the first data value based on an output port of the first MSE after the second MSE clocks in the second test sequence; and restore the first MSE based on an output port of the second MSE after the first MSE clocks in the first test sequence.

Abstract: A receiving core reads a packet from an ingress interface, wherein the ingress interface is an interface corresponding to a forwarding group to which the receiving core belongs; the receiving core sends the read packet to a forwarding core in the forwarding group; and the forwarding core sends the packet to a corresponding egress interface.

Abstract: A system on a chip (SoC) includes a plurality of processing cores and a stream switch coupled to two or more of the plurality of processing cores. The stream switch includes a plurality of N multibit input ports, wherein N is a first integer, a plurality of M multibit output ports, wherein M is a second integer, and a plurality of M multibit stream links dedicated to respective output ports of the plurality of M multibit output ports. The M multibit stream links are reconfigurably coupleable at run time to a selectable number of the N multibit input ports, wherein the selectable number is an integer between zero and N.

Abstract: Memory controllers, devices, modules, systems and associated methods are disclosed. In one embodiment, an integrated circuit (IC) memory device is disclosed. The memory device includes an array of storage cells and command interface circuitry to receive an internal transfer command. In response to the internal transfer command, transfer logic reads data from a first portion of the array of storage cells, transfers the data as on-chip transfer data, and writes the on-chip transfer data to a second portion of the array of storage cells. In response to the command interface circuitry receiving an interrupt command, the transfer logic pauses the internal transfer operation, and carries out an unrelated memory access operation involving at least the first portion of the array of storage cells or the second portion of the array of storage cells.

Abstract: Aspects of the present disclosure relate to an apparatus comprising register circuitry implementing a plurality of registers and processing circuitry to perform data processing operations on data stored in said registers. The apparatus comprises store buffer circuitry to, responsive to a store instruction in respect of given data, temporarily store said given data prior to providing said given data to a memory. Responsive to receiving at the processing circuitry a request to perform a state-saving-triggering operation, the register circuitry is configured to capture in shadow registers of said register circuitry a state of a subset of registers of the plurality of registers, provide the captured state from the shadow registers to the memory.

Abstract: An example method of allocating memory pages for a guest includes receiving, by a hypervisor, a request to allocate a plurality of guest memory pages for a guest running on a virtual machine. The virtual machine and the hypervisor run on a host machine. The method also includes in response to the request: (i) allocating, by the hypervisor, a plurality of host memory pages, and (ii) mapping the plurality of guest memory pages to the plurality of host memory pages.

Abstract: The disclosed embodiments relate to system, method and apparatus to compartmentalize information in a program so as to protect against malware. In one embodiment, the disclosed provides a compiler that is enhanced to automatically define multiple compartments within a program based on the data sets that they access. The disclosed embodiments may be implemented at a compiler and certain embodiments may be referred to as compartmentalizing compiler. For each data set, an exemplary compartmentalizing compiler separates program elements that need direct access to the data set from those that do not and it defines a boundary around the data set and the program elements that need to access it. In certain embodiments, other portions of the program may still need to invoke the compartment. Thus, the disclosure also generates interface routines to copy data back and forth through the compartment boundary.

Abstract: Apparatuses and methods of data processing are disclosed for tagging instructions on-line. Instruction tag storage stores information indicative of a tag applied to certain instruction identifiers. A data processing operation performed by the data processing circuitry in response to an executed instruction is dependent on whether there is a corresponding instruction identifier for the executed instruction in the instruction tag storage which has the instruction tag. Register writer storage is maintained, and an entry is created for each register writing instruction encountered which causes a result value to be written to a destination register, where the entry comprises an indication of the destination register and the register writing instruction. An instruction tagging queue buffers instruction identifiers and an instruction identifier is added to the queue for a predetermined type of instruction when it is encountered.

Abstract: A process for processor management includes activating a delay thread running on a processor. A determination is made whether a wait event for a first thread running on the processor is in a queue. Responsive to determining that the wait event for the first thread is in the queue, a determination is made whether a wait time associated with the wait event has expired. Responsive to determining that the wait time has not expired, a determination is made if wait time exceeds a threshold. Responsive to determining that the wait time exceeds the threshold, a timer is set and a low power mode is initiated for the processor.

Abstract: An electronic device includes a wireless communication modem; a processor; a volatile memory configured to be operatively connected to the processor; and a non-volatile memory configured to store at least one application program and to be operatively connected to the processor. The non-volatile memory may be configured to store, when executed, instructions that cause the processor to transmit and receive first data packets to and from the communication modem and to provide a network device interface including at least one first parameter related to processing of the first data packets, to receive requirement information related to the operation of the application program, and to adjust values of the at least one first parameter based on at least a part of the requirement information, and cause the network device interface to transmit and receive the first data packets using at least some of the adjusted values of the first parameters.

Abstract: A system to implement debugging for a multi-threaded processor is provided. The system includes a hardware thread scheduler configured to schedule processing of data, and a plurality of schedulers, each configured to schedule a given pipeline for processing instructions. The system further includes a debug control configured to control at least one of the plurality of schedulers to halt, step, or resume the given pipeline of the at least one of the plurality of schedulers for the data to enable debugging thereof. The system further includes a plurality of hardware accelerators configured to implement a series of tasks in accordance with a schedule provided by a respective scheduler in accordance with a command from the debug control. Each of the plurality of hardware accelerators is coupled to at least one of the plurality of schedulers to execute the instructions for the given pipeline and to a shared memory.

Abstract: Systems and methods for an efficient and robust multiprocessor-coprocessor interface that may be used between a streaming multiprocessor and an acceleration coprocessor in a GPU are provided. According to an example implementation, in order to perform an acceleration of a particular operation using the coprocessor, the multiprocessor: issues a series of write instructions to write input data for the operation into coprocessor-accessible storage locations, issues an operation instruction to cause the coprocessor to execute the particular operation; and then issues a series of read instructions to read result data of the operation from coprocessor-accessible storage locations to multiprocessor-accessible storage locations.

Abstract: This data-processing device includes a unit for processing data, a storage memory and a buffer-memory device configured to contain a first group of data relative to a first context and exchange data between the processing unit and the first group of data. The buffer-memory device is further configured to contain a second group of data relative to a second context and, upon reception of a context-switching instruction, exchange data between the processing unit and the second group of data, in place of the first group of data. The data-processing device further includes a context-switching device configured to emit the context-switching instruction, select a group of data recorded in the storage memory, copy the first group of data to the storage memory and copy the selected group of data to the buffer-memory device.

Abstract: Examples are described here that can be used to enable a main routine to request subroutines or other related code to be executed with other instantiations of the same subroutine or other related code for parallel execution. A sorting unit can be used to accumulate requests to execute instantiations of the subroutine. The sorting unit can request execution of a number of multiple instantiations of the subroutine corresponding to a number of lanes in a SIMD unit. A call stack can be used to share information to be accessed by a main routine after execution of the subroutine completes.

Abstract: A processor of an aspect includes a decode unit to decode a matrix multiplication instruction. The matrix multiplication instruction is to indicate a first memory location of a first source matrix, is to indicate a second memory location of a second source matrix, and is to indicate a third memory location where a result matrix is to be stored. The processor also includes an execution unit coupled with the decode unit. The execution unit, in response to the matrix multiplication instruction, is to multiply a portion of the first and second source matrices prior to an interruption, and store a completion progress indicator in response to the interruption. The completion progress indicator to indicate an amount of progress in multiplying the first and second source matrices, and storing corresponding result data to the third memory location, that is to have been completed prior to the interruption.

Abstract: A system and corresponding method unwind instructions in an out-of-order (OoO) processor. The system comprises a mapper. In response to a restart event causing at least one instruction to be unwound, the mapper restores a present integer mapper state and present floating-point (FP) mapper state, used for mapping instructions, to a former integer mapper state and former FP mapper state, respectively. The mapper stores integer snapshots and FP snapshots of the present integer and FP mapper state, respectively, to expedite restoration to the former integer and FP mapper state, respectively. Access to the FP snapshots is blocked, intermittently, as a function of at least one FP present indicator used by the mapper to record presence of FP registers used as destinations in the instructions. Blocking the access, intermittently, improves power efficiency of the OoO processor.

Abstract: Disclosed are methods and systems, among which is a system that includes a pattern-recognition processor, a central processing unit (CPU) coupled to the pattern-recognition processor via a pattern-recognition bus, and memory coupled to the CPU via a memory bus. In some embodiments, the pattern-recognition bus and the memory bus form about the same number of connections to the pattern-recognition processor and the memory, respectively.

Abstract: A system and method may provide assistance to programmer during programming to detect and predict the existence of errors in code and, in some aspects, predict fixes for erroneous code. In some aspects, the system and method may use artificial intelligence to learn based on edits made by programmers, by observing code changes that cause errors and code changes that fix errors, or based on other data.

Abstract: Systems, apparatuses and methods may provide for technology that activates a first context on a graphics processor and detects a context switch condition with respect to the first context. Additionally, a second context may be activated, in response to the context switch condition, on the graphics processor while the first context is active on the graphics processor. In one example, activating the second context includes adding a group identifier to a plurality of threads corresponding to the second context and launching the plurality of threads with the group identifier on the graphics processor.

Abstract: Aspects of the invention include tracking relative ages of instructions in a first-in-first-out (FIFO) issue queue of an out-of-order (OoO) processor. The FIFO issue queue is configured to add instructions to the issue queue in a sequential order and to remove instructions from the issue queue in any order including a non-sequential order. The tracking of relative ages of instructions includes maintaining a head pointer to a location of an oldest instruction in the issue queue and a tail pointer to a location of a last instruction added to the issue queue. It is determined periodically whether the tail pointer is pointing to a location that includes a valid instruction. The tail pointer is updated to point to a previous sequential location in the issue queue based at least in part on determining that the tail pointer is not pointing to a location that corresponds to a valid instruction.

Abstract: A client side method for processing a GPU task comprises: receiving a request for the GPU task from an application; determining whether the request relates to a query about an execution state of the GPU task; and in response to the request relating to the query, providing a positive acknowledgement for the query to the application, without forwarding the request to a machine that executes the GPU task. A server side method for processing a GPU task comprises: receiving a request for the GPU task from a machine, the request being irrelevant to a query about an execution state of the GPU task; determining whether processing of the request depends on a processing of a previous request; and in response to the processing of the request depending on the processing of the previous request, suspending the processing of the request until the processing of the previous request is completed.

Abstract: A method of processing exceptions in an exception-driven computing-based system that operates in either initialisation mode or exception-driven mode. The method includes, upon detecting an exception has occurred, causing the processor to execute exception handling instructions. When the system is operating in initialisation mode the exception handling instructions invoke a first exception handler that causes a main register set to be saved before processing the exception and restored after processing the exception, and when the system is operating in exception-driven mode the exception handling instructions invoke a second exception handler that does not cause the main register set to be saved and restored. In some examples, the exception handling instructions are initially configured to invoke the first exception handler and are dynamically updated when the system switches from initialisation mode to exception-driven mode to invoke the second exception handler.

Abstract: A data storage device includes a dynamic latch circuit. The dynamic latch circuit includes a first NMOS transistor, a second NMOS transistor, a first PMOS transistor, and a second PMOS transistor. A source terminal of the first NMOS transistor is connected to a source terminal of the first PMOS transistor to form a data input terminal. A drain terminal of the first NMOS transistor is connected to a drain terminal of the first PMOS transistor to form a latch internal node. A gate terminal of the first NMOS transistor is connected to a clock input signal. A gate terminal of the first PMOS transistor is connected to an inverse clock input signal. A gate terminal of the second NMOS transistor and a gate terminal of the second PMOS transistor are connected to the latch internal node. A drain terminal of the second NMOS transistor and a drain terminal of the second PMOS transistor are connected to form an inverted output terminal.

Abstract: A compiler parses a multithreaded application into cohesive blocks of instructions. Cohesive blocks include instructions that do not diverge or converge. Each cohesive block is associated with one or more uniform registers. When a set of threads executes the instructions in a given cohesive block, each thread in the set may access the uniform register independently of the other threads in the set. Accordingly, the uniform register may store a single copy of data on behalf of all threads in the set of threads, thereby conserving resources.

Abstract: Providing late physical register allocation and early physical register release in out-of-order processor (OOP)-based devices implementing a checkpoint-based architecture is provided. In this regard, an OOP-based device provides a register management circuit that is configured to employ a combination of the checkpoint approach and the virtual register approach. The register management circuit includes a most recent table (MRT) for tracking mappings of logical register numbers (LRNs) to physical register numbers (PRNs), a physical register file (PRF) storing information for physical registers, a virtual register file (VRF) storing data for virtual registers, and a checkpoint queue for tracking active checkpoints (each of which is a snapshot of the MRT at a given time).

Abstract: Techniques are provided for implementing asynchronous checkpointing of in-memory data in a distributed computing system. For example, a method includes processing a stream of data records by an operator executing on a computing node, maintaining in a system memory, an operator state which is generated in response to the operator processing the stream of data records, and performing an asynchronous checkpointing process. The asynchronous checkpointing process includes enqueuing a checkpoint of the operator state in a first queue, wherein the first queue is maintained in the system memory, and executing a background worker thread to dequeue the checkpoint of the operator state from the first queue and store the checkpoint of the operator state in a data store. The operator continues with processing the stream of data records during the asynchronous checkpointing process.

Abstract: An information processing apparatus includes a multi-core processor including at least three processor cores, and a memory configured to be accessed by the at least three processor cores. The memory has at least four data areas adapted to store data. The at least three processor cores include a first processor core and a second processor core each configured to perform an update task of updating data stored in the at least four data areas. The first processor core is configured to perform the update task on a non-object data area that is selected from the at least four data areas and is not an object of processing performed by the second processor core.

Abstract: A task definition is received. The task definition indicates at least a location from which one or more software image can be obtained and information usable to determine an amount of resources to allocate to one or more software containers for the one or more software image. A set of virtual machine instances in which to launch the one or more software containers is determined, the one or more software image is obtained from the location included in the task definition and is launched as the one or more of software containers within the set of virtual machine instances.

Abstract: An apparatus and method for data parallel single program multiple data (SPMD) execution. For example, one embodiment of a processor comprises: instruction fetch circuitry to fetch instructions of one or more primary threads; a decoder to decode the instructions to generate uops; a data parallel cluster (DPC) to execute microthreads comprising a subset of the uops, the DPC further comprising: a plurality of execution lanes to perform parallel execution of the microthreads; an instruction decode queue (IDQ) to store the uops prior to execution; and a scheduler to evaluate the microthreads based on associated variables including instruction pointer (IP) values, the scheduler to gang microthreads into fragments for parallel execution on the execution lanes based on the evaluation.

Abstract: Systems and methods are disclosed for saving and restoring the search state of a pattern-recognition processor. Embodiments include a pattern-recognition processor having a state variable array and a state variable storage array stored in on-chip memory (on-silicon memory with the processor). State variable storage control logic of the pattern-recognition processor may control the saving of state variables from the state variable array to the state variable storage array. The state variable storage control logic may also control restoring of the state variables from the state variable storage array to restore a search state.

Abstract: Operations include determining a compile-time representation of a particular type. A request for the compile-time representation of the particular type comprises a source representation of the particular type. Based on and subsequent to receiving the request, a source representation of a source code file comprising the source representation of the particular type is generated. The source representation of the source code file is converted to a compile-time representation of the source code file. The compile-time representation of the particular type is derived from the source time representation of the source code file. The source code file may also be compiled to generate a set of compiled code. The set of compiled code may be loaded into a virtual machine for generating a runtime representation of the set of compiled code. A runtime representation of the particular type is derived from the runtime representation of the set of compiled code.

Abstract: A data processing system 2 operates at a plurality of exception levels ELx and supports the use of protected execution environments. A register bank 16 contains registers having associated ownership variables indicating an owning exception level. Register access control circuitry 30 is responsive to the ownership values for respective registers to control access to those registers by processing circuitry 14 in dependence upon the ownership values. Target-constrained data transfer operations and associated program instructions may be provided which are able to access data values in registers not owned by the exception level associated with the execution of those program instructions, but are limited to perform data transfers to or from memory locations within a memory 6 indicated by an architected storage pointer for the owning exception level. Target-unconstrained transfer instructions at a given exception level are not able to access register data value marked as owned by a different exception level.

Abstract: Technology for a controller in a storage area network (SAN) node operable to perform data requests is described. The controller can receive a data request from a remote node. The data request can specify a data payload and a type of operation associated with the data request. The controller can select a kernel from a kernel table stored in the memory based on a set of rules. The kernel can be matched to the data request in accordance with the set of rules. The kernel can be configured using a bit stream. The controller can execute the kernel in order to perform the data request in accordance with the data payload and the type of operation.

Abstract: A task definition is received. The task definition indicates at least a location from which one or more software image can be obtained and information usable to determine an amount of resources to allocate to one or more software containers for the one or more software image. A set of virtual machine instances in which to launch the one or more software containers is determined, the one or more software image is obtained from the location included in the task definition and is launched as the one or more of software containers within the set of virtual machine instances.

Abstract: Systems, methods, and apparatus for automatically parallelizing code segments are provided. For example, an environment includes a profiling agent, a parallelization agent, and a verification agent. The profiling agent executes a code segment and generates a profile of the executed code segment. The parallelization agent analyzes the code segment to determine whether a parallelizable portion is present in the code segment. When a parallelizable portion is present, the parallelization agent determines, based on the profile of the executed code segment, whether to parallelize the parallelizable portion of the code segment. If it is determined to parallelize the parallelizable portion of the code segment, the parallelization agent automatically parallelizes the parallelizable portion of the code segment. The verification agent verifies the functionality and/or correctness of the parallelized code segment.

Abstract: A management apparatus that manages a first database and a second database synchronized with each other includes a memory and a processor configured to perform a stop of synchronous processing between the first database and the second database in accordance with detection of a delay with respect to a first processing request received by the first database, output an error notification concerning uncompleted processing in the first database in which the delay is detected, and allocate a second processing request received after the detection to the second database.

Abstract: Disclosed is a method of executing a decoding command. A method of executing a decoding command includes acquiring the decoding command, determining a type of an executable operation on the basis of the acquired decoding command, and performing any one of an operation of storing context information about an encoded symbol and an operation of decoding the encoded symbol on the basis of the determination result.

Abstract: A storage controller coupled to a storage array includes a device driver running in a kernel space that receives an administrative command from an application running in a user space of the storage controller and writes the administrative command to a first submission queue of a plurality of submission queues associated with a storage device in the storage array, where the first submission queue is reserved for use by the device driver. An input/output (I/O) command received from the application running in the user space, however, is written directly to a second submission queue of the plurality of submission queues without being routed through the kernel space, where the second submission queue being reserved for direct access by the application running in the user space.

Abstract: A task definition is received. The task definition indicates at least a location from which one or more software image can be obtained and information usable to determine an amount of resources to allocate to one or more software containers for the one or more software image. A set of virtual machine instances in which to launch the one or more software containers is determined, the one or more software image is obtained from the location included in the task definition and is launched as the one or more of software containers within the set of virtual machine instances.

Abstract: Aspects of the subject technology relate to methods for inter-container communication in a virtual network environment. Steps for implementing an inter-container communication method can include: creating, using a container management system, a file-structure in a shared memory, generating, by the container management system, a first memory-mapping between the file-structure and a first network container, and generating, by the container management system, a second memory-mapping between the file-structure and a second network container. In some aspects, the method can further include steps for transferring at least one data packet from the first network container to the second network container via the file-structure in the shared memory. Systems and machine-readable media are also provided.

Abstract: A processor circuit is disclosed. In an embodiment, the processor circuit includes a processor unit configured to execute a multiple load or multiple store instruction for loading or storing a plurality of data words, and a data interface block, DIB, configured to communicate with the processor and configured to, in response to an occurrence of an interrupt during execution of the multiple load or store instruction, save the state of the multiple load or store instruction. Saving the state can comprise storing the number of data words already loaded or stored when the interrupt occurred. When the multiple load/store instruction is executed again after the interrupt, the DIB can skip the stored number of data words.

Abstract: One or more architected registers are restored from a snapshot previously taken of the one or more architected registers. The snapshot indicates one or more physical registers previously assigned to the one or more architected registers. The restoring replaces the one or more physical registers currently assigned to the one or more architected registers with the one or more physical registers previously assigned to the one or more architected registers as indicated by the snapshot. A determination is made as to the validity of the one or more architected registers restored using the snapshot. The determining validity includes checking memory locations associated with the one or more architected registers to determine whether contents of the one or more architected registers have changed since the snapshot was taken. If the contents of the one or more architected registers have not changed, the one or more architected registers are valid.

Abstract: A processor (and method) includes a core that performs a floating point division through execution of various instructions. The instructions include a sign, exponent, and mantissa (SEM) separation instruction which causes the core to extract the sign, exponent and mantissa values from numerator and denominator floating point numbers. The instructions also include an unsigned mantissa division instruction which cause the core to iteratively perform a conditional subtraction operation to compute a value indicative of a mantissa of the quotient. The instructions further include a merge instruction that causes the core to generate a quotient floating point number using the extracted sign and exponent from the SEM separation instruction and the value indicative of the mantissa of the quotient.

Abstract: Data processing circuitry has a virtual data buffer, with contiguous virtual addresses of the virtual buffer being associated with discontiguous addresses of a physical memory. Cyphering circuitry coupled between the data processing circuitry and the physical memory responds to a command received from the data processing circuitry by determining a key associated with the command based on virtual buffer address information associated with the virtual buffer.