Context Preserving (e.g., Context Swapping, Checkpointing, Register Windowing Patents (Class 712/228)
  • Patent number: 10817569
    Abstract: Systems and methods are disclosed for saving and restoring the search state of a pattern-recognition processor. Embodiments include a pattern-recognition processor having a state variable array and a state variable storage array stored in on-chip memory (on-silicon memory with the processor). State variable storage control logic of the pattern-recognition processor may control the saving of state variables from the state variable array to the state variable storage array. The state variable storage control logic may also control restoring of the state variables from the state variable storage array to restore a search state.
    Type: Grant
    Filed: November 7, 2017
    Date of Patent: October 27, 2020
    Assignee: Micron Technology, Inc.
    Inventors: Harold B Noyes, David R. Brown
  • Patent number: 10802855
    Abstract: Operations include determining a compile-time representation of a particular type. A request for the compile-time representation of the particular type comprises a source representation of the particular type. Based on and subsequent to receiving the request, a source representation of a source code file comprising the source representation of the particular type is generated. The source representation of the source code file is converted to a compile-time representation of the source code file. The compile-time representation of the particular type is derived from the source time representation of the source code file. The source code file may also be compiled to generate a set of compiled code. The set of compiled code may be loaded into a virtual machine for generating a runtime representation of the set of compiled code. A runtime representation of the particular type is derived from the runtime representation of the set of compiled code.
    Type: Grant
    Filed: March 24, 2017
    Date of Patent: October 13, 2020
    Assignee: Oracle International Corporation
    Inventors: Vicente A. Romero Zaldivar, Maurizio Cimadamore, Jonathan J. Gibbons
  • Patent number: 10762226
    Abstract: A data processing system 2 operates at a plurality of exception levels ELx and supports the use of protected execution environments. A register bank 16 contains registers having associated ownership variables indicating an owning exception level. Register access control circuitry 30 is responsive to the ownership values for respective registers to control access to those registers by processing circuitry 14 in dependence upon the ownership values. Target-constrained data transfer operations and associated program instructions may be provided which are able to access data values in registers not owned by the exception level associated with the execution of those program instructions, but are limited to perform data transfers to or from memory locations within a memory 6 indicated by an architected storage pointer for the owning exception level. Target-unconstrained transfer instructions at a given exception level are not able to access register data value marked as owned by a different exception level.
    Type: Grant
    Filed: February 10, 2017
    Date of Patent: September 1, 2020
    Assignee: ARM Limited
    Inventor: Jason Parker
  • Patent number: 10754588
    Abstract: Technology for a controller in a storage area network (SAN) node operable to perform data requests is described. The controller can receive a data request from a remote node. The data request can specify a data payload and a type of operation associated with the data request. The controller can select a kernel from a kernel table stored in the memory based on a set of rules. The kernel can be matched to the data request in accordance with the set of rules. The kernel can be configured using a bit stream. The controller can execute the kernel in order to perform the data request in accordance with the data payload and the type of operation.
    Type: Grant
    Filed: March 31, 2017
    Date of Patent: August 25, 2020
    Assignee: Intel Corporation
    Inventors: Francesc Guim Bernat, Kshitij A. Doshi, Daniel Rivas Barragan
  • Patent number: 10725847
    Abstract: A management apparatus that manages a first database and a second database synchronized with each other includes a memory and a processor configured to perform a stop of synchronous processing between the first database and the second database in accordance with detection of a delay with respect to a first processing request received by the first database, output an error notification concerning uncompleted processing in the first database in which the delay is detected, and allocate a second processing request received after the detection to the second database.
    Type: Grant
    Filed: April 10, 2018
    Date of Patent: July 28, 2020
    Assignee: FUJITSU LIMITED
    Inventor: Daisuke Higuchi
  • Patent number: 10725812
    Abstract: A task definition is received. The task definition indicates at least a location from which one or more software image can be obtained and information usable to determine an amount of resources to allocate to one or more software containers for the one or more software image. A set of virtual machine instances in which to launch the one or more software containers is determined, the one or more software image is obtained from the location included in the task definition and is launched as the one or more of software containers within the set of virtual machine instances.
    Type: Grant
    Filed: June 8, 2018
    Date of Patent: July 28, 2020
    Assignee: Amazon Technologies, Inc.
    Inventors: Deepak Singh, Anthony Joseph Suarez, William Andrew Thurston, Anirudh Balachandra Aithal, Daniel Robert Gerdesmeier, Euan Skyler Kemp, Kiran Kumar Meduri, Muhammad Umer Azad
  • Patent number: 10725897
    Abstract: Systems, methods, and apparatus for automatically parallelizing code segments are provided. For example, an environment includes a profiling agent, a parallelization agent, and a verification agent. The profiling agent executes a code segment and generates a profile of the executed code segment. The parallelization agent analyzes the code segment to determine whether a parallelizable portion is present in the code segment. When a parallelizable portion is present, the parallelization agent determines, based on the profile of the executed code segment, whether to parallelize the parallelizable portion of the code segment. If it is determined to parallelize the parallelizable portion of the code segment, the parallelization agent automatically parallelizes the parallelizable portion of the code segment. The verification agent verifies the functionality and/or correctness of the parallelized code segment.
    Type: Grant
    Filed: May 3, 2017
    Date of Patent: July 28, 2020
    Assignee: Securboration, Inc.
    Inventors: Jacob A. Staples, Lee Krause, James B. Schneider, Adam K. Kavanaugh
  • Patent number: 10715823
    Abstract: Disclosed is a method of executing a decoding command. A method of executing a decoding command includes acquiring the decoding command, determining a type of an executable operation on the basis of the acquired decoding command, and performing any one of an operation of storing context information about an encoded symbol and an operation of decoding the encoded symbol on the basis of the determination result.
    Type: Grant
    Filed: March 31, 2015
    Date of Patent: July 14, 2020
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Doo-hyun Kim, Do-hyung Kim
  • Patent number: 10678432
    Abstract: A storage controller coupled to a storage array includes a device driver running in a kernel space that receives an administrative command from an application running in a user space of the storage controller and writes the administrative command to a first submission queue of a plurality of submission queues associated with a storage device in the storage array, where the first submission queue is reserved for use by the device driver. An input/output (I/O) command received from the application running in the user space, however, is written directly to a second submission queue of the plurality of submission queues without being routed through the kernel space, where the second submission queue being reserved for direct access by the application running in the user space.
    Type: Grant
    Filed: January 26, 2017
    Date of Patent: June 9, 2020
    Assignee: Pure Storage, Inc.
    Inventors: Roland Dreier, Bryan Freed, Logan Jennings, Sandeep Mann
  • Patent number: 10678582
    Abstract: A task definition is received. The task definition indicates at least a location from which one or more software image can be obtained and information usable to determine an amount of resources to allocate to one or more software containers for the one or more software image. A set of virtual machine instances in which to launch the one or more software containers is determined, the one or more software image is obtained from the location included in the task definition and is launched as the one or more of software containers within the set of virtual machine instances.
    Type: Grant
    Filed: June 8, 2018
    Date of Patent: June 9, 2020
    Assignee: Amazon Technologies, Inc.
    Inventors: Deepak Singh, Anthony Joseph Suarez, William Andrew Thurston, Anirudh Balachandra Aithal, Daniel Robert Gerdesmeier, Euan Skyler Kemp, Kiran Kumar Meduri, Muhammad Umer Azad
  • Patent number: 10671571
    Abstract: Aspects of the subject technology relate to methods for inter-container communication in a virtual network environment. Steps for implementing an inter-container communication method can include: creating, using a container management system, a file-structure in a shared memory, generating, by the container management system, a first memory-mapping between the file-structure and a first network container, and generating, by the container management system, a second memory-mapping between the file-structure and a second network container. In some aspects, the method can further include steps for transferring at least one data packet from the first network container to the second network container via the file-structure in the shared memory. Systems and machine-readable media are also provided.
    Type: Grant
    Filed: January 31, 2017
    Date of Patent: June 2, 2020
    Assignee: CISCO TECHNOLOGY, INC.
    Inventor: Ian Wells
  • Patent number: 10656952
    Abstract: A processor circuit is disclosed. In an embodiment, the processor circuit includes a processor unit configured to execute a multiple load or multiple store instruction for loading or storing a plurality of data words, and a data interface block, DIB, configured to communicate with the processor and configured to, in response to an occurrence of an interrupt during execution of the multiple load or store instruction, save the state of the multiple load or store instruction. Saving the state can comprise storing the number of data words already loaded or stored when the interrupt occurred. When the multiple load/store instruction is executed again after the interrupt, the DIB can skip the stored number of data words.
    Type: Grant
    Filed: May 1, 2015
    Date of Patent: May 19, 2020
    Assignee: NXP B.V.
    Inventors: Nicolas Laine, Cyril Edeline
  • Patent number: 10649785
    Abstract: One or more architected registers are restored from a snapshot previously taken of the one or more architected registers. The snapshot indicates one or more physical registers previously assigned to the one or more architected registers. The restoring replaces the one or more physical registers currently assigned to the one or more architected registers with the one or more physical registers previously assigned to the one or more architected registers as indicated by the snapshot. A determination is made as to the validity of the one or more architected registers restored using the snapshot. The determining validity includes checking memory locations associated with the one or more architected registers to determine whether contents of the one or more architected registers have changed since the snapshot was taken. If the contents of the one or more architected registers have not changed, the one or more architected registers are valid.
    Type: Grant
    Filed: April 18, 2017
    Date of Patent: May 12, 2020
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Michael K. Gschwind, Valentina Salapura, Chung-Lung K. Shum, Timothy J. Slegel
  • Patent number: 10635395
    Abstract: A processor (and method) includes a core that performs a floating point division through execution of various instructions. The instructions include a sign, exponent, and mantissa (SEM) separation instruction which causes the core to extract the sign, exponent and mantissa values from numerator and denominator floating point numbers. The instructions also include an unsigned mantissa division instruction which cause the core to iteratively perform a conditional subtraction operation to compute a value indicative of a mantissa of the quotient. The instructions further include a merge instruction that causes the core to generate a quotient floating point number using the extracted sign and exponent from the SEM separation instruction and the value indicative of the mantissa of the quotient.
    Type: Grant
    Filed: June 30, 2016
    Date of Patent: April 28, 2020
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Prasanth Viswanathan Pillai, Venkatesh Natarajan, Alexander Tessarolo
  • Patent number: 10592264
    Abstract: A method may include generating, from an expression, an expression tree including an arithmetic operation and conversion operations each converting an operand of the arithmetic operation from an initial decimal format to an optimized decimal format. The initial decimal format may include a shape. The method may further include at runtime, evaluating the arithmetic operation with initial operands represented in the initial decimal format, and specializing one of the conversion operations according to the shape of the corresponding initial operand.
    Type: Grant
    Filed: May 16, 2018
    Date of Patent: March 17, 2020
    Assignee: Oracle International Corporation
    Inventors: Alexey Karyakin, Laurent Daynes
  • Patent number: 10594483
    Abstract: Data processing circuitry has a virtual data buffer, with contiguous virtual addresses of the virtual buffer being associated with discontiguous addresses of a physical memory. Cyphering circuitry coupled between the data processing circuitry and the physical memory responds to a command received from the data processing circuitry by determining a key associated with the command based on virtual buffer address information associated with the virtual buffer.
    Type: Grant
    Filed: March 24, 2015
    Date of Patent: March 17, 2020
    Assignee: STMICROELECTRONICS (RESEARCH AND DEVELOPMENT) LIMITED
    Inventor: Robert Smart
  • Patent number: 10579482
    Abstract: The invention relates to a method of checkpointing the working environment of a user (7) session on a server (1) comprising a first step (11) of checkpointing the working environment of a first application of said session, characterized in that it comprises at least one second step (12) of checkpointing the working environment of a second application of said session different from said first application, and in that said first checkpointing step (11) and said second checkpointing step (12) are synchronized with each other such that the checkpointed working environment of the first application and the checkpointed working environment of the second application are coherent with each other.
    Type: Grant
    Filed: July 19, 2016
    Date of Patent: March 3, 2020
    Assignee: BULL SAS
    Inventors: Sylvain Cohard, Rafael Escovar
  • Patent number: 10572258
    Abstract: Systems, apparatuses and methods may provide for technology that activates a first context on a graphics processor and detects a context switch condition with respect to the first context. Additionally, a second context may be activated, in response to the context switch condition, on the graphics processor while the first context is active on the graphics processor. In one example, activating the second context includes adding a group identifier to a plurality of threads corresponding to the second context and launching the plurality of threads with the group identifier on the graphics processor.
    Type: Grant
    Filed: April 1, 2017
    Date of Patent: February 25, 2020
    Assignee: Intel Corporation
    Inventors: Altug Koker, Michael Apodaca, Kai Xiao, Chandrasekaran Sakthivel, Jeffery S. Boles, Adam T. Lake, Abhishek R. Appu
  • Patent number: 10540200
    Abstract: A hardware context manager in a field-programmable gate array (FPGA) device includes configuration logic configured to program one or more programming regions in the FPGA device based on configuration data for implementing a target configuration of the one or more programming regions. Context management logic in the hardware context manager is coupled with the configuration logic and saves a first context corresponding to the target configuration by retrieving first state information from the set of one or more programming regions, where the first state information is generated based on the target configuration, and storing the retrieved first state information in a context memory. The context management logic restores the first context by transferring the first state information from the context memory to the one or more programming regions, and causing the configuration logic to program the one or more programming regions based on the configuration data.
    Type: Grant
    Filed: November 10, 2017
    Date of Patent: January 21, 2020
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Kevin Y. Cheng, David A. Roberts, William C. Brantley
  • Patent number: 10541858
    Abstract: A thin client system comprises a plurality of virtual desktop environment servers each including a virtual desktop environment in which a workplace environment is generated in a virtual machine, and a management server which manages setting of the virtual desktop environment and the virtual desktop environment server, wherein the management server comprises an OS sorting unit which generates information of an OS sorting result obtained by sorting the virtual desktop environment servers in the order of failing to have a virtual machine whose OS is other than OS of a virtual machine to be newly created, and a VM creating unit which determines the virtual desktop environment server in which the virtual machine is to be created based on the OS sorting result information by giving preference to the virtual desktop environment server failing to have a virtual machine having that other OS.
    Type: Grant
    Filed: January 30, 2013
    Date of Patent: January 21, 2020
    Assignee: NEC CORPORATION
    Inventor: Masahiko Taguchi
  • Patent number: 10534614
    Abstract: A method of sharing a plurality of registers in a shared register pool among a plurality of microprocessor threads begins with a determination that a first instruction to be executed by a microprocessor in a first microprocessor thread requires a first logical register. Next a determination is made that a second instruction to be executed by the microprocessor in a second microprocessor thread requires a second logical register. A first physical register in the shared register pool is allocated to the first microprocessor thread for execution of the first instruction and the first logical register is mapped to the first physical register. A second physical register in the shared register pool is allocated to the second microprocessor thread for execution of the second instruction. Finally, the second logical register is mapped to the second physical register.
    Type: Grant
    Filed: June 8, 2012
    Date of Patent: January 14, 2020
    Assignee: MIPS Tech, LLC
    Inventor: Ilie Garbacea
  • Patent number: 10521237
    Abstract: A method and a device that includes a set of multiple pipeline stages, wherein the set of multiple pipeline stages is arranged to execute a first thread of instructions; multiple memristor based registers that are arranged to store a state of another thread of instructions that differs from the first thread of instructions; and a control circuit that is arranged to control a thread switch between the first thread of instructions and the other thread of instructions by controlling a storage of a state of the first thread of instructions at the multiple memristor based registers and by controlling a provision of the state of the other thread of instructions by the set of multiple pipeline stages; wherein the set of multiple pipeline stages is arranged to execute the other thread of instructions upon a reception of the state of the other thread of instructions.
    Type: Grant
    Filed: March 19, 2014
    Date of Patent: December 31, 2019
    Assignee: TECHNION RESEARCH AND DEVELOPMENT FOUNDATION LTD
    Inventors: Avinoam Kolodny, Uri Weiser, Shahar Kvatinsky
  • Patent number: 10496437
    Abstract: Context switch by changing memory pointers. A determination is made that a context switch is to be performed from a first context to a second context. Data of the first context is stored in one or more configuration state registers stored at least in part in a first memory unit and data of the second context is stored in one or more configuration state registers stored at least in part in a second memory unit. The context switch is performed by changing a pointer from the first memory unit to the second memory unit.
    Type: Grant
    Filed: November 14, 2017
    Date of Patent: December 3, 2019
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Michael K. Gschwind, Valentina Salapura
  • Patent number: 10474468
    Abstract: Systems, apparatuses, and methods for processing variable wavefront sizes on a processor are disclosed. In one embodiment, a processor includes at least a scheduler, cache, and multiple execution units. When operating in a first mode, the processor executes the same instruction on multiple portions of a wavefront before proceeding to the next instruction of the shader program. When operating in a second mode, the processor executes a set of instructions on a first portion of a wavefront. In the second mode, when the processor finishes executing the set of instructions on the first portion of the wavefront, the processor executes the set of instructions on a second portion of the wavefront, and so on until all portions of the wavefront have been processed. The processor determines the operating mode based on one or more conditions.
    Type: Grant
    Filed: February 22, 2017
    Date of Patent: November 12, 2019
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Michael J. Mantor, Brian D. Emberling, Mark Fowler, Mark M. Leather
  • Patent number: 10430596
    Abstract: The invention provides an information processing method. The information processing method is applied to a terminal that comprises a plurality of operating systems. The information processing method comprises: upon receiving an instruction of copying data information in an arbitrary operating system to a specified operating system among the plurality of operating systems, acquiring a target entering key of the specified operating system; and after copying the data information to the specified operating system, encrypting the data information in the arbitrary operating system by using the target entering key of the specified operating system, or not displaying the data information in the arbitrary operating system again. The technical solution guarantees that data are not lost and also guarantees that data are not easy to divulge. The invention also provides a terminal and a nonvolatile machine-readable medium.
    Type: Grant
    Filed: March 24, 2017
    Date of Patent: October 1, 2019
    Assignee: YULONG COMPUTER TELECOMMUNICATION SCIENTIFIC (SHENZHEN) CO., LTD.
    Inventor: Jingen Sheng
  • Patent number: 10423424
    Abstract: Techniques are disclosed for performing an auxiliary operation via a compute engine associated with a host computing device. The method includes determining that the auxiliary operation is directed to the compute engine, and determining that the auxiliary operation is associated with a first context comprising a first set of state parameters. The method further includes determining a first subset of state parameters related to the auxiliary operation based on the first set of state parameters. The method further includes transmitting the first subset of state parameters to the compute engine, and transmitting the auxiliary operation to the compute engine. One advantage of the disclosed technique is that surface area and power consumption are reduced within the processor by utilizing copy engines that have no context switching capability.
    Type: Grant
    Filed: September 28, 2012
    Date of Patent: September 24, 2019
    Assignee: NVIDIA CORPORATION
    Inventors: Lincoln G. Garlick, Philip Browning Johnson, Rafal Zboinski, Jeff Tuckey, Samuel H. Duncan, Peter C. Mills
  • Patent number: 10417111
    Abstract: Methods, systems and computer readable medium are provided for sequentially analyzing a series of thread dump samples to estimate the intensity statistic of newly classified stack segments of stack frames. According to one embodiment, a branch point along one or more linearly connected stack frames of a stack segment can be detected, where the stack segment is associated with one or more thread intensity statistic parameters. Upon detecting the branch point along the one or more linearly connected stack frames of the stack segment, the system can split the stack segment into a plurality of new stack segments that each include a subset of the stack frames, where the plurality of new stack segments are referenced by the stack segment. The system can then initialize the one or more thread intensity statistic parameters for each of the new stack segments.
    Type: Grant
    Filed: May 5, 2017
    Date of Patent: September 17, 2019
    Assignee: ORACLE INTERNATIONAL CORPORATION
    Inventor: Eric S. Chan
  • Patent number: 10380034
    Abstract: Improving operation of a processing unit to access data within a cache system. A first fetch request and one or more subsequent fetch requests are accessed in an instruction stream. An address of data sought by the first fetch requested is obtained. At least a portion of the address of data sought by the first fetch request in inserted in each of the one or more subsequent fetch requests. The portion of the address inserted in each of the one or more subsequent fetch requests is utilized to retrieve the data sought by the first fetch request first in order from the cache system.
    Type: Grant
    Filed: July 14, 2017
    Date of Patent: August 13, 2019
    Assignee: International Business Machines Corporation
    Inventors: Markus Kaltenbach, Ulrich Mayer, Siegmund Schlechter, Maxim Scholl
  • Patent number: 10354706
    Abstract: For an integrated circuit (IC) that is designed to execute user defined operations after initialization, a sequencing circuitry in the IC that delays the start of the user design execution until a set of initial condition has been computed and propagated is provided. The sequencing holds the first group of circuits at an initial state while a second group of circuits computes and propagates a set of initial conditions based at least partly on the initial state of the first group of circuits. The circuits in the first group when being held disregard their inputs and do not change their outputs. The first group of circuits is released from its initial state after the second group of circuits has completed computation and propagation of the set of initial conditions. The circuits in the first group when released are freed to store or clock-in new inputs and produce new outputs in order to perform the user defined operations in conjunction with the second group of circuits.
    Type: Grant
    Filed: November 23, 2015
    Date of Patent: July 16, 2019
    Assignee: Altera Corporation
    Inventors: Christopher D. Ebeling, Trevis Chandler
  • Patent number: 10325844
    Abstract: A computer-implemented method includes, in a code transformation system, identifying save-to-return code instructions, function call code instructions, comparison code instructions, and exceptional code instructions. The function call code instructions are associated with the save-to-return code instructions. The comparison code instructions are associated with the save-to-return code instructions. The exceptional code instructions are associated with the comparison code instructions. A predefined proximity range based on a predefined proximity value as well as a proximity eligibility indicator are determined. The proximity eligibility indicator denotes whether the save-to-return code instructions and the comparison code instructions are within the predefined proximity range.
    Type: Grant
    Filed: February 1, 2018
    Date of Patent: June 18, 2019
    Assignee: International Business Machines Corporation
    Inventors: Iain A. Ireland, Allan H. Kielstra, Muntasir A. Mallick
  • Patent number: 10295980
    Abstract: An apparatus, method for operating an automation device which includes a processor for directly executing function modules, where a function module selected as a component of an automation solution via a development environment, is converted into a code block via the development environment, where the code block includes a type identifier corresponding to the type of the particular function module, where inputs and outputs of the particular function module are mapped to simultaneously usable processor registers in the code block, a plurality of code blocks is processed by reading-in a particular code block by the processor and subsequently executing the code block to execute the automation solution, and where execution of the code block includes selecting a function unit from a plurality of function units based on the type identifier of the code block and activation of the selected function unit with the processor registers specified in the code block.
    Type: Grant
    Filed: March 26, 2015
    Date of Patent: May 21, 2019
    Assignee: Siemens Aktiengesellschaft
    Inventor: Eberhard Schlarb
  • Patent number: 10275250
    Abstract: An apparatus comprises processing circuitry for executing instructions of two or more threads of processing, hardware registers to store context data for the two or more threads concurrently, and commit circuitry to commit results of executed instructions of the threads, where for each thread the commit circuitry commits the instructions of that thread in program order. At least one defer buffer is provided to buffer at least one blocked instruction for which execution by the processing circuitry is complete but execution of an earlier instruction of the same thread in the program order is incomplete. This can help to resolve inter-thread blocking and hence improve performance.
    Type: Grant
    Filed: March 6, 2017
    Date of Patent: April 30, 2019
    Assignee: ARM Limited
    Inventors: Jose Alberto Joao, Ziqiang Huang, Alejandro Rico Carro
  • Patent number: 10248908
    Abstract: Methods, systems, and apparatus for accessing a N-dimensional tensor are described. In some implementations, a method includes, for each of one or more first iterations of a first nested loop, performing iterations of a second nested loop that is nested within the first nested loop until a first loop bound for the second nested loop is reached. A number of iterations of the second nested loop for the one or more first iterations of the first nested loop is limited by the first loop bound in response to the second nested loop having a total number of iterations that exceeds a value of a hardware property of the computing system. After a penultimate iteration of the first nested loop has completed, one or more iterations of the second nested loop are performed for a final iteration of the first nested loop until an alternative loop bound is reached.
    Type: Grant
    Filed: June 19, 2017
    Date of Patent: April 2, 2019
    Assignee: Google LLC
    Inventors: Olivier Temam, Harshit Khaitan, Ravi Narayanaswami, Dong Hyuk Woo
  • Patent number: 10180789
    Abstract: Systems, apparatuses, and methods for implementing software control of state sets are disclosed. In one embodiment, a processor includes at least an execution unit and a plurality of state registers. The processor is configured to detect a command to allocate a first state set for storing a first state, wherein the command is generated by software, and wherein the first state specifies values for the plurality of state registers. The command is executed on the execution unit while the processor is in a second state, wherein the second state is different from the first state. The first state set of the processor is allocated with the first state responsive to executing the command on the execution unit. The processor is configured to allocate the first state set for the first state prior to the processor entering the first state.
    Type: Grant
    Filed: January 26, 2017
    Date of Patent: January 15, 2019
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Rex Eldon McCrary, Michael J. Mantor, Alexander Fuad Ashkar, Harry J. Wise
  • Patent number: 10176002
    Abstract: Methods and apparatuses for performing a quiesce operation in a multithread environment is provided. A processor receives a first thread quiesce request from a first thread executing on the processor. A processor sends a first processor quiesce request to a system controller to initiate a quiesce operation. A processor performs one or more operations of the first thread based, at least in part, on receiving a response from the system controller.
    Type: Grant
    Filed: December 17, 2014
    Date of Patent: January 8, 2019
    Assignee: International Business Machines Corporation
    Inventors: Michael Fee, Ute Gaertner, Lisa C. Heller, Thomas Koehler, Frank Lehnert, Jennifer A. Navarro
  • Patent number: 10168941
    Abstract: Methods, systems, and computer program products for historical state snapshot construction over temporally evolving data are provided herein. A computer-implemented method includes classifying each of multiple temporally evolving data entities into one of multiple categories based on one or more parameters; partitioning the multiple temporally evolving data entities into multiple partitions based at least on (i) said classifying and (ii) the update frequency of each of the multiple temporally evolving data entities; implementing multiple checkpoints at a distinct temporal interval for each of the multiple partitions; and creating a snapshot of the multiple temporally evolving data entities at a selected past point of time (i) based on said implementing and (ii) in response to a query pertaining to a historical state of one or more of the multiple temporally evolving data entities.
    Type: Grant
    Filed: February 19, 2016
    Date of Patent: January 1, 2019
    Assignee: International Business Machines Corporation
    Inventors: Srikanta B. Jagannath, Sriram Lakshminarasimhan, Sameep Mehta, Animesh Nandi, Narendran Sachindran
  • Patent number: 10162687
    Abstract: A processor of an aspect includes at least one lower processing capability and lower power consumption physical compute element and at least one higher processing capability and higher power consumption physical compute element. Migration performance benefit evaluation logic is to evaluate a performance benefit of a migration of a workload from the at least one lower processing capability compute element to the at least one higher processing capability compute element, and to determine whether or not to allow the migration based on the evaluated performance benefit. Available energy and thermal budget evaluation logic is to evaluate available energy and thermal budgets and to determine to allow the migration if the migration fits within the available energy and thermal budgets. Workload migration logic is to perform the migration when allowed by both the migration performance benefit evaluation logic and the available energy and thermal budget evaluation logic.
    Type: Grant
    Filed: December 28, 2012
    Date of Patent: December 25, 2018
    Assignee: Intel Corporation
    Inventors: Eugene Gorbatov, Alon Naveh, Inder M. Sodhi, Ganapati N. Srinivasa, Eliezer Weissmann, Guarav Khanna, Mishali Naik, Russell J. Fenger, Andrew D. Henroid, Dheeraj R. Subbareddy, David A. Koufaty, Paolo Narvaez
  • Patent number: 10146548
    Abstract: A method for populating a source view data structure by using register template snapshots. The method includes receiving an incoming instruction sequence using a global front end; grouping the instructions to form instruction blocks; using a plurality of register templates to track instruction destinations and instruction sources by populating the register template with block numbers corresponding to the instruction blocks, wherein the block numbers corresponding to the instruction blocks indicate interdependencies among the blocks of instructions; populating a source view data structure, wherein the source view data structure stores sources corresponding to the instruction blocks as recorded by the plurality of register templates; and determining which of the plurality of instruction blocks are ready for dispatch by using the populated source view data structure.
    Type: Grant
    Filed: January 17, 2017
    Date of Patent: December 4, 2018
    Assignee: Intel Corporation
    Inventor: Mohammad Abdallah
  • Patent number: 10127076
    Abstract: A method includes performing one or more operations as requested by a thread executing on a processor, the thread having a thread context; receiving a park request from the thread, the park request received following a request from the thread for a low latency resource, wherein the cache response time is less than or equal to a resource response threshold so as to allow the thread context to be stored and retrieved from the cache in less time than the portion of time it takes to complete the request for the low latency resource; storing the thread context in the cache; detecting that the resume condition has occurred; retrieving the thread context from the cache; and resuming execution of the thread.
    Type: Grant
    Filed: June 6, 2016
    Date of Patent: November 13, 2018
    Assignee: Google LLC
    Inventors: Luiz Andre Barroso, James Laudon, Michael R. Marty
  • Patent number: 10115222
    Abstract: A graphics processing unit comprises a programmable execution unit executing graphics processing programs for execution threads to perform graphics processing operations, a local register memory comprising one or more registers, where registers of the register memory are assignable to store data associated with an individual execution thread that is being executed by the execution unit, and where the register(s) assigned to an individual execution thread are accessible only to that associated individual execution thread, and a further local memory that is operable to store data for use in common by plural execution threads, where the data stored in the further local memory is accessible to plural execution threads as they execute. The programmable execution unit is operable to selectively store output data for an execution thread in a register(s) of the local register memory assigned to the execution thread, and the further local memory.
    Type: Grant
    Filed: January 9, 2017
    Date of Patent: October 30, 2018
    Assignee: Arm Limited
    Inventors: Sean Tristram LeGuay Ellis, Thomas James Cooksey, Robert Martin Elliott
  • Patent number: 10095525
    Abstract: A processor may include a reorder buffer, reservation stations, and execution units. The reorder buffer may be a circular buffer with a head pointer and a tail pointer, configured to assign indexes to instructions. Reservation stations may be configured to host instructions with the assigned indexes, while waiting to be issued to the execution units. Responsive to exception event, reservation stations may be configured to flush instructions that are younger, in program order, than the instruction executed with exception. Execution units may provide the reorder buffer index EX of the instruction executed with exception. The reorder buffer may provide the reorder buffer index TP stored in the tail pointer. Reservation stations may be configured to flush instructions with assigned indexes in the wrapped-around increasing interval from the index EX to the index TP.
    Type: Grant
    Filed: November 24, 2017
    Date of Patent: October 9, 2018
    Inventor: Dejan Spasov
  • Patent number: 10067782
    Abstract: Various aspects are disclosed herein for attenuating spin waiting in a virtual machine environment comprising a plurality of virtual machines and virtual processors. Selected virtual processors can be given time slice extensions in order to prevent such virtual processors from becoming de-scheduled (and hence causing other virtual processors to have to spin wait). Selected virtual processors can also be expressly scheduled so that they can be given higher priority to resources, resulting in reduced spin waits for other virtual processors waiting on such selected virtual processors. Finally, various spin wait detection techniques can be incorporated into the time slice extension and express scheduling mechanisms, in order to identify potential and existing spin waiting scenarios.
    Type: Grant
    Filed: November 18, 2015
    Date of Patent: September 4, 2018
    Assignee: Microsoft Technology Licensing, LLC
    Inventors: Yau Ning Chin, John Te-Jui Sheu, Arun Kishan, Thomas Fahrig, Rene Antonio Vega
  • Patent number: 10025608
    Abstract: Methods and apparatuses for performing a quiesce operation in a multithread environment is provided. A processor receives a first thread quiesce request from a first thread executing on the processor. A processor sends a first processor quiesce request to a system controller to initiate a quiesce operation. A processor performs one or more operations of the first thread based, at least in part, on receiving a response from the system controller.
    Type: Grant
    Filed: November 17, 2014
    Date of Patent: July 17, 2018
    Assignee: International Business Machines Corporation
    Inventors: Michael Fee, Ute Gaertner, Lisa C. Heller, Thomas Koehler, Frank Lehnert, Jennifer A. Navarro
  • Patent number: 10019283
    Abstract: A processing device includes a first memory that includes a context buffer. The processing device also includes a processor core to execute threads based on context information stored in registers of the processor core and a memory controller to selectively move a subset of the context information between the context buffer and the registers based on one or more latencies of the threads.
    Type: Grant
    Filed: June 22, 2015
    Date of Patent: July 10, 2018
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Dmitri Yudanov, Sergey Blagodurov, Arkaprava Basu, Sooraj Puthoor, Joseph L. Greathouse
  • Patent number: 9977968
    Abstract: A method and system for identifying content relevance comprises acquiring video data, mapping the acquired video data to a feature space to obtain a feature representation of the video data, assigning the acquired video data to at least one action class based on the feature representation of the video data, and determining a relevance of the acquired video data.
    Type: Grant
    Filed: March 4, 2016
    Date of Patent: May 22, 2018
    Assignee: Xerox Corporation
    Inventors: Edgar A. Bernal, Qun Li, Yun Zhang, Jayant Kumar, Raja Bala
  • Patent number: 9959238
    Abstract: Message passing is provided among a plurality of interdependent parallel processes using a shared memory. Inter-process communication among a plurality of interdependent processes executing on a plurality of compute nodes is performed by obtaining a message from a first process for a second process; and storing the message in a memory location of a Peripheral Component Interconnect Express (PCIE)-linked storage device, wherein the second process reads the memory location to obtain the message. The message is optionally persistently stored in the PCIE-linked storage device for an asynchronous checkpoint until the message is no longer required for an asynchronous restart.
    Type: Grant
    Filed: December 23, 2014
    Date of Patent: May 1, 2018
    Assignee: EMC IP Holding Company LLC
    Inventors: John M. Bent, Sorin Faibish, James M. Pedone, Jr.
  • Patent number: 9946547
    Abstract: A load/store unit for a processor, and applications thereof. In an embodiment, the load/store unit includes a load/store queue configured to store information and data associated with a particular class of instructions. Data stored in the load/store queue can be bypassed to dependent instructions. When an instruction belonging to the particular class of instructions graduates and the instruction is associated with a cache miss, control logic causes a pointer to be stored in a load/store graduation buffer that points to an entry in the load/store queue associated with the instruction. The load/store graduation buffer ensures that graduated instructions access a shared resource of the load/store unit in program order.
    Type: Grant
    Filed: September 29, 2006
    Date of Patent: April 17, 2018
    Assignee: ARM Finance Overseas Limited
    Inventors: Meng-Bing Yu, Era K. Nangia, Michael Ni
  • Patent number: 9940168
    Abstract: Methods and systems that reduce the number of instance of a shared resource needed for a processor to perform an operation and/or execute a process without impacting function are provided. a method of processing in a processor is provided. Aspects include determining that an operation to be performed by the processor will require the use of a shared resource. A command can be issued to cause a second operation to not use the shared resources N cycles later. The shared resource can then be used for a first aspect of the operation at cycle X and then used for a second aspect of the operation at cycle X+N. The second operation may be rescheduled according to embodiments.
    Type: Grant
    Filed: January 12, 2017
    Date of Patent: April 10, 2018
    Assignee: MIPS Tech, LLC
    Inventor: Debasish Chandra
  • Patent number: 9940139
    Abstract: A split level history buffer in a central processing unit is provided. A history buffer is split into a first portion and a second portion. An instruction fetch unit fetches and tags instructions. A register file stores tagged instructions. An execution unit generates results for tagged instructions. A first instruction is fetched, tagged, and stored in an entry of the register file. A second instruction is fetched and tagged, and then evicts the first instruction from the register file, such that the second instruction is stored in the entry of the register file. Subsequently, the first instruction is stored in an entry in the first portion of the history buffer. After a result for the first instruction is generated, the first instruction is moved from the first portion of the history buffer to the second portion of the history buffer.
    Type: Grant
    Filed: September 20, 2016
    Date of Patent: April 10, 2018
    Assignee: Internaitonal Business Machines Corporation
    Inventors: Hung Q. Le, Dung Q. Nguyen, David R. Terry
  • Patent number: 9891925
    Abstract: An allocation system and a method for allocating an architectural register in a system having one or more mapping tables. When the allocation system detects a plurality of available architectural registers to an allocation target virtual register, it identifies adjacent instructions to all instructions having the allocation target virtual register in its destination operand, counts the number of uses of the architectural register appearing in the destination operand for each architectural register, summing the number of uses for each architectural register for each entry group in one or more mapping tables having the same assignment rule for correlations with the architectural registers, calculating the total of the numbers of uses of entries for each entry group, and allocating the architectural register to the allocation target virtual register such that the total of the numbers of uses of entries for each entry group approaches uniformity.
    Type: Grant
    Filed: October 5, 2016
    Date of Patent: February 13, 2018
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventor: Kazuaki Ishizaki