Mode Switch Or Change Patents (Class 712/229)
  • Patent number: 10564968
    Abstract: First and second types of vector load instruction are provided. For the first type, a response action is performed when an exceptional condition is detected for a load operation performed for a first active data element of at least one vector register, but when the exceptional condition is detected for an active data element other than the first active data element, the response action is suppressed and element identifying information is stored identifying the element which caused the exceptional condition. For the second type, the response action is suppressed and the element identifying information is stored when the exceptional condition arises for any active data element. This approach is useful for allowing loop speculation and loop unrolling to be used together to improve performance of vectorised code.
    Type: Grant
    Filed: September 5, 2016
    Date of Patent: February 18, 2020
    Assignee: ARM Limited
    Inventor: Nigel John Stephens
  • Patent number: 10503636
    Abstract: Examples relate to providing concurrent dead actor collection. In some examples, a blocked notification is received from an actor of a number of actors in a distributed system, where the actors are arranged in an actor hierarchy that describes communication links between the actors. In response to receiving the blocked notification, a blocked status is requested from each other actor in a loop subset of the actors, where each of the other actors is connected to the actor in the actor hierarchy by an incoming edge. After using the blocked status of each of the other actors to determine that incoming edges of the actor refer to blocked actors, the actor is designated for garbage collection.
    Type: Grant
    Filed: June 30, 2014
    Date of Patent: December 10, 2019
    Assignee: HEWLETT PACKARD ENTERPRISE DEVELOPMENT LP
    Inventor: Luis Miguel Vaquero Gonzalez
  • Patent number: 10496510
    Abstract: A method, an information handling system (IHS), and an event logging system generate combined event logs in an IHS. The method includes receiving, via a remote access controller (RAC), a tagged log containing operating system (OS) event data. A hardware log containing hardware event data is retrieved from a RAC memory. The tagged log and the hardware log are combined to form a combined event log containing both OS event data and hardware event data in a uniform format. The combined event log is stored to the RAC memory.
    Type: Grant
    Filed: April 24, 2017
    Date of Patent: December 3, 2019
    Assignee: Dell Products, L.P.
    Inventors: Vaideeswaran Ganesan, Pravin Janakiram, Rajib Saha, Prasoon Sinha
  • Patent number: 10417129
    Abstract: Embodiments of the invention are directed to methods for handling cache prefetch requests. The method includes receiving a request to prefetch data from main memory to a cache. The method further includes based on a determination that the prefetch request is a speculative prefetch request, determining if the cache is being used for transactional memory. The method further includes based on a determination that the cache is not being used for transactional memory, processing the prefetch request. The method further includes based on a determination that the cache is being used for transactional memory, and a determination if the prefetch request can be processed without affecting transactional memory, processing the prefetch request. The method further includes based on a determination that the cache is being used for transactional memory, and a determination if the prefetch request can be processed without affecting transactional memory, rejecting the prefetch request.
    Type: Grant
    Filed: May 8, 2017
    Date of Patent: September 17, 2019
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventor: Shakti Kapoor
  • Patent number: 10394636
    Abstract: A technique for operating a data processing system includes detecting that a processing unit within a first group of processing units in the data processing system has a hang condition. In response to detecting that the processing unit has a hang condition, a command issue rate for the first group of processing units is reduced. One or more other groups of processing units in the data processing system are notified that the first group of processing units has reduced the command issue rate for the first group of processing units. In response to the notifying, respective command issue rates of the other groups of processing units are reduced to reduce a number of commands received by the first group of processing units from the other groups of processing units.
    Type: Grant
    Filed: August 2, 2017
    Date of Patent: August 27, 2019
    Assignee: International Business Machines Corporation
    Inventors: Guy L. Guthrie, Charles Marino, Praveen S. Reddy, Michael S. Siegel
  • Patent number: 10379904
    Abstract: In one embodiment, a processor includes: a first storage to store a set of common performance state request settings; a second storage to store a set of thread performance state request settings; and a controller to control a performance state of a first core based on a combination of at least one of the set of common performance state request settings and at least one of the set of thread performance state request settings. Other embodiments are described and claimed.
    Type: Grant
    Filed: August 31, 2016
    Date of Patent: August 13, 2019
    Assignee: Intel Corporation
    Inventors: Eliezer Weissmann, Israel Hirsh, Efraim Rotem, Doron Rajwan, Avinash N. Ananthakrishnan, Natanel Abitan, Ido Melamed, Guy M. Therien
  • Patent number: 10367547
    Abstract: Systems and methods are provided for optimizing power consumption for power line communication (PLC). An example system may include a coupler that connects the system to a power line; an analog front end (AFE) for handling communications over the power line via the coupler; and a processor for controlling power consumption of the AFE. The processor may determine information regarding one or more control parameters of the analog front end (AFE), the information relating to powerline communications (PLC) over the power line; and based on the information, sets or adjusts the one or more control parameters of the analog front end (AFE), to control power consumption of the analog front end (AFE) during the powerline communications (PLC) over the power line. The analog front end (AFE) may then transmit or receive data over the power line using powerline communications (PLC), based on the one or more control parameters.
    Type: Grant
    Filed: November 17, 2017
    Date of Patent: July 30, 2019
    Assignee: MAXLINEAR ASIA SINGAPORE PRIVATE LIMITED
    Inventors: Lydi Smaini, Alexandre Rouxel
  • Patent number: 10339284
    Abstract: A measurement method, an electronic device, and a measurement system where the electronic device reads, from a hardware storage device, running code and running data that are in a running process of a virtual machine manager (VMM), and generates first verification information according to the running code and the running data, and the electronic device stores the first verification information, and transmits, to a trusted data center, log information generated in a process that is from reading, by the electronic device, the running code and the running data to storing, by the electronic device, the first verification information such that the trusted data center measures the electronic device using the first verification information acquired from the electronic device and second verification information generated according to the log information.
    Type: Grant
    Filed: March 16, 2016
    Date of Patent: July 2, 2019
    Assignee: HUAWEI TECHNOLOGIES CO., LTD.
    Inventors: Jianfeng Liu, Xun Shi, Huanguo Zhang, Fei Yan
  • Patent number: 10289414
    Abstract: Branch prediction is suppressed for branch instructions executing in a transaction of a transactional memory (TM) environment in transactions that are re-executions of previously aborted transactions.
    Type: Grant
    Filed: June 2, 2014
    Date of Patent: May 14, 2019
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Michael K Gschwind, Valentina Salapura, Chung-Lung Shum
  • Patent number: 10261811
    Abstract: Systems and methods for contextually allocating emulation resources for providing an emulation session are disclosed. The method involves a plurality of emulation parameters including the computer product to be emulated, context data defining an emulation context, at least one kind of external resource usable to provide the emulation of the computer product. The method includes receiving an emulation request from a client device; determining a required class of service for providing the emulation based on the context data; determining a plurality of possible resource instances providable by the emulator system; selecting at least one selected resource instance from the plurality of possible resource instances to provide an operating instance of the at least one kind of external hardware resource for the emulation based at least in part on the required class of service; and providing the emulation to the client device using the at least one selected resource instance.
    Type: Grant
    Filed: March 10, 2016
    Date of Patent: April 16, 2019
    Assignee: SPHERE 3D INC.
    Inventors: Giovanni Morelli, Brandon Cowen, Marian Dan
  • Patent number: 10216927
    Abstract: A computerized method is provided for protecting processes operating within a computing device. The method comprises an operation for identifying, by a virtualization layer operating in a host mode, when a guest process switch has occurred. The guest process switch corresponds to a change as to an operating state of a process within a virtual machine. Responsive to an identified guest process switch, an operation is conducted to determine, by the virtualization layer, whether hardware circuitry within the computing device is to access a different nested page table for use in memory address translations. The different nested page table alters page permissions for one or more memory pages associated with at least the process that are executable in the virtual machine.
    Type: Grant
    Filed: June 30, 2016
    Date of Patent: February 26, 2019
    Assignee: FireEye, Inc.
    Inventor: Udo Steinberg
  • Patent number: 10204198
    Abstract: Aspects of the present invention include a method, system and computer program product that provides for improved localized self-heating analysis during IC design. The method includes a processor for modeling a power characteristic and a thermal resistance characteristic for each one of a plurality of locations within a cell that is being designed into an integrated circuit; for performing a self-heating analysis to determine an amount of heat at each one of the plurality of locations within the cell; and for creating a thermal profile for the cell, wherein the thermal profile includes a maximum self-heating value for each of the plurality of locations within the cell and includes an average self-heating value for the cell, and wherein the maximum self-heating value and the average self-heating value are derived from the determined amount of heat at each one of the plurality of locations within the cell.
    Type: Grant
    Filed: January 20, 2017
    Date of Patent: February 12, 2019
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Nagashyamala R. Dhanwada, Arun Joseph, Arya Madhusoodanan, Spandana V. Rachamalla
  • Patent number: 10108670
    Abstract: Methods and systems for sorting a dataset include partitioning the dataset into 2npartitions, where n is a number of available processors. A first quicksort is performed in parallel across pairs of partitions based on a pivot using a plurality of processors. A second quicksort is performed in parallel on unsorted elements within each partition based on the pivot, where the unsorted elements were left unsorted by the first quicksort. Misplaced elements from a left side of the dataset are swapped with misplaced elements from a right side of the dataset to produce a left dataset that has elements equal to or lower than the pivot and a right dataset that has elements equal to or higher than the pivot.
    Type: Grant
    Filed: August 19, 2015
    Date of Patent: October 23, 2018
    Assignee: International Business Machines Corporation
    Inventors: Daniel Brand, Minsik Cho, Ruchir Puri
  • Patent number: 10055227
    Abstract: Systems and methods for tracking and switching between execution modes in processing systems. A processing system is configured to execute instructions in at least two instruction execution triodes including a first and second execution mode chosen from a classic/aligned mode and a compressed/unaligned mode. Target addresses of selected instructions such as calls and returns are forcibly misaligned in the compressed mode, such one or more bits, such as, the least significant bits (alignment bits) of the target address in the compressed mode are different from the corresponding alignment bits in the classic mode. When the selected instructions are encountered during execution in the first mode, a decision to switch operation to the second mode is based on analyzing the alignment bits of the target address of the selected instruction.
    Type: Grant
    Filed: October 19, 2012
    Date of Patent: August 21, 2018
    Assignee: QUALCOMM Incorporated
    Inventors: Charles Joseph Tabony, Erich James Plondke, Lucian Codrescu, Suresh K. Venkumahanti, Evandro Carlos Menezes
  • Patent number: 10025741
    Abstract: A system-on-chip (SoC) to perform a deadlock control on a processor of the SoC, the SoC including the processor including a plurality of central processing unit (CPU) cores, a first bus connected to the processor, a graphic processing unit (GPU) connected to the first bus, a memory controller connected to the first bus, a second bus connected to the processor, an isolation cell including a logic circuit configured to retain a signal value input to the processor according to an isolation signal, and a deadlock controller connected to the first bus and the second bus. The deadlock controller is configured to isolate the processor, which is in a deadlock state, from the first bus by applying the isolation signal on the isolation cell, and to extract, via the second bus, state information of the isolated processor in the deadlock state.
    Type: Grant
    Filed: January 13, 2016
    Date of Patent: July 17, 2018
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Jae-Youl Kim, Chih Jen Lin, Jinook Song, Sungjae Lee, Hyun-ki Koo, Donghyeon Ham
  • Patent number: 9965310
    Abstract: Technologies are generally described for systems, devices and methods effective to implement a virtual machine exit analyzer. A virtual machine handler may receive a request that includes an instruction. The instruction may include a port and a data block identifier. The virtual machine handler may generate a modified request. The modified request may include the port, a block portion identifier and an identification of a comparator. The virtual machine handler may send values identified by the block portion identifier to the comparator. The virtual machine handler may receive an exit indicator from the comparator that indicates whether the virtual machine should exit the core.
    Type: Grant
    Filed: August 28, 2013
    Date of Patent: May 8, 2018
    Assignee: EMPIRE TECHNOLOGY DEVELOPMENT LLC
    Inventor: Ezekiel Kruglick
  • Patent number: 9952871
    Abstract: An apparatus comprises a processing pipeline comprising out-of-order execution circuitry and second execution circuitry. Control circuitry monitors at least one reordering metric indicative of an extent to which instructions are executed out of order by the out-of-order execution circuitry, and controls whether instructions are executed using the out-of-order execution circuitry or the second execution circuitry based on the reordering metric. A speculation metric indicative of a fraction of executed instructions that are flushed due to a mis-speculation can also be used to determine whether to execute instructions on first or second execution circuitry having different performance or energy consumption characteristics.
    Type: Grant
    Filed: June 5, 2015
    Date of Patent: April 24, 2018
    Assignee: ARM Limited
    Inventors: Ian Michael Caulfield, Peter Richard Greenhalgh, Simon John Craske, Max John Batley, Allan John Skillman, Antony John Penton
  • Patent number: 9916243
    Abstract: A method and apparatus for performing a bus lock and a translation lookaside buffer invalidate transaction includes receiving, by a lock master, a lock request from a first processor in a system. The lock master sends a quiesce request to all processors in the system, and upon receipt of the quiesce request from the lock master, all processors cease issuing any new transactions and issue a quiesce granted transaction. Upon receipt of the quiesce granted transactions from all processors, the lock master issues a lock granted message that includes an identifier of the first processor. The first processor performs an atomic transaction sequence and sends a first lock release message to the lock master upon completion of the atomic transaction sequence. The lock master sends a second lock release message to all processors upon receiving the first lock release message from the first processor.
    Type: Grant
    Filed: October 23, 2014
    Date of Patent: March 13, 2018
    Assignee: Advanced Micro Devices, Inc.
    Inventors: William L. Walker, Paul J. Moyer, Richard M. Born, Eric Morton, David Christie, Marius Evers, Scott T. Bingham
  • Patent number: 9846571
    Abstract: A device generates a model associated with a multi-rate system. The multi-rate system includes a system associated with a clock rate and a sample rate, and the clock rate is greater than the sample rate. The device identifies the clock rate of the multi-rate system based on the model, and identifies a portion, of the model, associated with the sample rate. The device applies clock rate pipelining to adjust the sample rate associated with the portion of the model so that the sample rate substantially equals the clock rate, and generates code associated with the model and the applied clock rate pipelining.
    Type: Grant
    Filed: January 14, 2015
    Date of Patent: December 19, 2017
    Assignee: The MathWorks, Inc.
    Inventors: Girish Venkataramani, Yongfeng Gu, Wang Chen
  • Patent number: 9836810
    Abstract: The present disclosure provides systems and methods for multi-path rendering on tile based architectures including executing, with a graphics processing unit (GPU), a query pass, executing, with the GPU, a condition true pass based on the query pass without executing a flush operation, executing, with the GPU, a condition false pass based on the query pass without executing a flush operation, and responsive to executing the condition true pass and the condition false pass, executing, with the GPU, a flush operation.
    Type: Grant
    Filed: February 1, 2016
    Date of Patent: December 5, 2017
    Assignee: QUALCOMM Incorporated
    Inventors: Murat Balci, Christopher Paul Frascati, Avinash Seetharamaiah
  • Patent number: 9762771
    Abstract: The storage section of the multifunction peripheral stores location information containing a storage location of software which transmits a control command whose execution is permissible. The execution permission judging section of the multifunction peripheral includes (I) a storage location detecting section which detects a storage location of software which has participated in a transmission of a received control command and (II) a command permitting/prohibiting section which (i) prohibits execution of the received control command when a storage location indicated by the location information is not detected by the storage location detecting section but (ii) permits execution of the received control command when the storage location is detected by the storage location detecting section.
    Type: Grant
    Filed: September 18, 2015
    Date of Patent: September 12, 2017
    Assignee: SHARP KABUSHIKI KAISHA
    Inventor: Akihiro Okamura
  • Patent number: 9753738
    Abstract: In some examples, a privileged domain includes a function of a Basic Input/Output System (BIOS). A request to access the function of the BIOS is routed to the privileged domain. The privileged domain determines whether to execute the function based on identifying at least one selected from among a source of the request and a context of the request.
    Type: Grant
    Filed: October 21, 2011
    Date of Patent: September 5, 2017
    Assignee: Hewlett-Packard Development Company, L.P.
    Inventors: Valiuddin Y. Ali, Jose Paulo Xavier Pires, James M. Mann, Boris Balacheff, Chris I. Dalton
  • Patent number: 9753799
    Abstract: A microprocessor comprises a cache including a tag array; a tag pipeline that arbitrates access to the tag array; and a pattern detector. The pattern detector comprises snapshot capture logic that captures snapshots of tagpipe arbs—including information about whether the tagpipe arb is a load, snoop, store or other arb type and whether the tagpipe arb completed or replayed—and a plurality of configurable register modules operable to store user-configured snapshot patterns. Configuration logic enables a user to specify, for each configurable register module, properties of tagpipe arbs for the pattern detector to detect as well as dependencies between the configurable register modules. A register module becomes triggered if a tagpipe arb or pattern of tagpipe arbs meets the user-specified properties for the register module and if any other register module on which the register module depends is also in a triggered state.
    Type: Grant
    Filed: December 13, 2014
    Date of Patent: September 5, 2017
    Assignee: VIA ALLIANCE SEMICONDUCTOR CO., LTD.
    Inventors: Rodney E. Hooker, Douglas R. Reed
  • Patent number: 9742847
    Abstract: A network of sensor and controller nodes having the ability to be dynamically programmed and receive updated software from one another, and from a host system. Each network node includes multiple state machines, at least some of which are operable relative to physical pins at the network node; the physical pins correspond to inputs from sensor functions or outputs to control functions. The network nodes include microcontrollers that are operable in an operating mode to execute a state machine and respond to commands from other nodes or the host, and in a read mode to receive and store program instructions transmitted from other nodes or the host. A learn mode is also provided, by way of which a network node can store program code corresponding to instructions and actions at the node when under user control.
    Type: Grant
    Filed: August 30, 2013
    Date of Patent: August 22, 2017
    Assignee: Texas Instruments Incorporated
    Inventors: Leonardo William Estevez, Sriram Narayanan
  • Patent number: 9715720
    Abstract: System and methods are provided for performing image noise reduction. A pixel having an initial pixel value is selected from an image for performing noise reduction, wherein the image is stored in a data structure in a non-transitory computer-readable storage medium. A block window including a plurality of pixel blocks associated with the selected pixel is determined, wherein a pixel block includes a plurality of pixels. A plurality of pixel block average values for the plurality of pixel blocks are calculated, wherein a pixel block average value corresponds to an average pixel value of a pixel block. A weighted average of the plurality of pixel block average values with respect to the selected pixel is calculated using a bilateral filtering algorithm. The data structure is updated by replacing the initial pixel value of the selected pixel with the weighted average of the plurality of pixel block average values.
    Type: Grant
    Filed: September 18, 2015
    Date of Patent: July 25, 2017
    Assignee: MARVELL INTERNATIONAL LTD.
    Inventors: Hongxin Li, Wenyi Su
  • Patent number: 9652262
    Abstract: This follows a data processing system comprising multiple GPUs includes instruction queue circuitry storing data specifying program instructions for threads awaiting issue for execution. Instruction characterization circuitry determines one or more characteristics of the program instructions awaiting issue within the instructional queue circuitry and supplies this to operating parameter control circuitry. The operating parameter control circuitry alters one or more operating parameters of the system in response to the one or more characteristics of the program instructions awaiting issue.
    Type: Grant
    Filed: October 9, 2014
    Date of Patent: May 16, 2017
    Assignee: The Regents of the University of Michigan
    Inventors: Ankit Sethia, Scott Mahlke
  • Patent number: 9588770
    Abstract: Reconfiguring a register file using a rename table having a plurality of fields that indicate fracture information about a source register of an instruction for instructions which have narrow to wide dependencies.
    Type: Grant
    Filed: March 15, 2013
    Date of Patent: March 7, 2017
    Assignee: Samsung Electronics Co., LTD.
    Inventors: Bradley Gene Burgess, Ashraf Ahmed, Ravi Iyengar
  • Patent number: 9588863
    Abstract: One aspect is a method that includes analyzing, by a processor of an analysis system, an instruction set architecture of a targeted complex-instruction set computer (CISC) processor to generate an instruction set profile for each CISC architectural instruction variant of the instruction set architecture. A combination of instruction sequences for the targeted CISC processor is determined from the instruction set profile that corresponds to a desired stressmark type. The desired stressmark type defines a metric representative of functionality of interest of the targeted CISC processor. Performance of the targeted CISC processor is monitored with respect to the desired stressmark type while executing each of the instruction sequences. One of the instruction sequences is identified as most closely aligning with the desired stressmark type based on performance results of execution of the instruction sequences with respect to the desired stressmark type.
    Type: Grant
    Filed: October 21, 2014
    Date of Patent: March 7, 2017
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Ramon Bertran, Pradip Bose, Alper Buyuktosunoglu, Timothy J. Slegel
  • Patent number: 9541992
    Abstract: A method of performing a dynamic voltage and frequency scaling operation comprises controlling a clock management unit (CMU) to predict an operating state of a central processing unit (CPU) and to provide operating frequency information to a power management integrated circuit (PMIC) based on the predicted operating state of the CPU, the operating frequency information indicating a change of an operating frequency of an application processor, and controlling the PMIC to change an operating voltage of the application processor based on the operating frequency information provided from the clock management unit.
    Type: Grant
    Filed: September 10, 2013
    Date of Patent: January 10, 2017
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Jae-Gon Lee, Taek-Kyun Shin, Sang-Jung Jeon, Jin-Sub Choi
  • Patent number: 9477469
    Abstract: Branch prediction is suppressed for specific branch instructions executing in a transaction of a transactional memory (TM) environment, when the specific branch instruction was previously executed in the transaction, in one embodiment the specific branch instruction is suppressed after a predetermined number of executions of the specific instruction in a transaction.
    Type: Grant
    Filed: June 2, 2014
    Date of Patent: October 25, 2016
    Assignee: International Business Machines Corporation
    Inventors: Michael K Gschwind, Valentina Salapura, Chung-Lung Shum
  • Patent number: 9460281
    Abstract: A method to secure a non-native application. The non-native application is processed to obtain an application stub to be triggered within a virtual machine. The processing of the non-native application also provide a native code function upon which the application stub depends. The non-native function is part of a trusted module that extends security services from the trusted module to the virtual machine. The trusted module is a native code application that creates a trusted zone as a root of trustiness extending to the virtual machine by an execution-enabling mechanism between the application tab and the non-native function.
    Type: Grant
    Filed: March 31, 2011
    Date of Patent: October 4, 2016
    Assignee: Irdeto B.V.
    Inventors: Garney David Adams, Yuan Xiang Gu, Jack Jiequn Rong
  • Patent number: 9378002
    Abstract: An apparatus for providing memory footprint reduction for classes of an application programming interface includes a comparing element and a set selection element. The comparing element may be configured to receive a reference class file and one or more modified class files for each of a plurality of classes and to compare a size of each of the one or more modified class files and the reference class file. The set selection element may be in communication with the comparing element. The set selection element may be configured to select one of the one or more modified class files or the reference class file based at least in part on the size of each of the one or more modified class files and the reference class file as a selected file for each corresponding one of the classes and to form a class set comprising the selected file for each corresponding one of the classes.
    Type: Grant
    Filed: December 22, 2006
    Date of Patent: June 28, 2016
    Assignee: Core Wireless Licensing S.a.r.l.
    Inventor: Juha Uola
  • Patent number: 9378021
    Abstract: A processor includes a cache, a prefetcher module to select information according to a prefetcher algorithm, and a prefetcher algorithm selection module. The prefetcher algorithm selection module includes logic to select a candidate prefetcher algorithm determine and store memory addresses of predicted memory accesses of the candidate prefetcher algorithm when performed by the prefetcher module, determine cache lines accessed during memory operations, and evaluate whether the determined cache lines match the stored memory addresses. The prefetcher algorithm selection module further includes logic to adjust an accuracy ratio of the candidate prefetcher algorithm, compare the accuracy ratio with a threshold accuracy ratio, and determine whether to apply the first candidate prefetcher algorithm to the prefetcher module.
    Type: Grant
    Filed: February 14, 2014
    Date of Patent: June 28, 2016
    Assignee: Intel Corporation
    Inventors: Zeshan A. Chishti, Christopher B. Wilkerson, Seth Pugsley, Peng-Fei Chuang, Robert L. Scott, Aamer Jaleel, Shih-Lien L. Lu, Kingsum Chow
  • Patent number: 9372773
    Abstract: A processor, a method and a computer-readable medium for recording branch addresses are provided. The processor comprises hardware registers and first and second circuitry. The first circuitry is configured to store a first address associated with a branch instruction in the hardware registers. The first circuitry is further configured to store a second address that indicates where the processor execution is redirected to as a result of the branch instruction in the hardware registers. The second circuitry is configured to, in response to a second instruction, retrieve a value of at least one of the registers. The second instruction can be a user-level instruction.
    Type: Grant
    Filed: June 12, 2013
    Date of Patent: June 21, 2016
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Joseph Lee Greathouse, Anton Chernoff
  • Patent number: 9367325
    Abstract: A method is described that includes deciding to migrate a thread from a first processing core to a second processing core. The method also includes automatically in hardware migrating first context of the thread of the first processing core whose register definition is also found on the second processing core to the second processing core. The method also includes automatically in hardware migrating second context of the thread of the first processing core whose register definition is not found on the second processing core to a first storage location external to the second processing core. The message also includes automatically in hardware migrating third context of the thread from a second storage location external to the second processing core to register definition found on the second processing core but not found on the first processing core.
    Type: Grant
    Filed: June 29, 2013
    Date of Patent: June 14, 2016
    Assignee: Intel Corporation
    Inventors: Bret Toll, Jason W. Brandt, John Holm
  • Patent number: 9367455
    Abstract: The described embodiments include a core that uses predictions for store-to-load forwarding. In the described embodiments, the core comprises a load-store unit, a store buffer, and a prediction mechanism. During operation, the prediction mechanism generates a prediction that a load will be satisfied using data forwarded from the store buffer because the load loads data from a memory location in a stack. Based on the prediction, the load-store unit first sends a request for the data to the store buffer in an attempt to satisfy the load using data forwarded from the store buffer. If data is returned from the store buffer, the load is satisfied using the data. However, if the attempt to satisfy the load using data forwarded from the store buffer is unsuccessful, the load-store unit then separately sends a request for the data to a cache to satisfy the load.
    Type: Grant
    Filed: September 5, 2013
    Date of Patent: June 14, 2016
    Assignee: ADVANCED MICRO DEVICES, INC.
    Inventors: Yasuko Eckert, Lena E. Olson, Srilatha Manne, James M. O'Connor
  • Patent number: 9311641
    Abstract: The present disclosure involves a system that includes a computer memory storage component configured to store computer programming instructions and a computer processor component operatively coupled to the computer memory storage component. The computer processor component is configured to run a secure operating system and a non-secure operating system in parallel. The secure and non-secure operating systems are isolated from each other. The computer processor component is configured to execute code to perform the following operations: receiving an authentication request from an application that is run by the non-secure operating system, wherein the authentication request contains credentials of the application; communicating with a secure applet that is run by the secure operating system, and wherein the communicating includes transferring the credentials of the application to the secure applet; and authenticating and vetting the application based on the credentials of the application.
    Type: Grant
    Filed: December 2, 2014
    Date of Patent: April 12, 2016
    Assignee: PayPal, Inc.
    Inventors: Sebastien Ludovic Jean Taveau, Hadi Nahari
  • Patent number: 9213585
    Abstract: A method and apparatus are described for performing sprinting in a processor. An analyzer in the processor may monitor thermal capacity remaining in the processor while not sprinting. When the remaining thermal capacity is sufficient to support sprinting, the analyzer may perform sprinting of a new workload when a benefit derived by sprinting the new workload exceeds a threshold and does not cause the remaining thermal capacity in the processor to be exhausted. The analyzer may perform sprinting of the new workload in accordance with sprinting parameters determined for the new workload. The analyzer may continue to monitor the remaining thermal capacity while not sprinting when the benefit derived by sprinting the new workload does not exceed the threshold.
    Type: Grant
    Filed: June 24, 2013
    Date of Patent: December 15, 2015
    Assignee: ADVANCED MICRO DEVICES, INC.
    Inventors: Manish Arora, Nuwan Jayasena, Michael Schulte
  • Patent number: 9135010
    Abstract: Systems and methods are disclosed for processing data. In accordance with one implementation, a processor may include an arithmetic logic unit (ALU). The processor may also include pipeline circuitry to, in a non-error correction code (ECC) operating mode, execute a sequence of single-cycle instructions in the ALU in a first execution stage, and in an ECC operating mode, execute the same sequence of single-cycle instructions in the ALU in a second execution stage instead of the first execution stage. Further, the processor may include mode control signaling to configure the pipeline circuitry between the non-ECC and ECC operating modes.
    Type: Grant
    Filed: January 25, 2013
    Date of Patent: September 15, 2015
    Assignee: Rambus Inc.
    Inventors: William C. Moyer, Jeffrey W. Scott
  • Patent number: 9052916
    Abstract: Embodiments include methods, apparatus, and systems using a system read only memory (ROM) with an embedded disk image. One method of software execution includes embedding a disk image in a system read only memory (ROM) of a computer system; exporting the disk image through a universal serial bus (USB) interface after an operating system (OS) of the computer system loads; and executing software in the disk image in the computer system.
    Type: Grant
    Filed: September 21, 2006
    Date of Patent: June 9, 2015
    Assignee: Hewlett-Packard Development Company, L.P.
    Inventor: Darren Cepulis
  • Patent number: 9047068
    Abstract: Management information for managing thermal conditions within an information handling system is retrieved from a storage device drive information area by request to a logical block address associated with the management information. The controller of the storage device maps the logical block address to the drive information area to respond to the request to the logical block address with the management information. For example, storage device temperature information measured with a temperature sensor of the storage device and stored to a log page or diagnostics page of the storage device maps from the drive information area to the logical block address so that a controller of the storage device responds with the log page or diagnostics page when a request is made to the logical block address.
    Type: Grant
    Filed: October 31, 2011
    Date of Patent: June 2, 2015
    Assignee: Dell Products L.P.
    Inventor: David M. Pereira
  • Patent number: 9043585
    Abstract: In an example embodiment, there is described herein an apparatus comprising an interface for communicating with a plurality of digital signal processors and logic operable to send and receive data via the interface. The logic is configured to determine a first set of digital signal processors to be maintained in a ready state, a second set of digital signal processors to be maintained in a first energy saving state, and a third set of digital signal processors to be maintained in a second energy saving state.
    Type: Grant
    Filed: March 31, 2010
    Date of Patent: May 26, 2015
    Assignee: CISCO TECHNOLOGY, INC.
    Inventors: Ming Chen, Prasad Miriyala, Ramakrishnan Kunnath, Jing Li
  • Patent number: 9032191
    Abstract: A hypervisor and one or more guest operating systems resident in a data processing system and hosted by the hypervisor are configured to selectively enable or disable branch prediction logic through separate hypervisor-mode and guest-mode instructions. By doing so, different branch prediction strategies may be employed for different operating systems and user applications hosted thereby to provide finer grained optimization of the branch prediction logic for different operating scenarios.
    Type: Grant
    Filed: January 23, 2012
    Date of Patent: May 12, 2015
    Assignee: International Business Machines Corporation
    Inventors: Adam J. Muff, Paul E. Schardt, Robert A. Shearer, Matthew R. Tubbs
  • Publication number: 20150127928
    Abstract: A processor is described herein that is configured to switch between a first instruction issue mode of the processor and a second instruction issue mode of the processor based at least in part on a characteristic associated with a plurality of instructions. The first instruction issue mode and the second instruction issue mode are associated with different energy consumption characteristics. Also, the first instruction issue mode may be an out-of-order instruction issue mode and the second instruction issue mode may be an in-order instruction issue mode.
    Type: Application
    Filed: November 7, 2013
    Publication date: May 7, 2015
    Applicant: Microsoft Corporation
    Inventors: Douglas C. Burger, Aaron L. Smith
  • Publication number: 20150121048
    Abstract: A processor core includes a front end, and first and second back ends, the front end including a fetch engine configured to retrieve the sequence of data processing instructions for both the first back end and the second back end from a memory, and the first and second back ends are each configured to execute the sequence of program instructions. The core operates in a first mode in which the first back end is active and receives the sequence of data processing instructions from the fetch engine and the second back end is inactive, and a second mode in which the first back end is inactive and the second back end is active and receives the sequence of data processing instructions from the fetch engine, where the cycles-per-instruction rate is lower and energy consumption is higher for the first mode than the second mode.
    Type: Application
    Filed: November 29, 2013
    Publication date: April 30, 2015
    Applicant: THE REGENTS OF THE UNIVERSITY OF MICHIGAN
    Inventors: Andrew LUKEFAHR, Reetuparna DAS, Shruti PADMANABHA, Scott MAHLKE
  • Patent number: 9021126
    Abstract: A data processing apparatus includes multiple processing means that are connected in a ring shape via corresponding communication means respectively. Each communication means includes a reception means for receiving data from a previous communication means, and a transmission means for transmitting data to a next communication means. Connection information is assigned to each of the reception means and the transmission means. The communication means, when receiving a packet that has same connection information as one assigned to its reception means, causes the corresponding processing means to perform data processing on the packet, sets the connection information assigned to its transmission means to the packet, and transmits the packet to the next communication means, and when receiving a packet that has connection information that is not same as one assigned to its reception means, transmits the packet to the next communication means without changing the connection information of the packet.
    Type: Grant
    Filed: January 15, 2010
    Date of Patent: April 28, 2015
    Assignee: Canon Kabushiki Kaisha
    Inventor: Hisashi Ishikawa
  • Patent number: 9021239
    Abstract: The disclosure relates to the implementation of multi-tasking on a digital signal processor. Blocking functions are arranged such that they do not make use of a processor's hardware stack. Respective function calls are replaced with a piece of inline assembly code, which instead performs a branch to the correct routine for carrying out said function. If a blocking condition of the blocking function is encountered, a task switch can be done to resume another task. Whilst the hardware stack is not used when a task switch might have to occur, mixed-up contents of the hardware stack among function calls performed by different tasks are avoided.
    Type: Grant
    Filed: April 7, 2006
    Date of Patent: April 28, 2015
    Assignee: NXP, B.V.
    Inventor: Tomas Henriksson
  • Patent number: 9015450
    Abstract: Embodiments of a processor architecture efficiently implement shadow registers in hardware. A register system in a processor includes a set of physical data registers coupled to register renaming logic. The register renaming logic stores data in and retrieves data from the set of physical registers when the processor is in a first processor state. The register renaming logic identifies ones of the set of physical registers that have a first operational state as a first group of registers and identifies the remaining ones of the set of physical registers as a second group of registers in response to an indication that the processor is to enter a second processor state from the first processor state. The register renaming logic stores data in and retrieves data from the second group of registers but not the first group of registers when the processor is in the second processor state.
    Type: Grant
    Filed: January 20, 2010
    Date of Patent: April 21, 2015
    Assignee: STMicroelectronics (Beijing) R&D Co. Ltd.
    Inventors: Hong-Xia Sun, Peng Fei Zhu, Yong Qiang Wu
  • Publication number: 20150106601
    Abstract: The present invention provides a mobile device adopting multicore processors in which each of multiple applications are automatically configured in corresponding processing modes stored in an established table. When one of the application is operated, looking up the table to select the corresponding processing mode. The mobile device automatically switches to the corresponding processing mode. Since the cores in the processor are allocated according to demands, the speed of processing and the power consumption get balanced.
    Type: Application
    Filed: August 15, 2013
    Publication date: April 16, 2015
    Inventor: Dawei Ye
  • Patent number: RE45458
    Abstract: An apparatus and method for performing a shuffle operation on packed data using computer-implemented steps is described. In one embodiment, a first packed data operand having at least two data elements is accessed. A second packed data operand having at least two data elements is accessed. One of the data elements in the first packed data operand is shuffled into a lower destination field of a destination register, and one of the data elements in the second packed data operand is shuffled into an upper destination field of the destination register.
    Type: Grant
    Filed: March 21, 2002
    Date of Patent: April 7, 2015
    Assignee: Intel Corporation
    Inventors: Patrice Roussel, Srinivas Chennupaty, Micheal D. Cranford, Mohammed A. Abdallah, James Coke, Katherine Kong