Abstract: Methods and systems for on-chip processing of data are disclosed. Aspects of the method may include generating a plurality of data processing commands for data compression. A first string of characters may be encoded in one operating cycle utilizing the generated plurality of data processing commands for data compression. The plurality of data processing commands may comprise a branch command, a register moving command, a register setting command, a memory load command, a memory store command, and/or a register compare command. The generated plurality of data processing commands may be stored. At least a portion of the stored data processing commands may be decoded. The decoded portion of the stored data processing commands may be sequenced. The first string of characters may be acquired from a character space. The acquired first string of characters may be matched with at least one existing codeword.

Abstract: According to the invention, a processing core (12) comprising a processing pipeline (100) having N-number of processing paths (56), each of which process instructions (54) on M-bit data words. In addition, the processing core (12) includes one or more register files (60), each preferably having Q-number of registers which are M-bits wide. Preferably, one of the Q-number of registers in at least one of the register files (60) is a program counter register dedicated to hold a program counter, and one of the Q-number of registers in at least one of the register files is a zero register dedicated to hold a zero value. In this manner, program jumps can be executed by adding values to the program counter in the program counter register, and memory address values can be calculated by adding values to the program counter stored in the program counter register or to the zero value stored in the zero register.

Abstract: A method for controlling functional units in a processor, according to which in a configuration a sequence of primary instruction words which consists of several instruction word parts and originates from a translation of a program code is compressed and stored as a sequence of associated program words. The invention also relates to a processor system for carrying out this method. The aim of the invention is to increase operating speed in an application-specific manner while retaining a low program word width. To this end, as regards the method, a program word contains a first characteristic of a primary instruction word and instruction word parts which differentiate the primary instruction word belonging to the program word from the primary instruction word belonging to the characteristic.

Abstract: The invention relates to a method and an arrangement for instruction word generation in the controlling of functional units in a processor, the instruction words comprising a plurality of instruction word parts. In this case, in a program sequence, under the control of a program word, an instruction word is taken from a row—determined by a reading row number—of an instruction word memory that can be written to row by row, the said instruction word is altered by means of substitution of an instruction word part by the information part of the respective program word and is written back to a row of the instruction word memory, the said row being determined by a writing row number. Afterwards, an instruction word—which is generated in this way and is to be executed in accordance with the program—for controlling the functional units is output to the processor.

Abstract: A processor is described in which the need to encode no-operation instructions (nops) in the program is minimised by providing a device for generating nops in response to information encoded in operative instructions.

Abstract: A method and system for fixed-length memory-to-memory processing of fixed-length instructions. Further, the present invention is a method and system for implementing a memory operand width independent of the ALU width. The arithmetic and register data are 32 bits, but the memory operand is variable in size. The size of the memory operand is specified by the instruction. Instructions in accordance with the present invention allow for multiple memory operands in a single fixed-length instruction. The instruction set is small and simple, so the implementation is lower cost than traditional processors. More addressing modes are provided for, thus creating a more efficient code. Semaphores are implemented using a single bit. Shift-and-merge instructions are used to access data across word boundaries.

Abstract: The present invention is a system in which a multiplicity of diverse dedicated hardware off-core execution units are connected to a core processor in order to increase the speed, power, and flexibility of the processor, and a method of operating the system. Reference instructions executed by the core processor initiate the execution of Configurable Long Instruction Word (CLIW) instructions stored in a CLIW memory. The operation of the off-core execution units is controlled by CLIW instructions. These CLIW instructions may also control operations performed by the core processor, and may be in addition to any other CLIW instructions that control the core processor exclusively. The off-core logic units are operationally connected to the data memory of the core processor under the control of the core processor's data address logic.

Abstract: A computing system as described in which individual instructions are executable in parallel by processing pipelines, and instructions to be executed in parallel by different pipelines are supplied to the pipelines simultaneously. The system includes storage for storing an arbitrary number of the instructions to be executed. The instructions to be executed are tagged with pipeline identification tags indicative of the pipeline to which they should be dispatched. The pipeline identification tags are supplied to a system which controls a crossbar switch, enabling the tags to be used to control the switch and supply the appropriate instructions simultaneously to the differing pipelines.

Abstract: A signal processing device and method of supplying a signal processing result to a plurality of registers arranged in different register files. A plurality of different register files are selected based on a corresponding indication in said instruction word and the register address is supplied to said selected register files. Result values can be broadcasted to multiple registers in a single processor cycle while a copy operation between different register files is eliminated. Broadcasting is thus implemented via overlapping register address spaces, since physical registers having the same logical register address are provided in different register files.

Abstract: A multiprocessor data processing system for executing a program having branch instructions therein, each branch instruction specifying a target address in the program defining an instruction that is to be executed if that branch instruction causes the program to branch. The data processing system includes a plurality of processing sections having a function unit, a local memory, and a pointer. The local memory stores instruction sequences from the program that is to be executed by the function unit in that processing section. The pointer contains a value defining the next instruction in the local memory to be executed by the function unit. Each function unit executes instructions according to machine cycles, each function unit executing one instruction per machine cycle. The pointers in each of the processing sections are reset to a new value determined by the target address of one of the branch instructions when a function unit branches in response to that branch instruction.

Abstract: A processing core comprising R-number of processing pipelines each comprising N-number of processing paths. Each of the R-number of processing pipelines are synchronized together to operate as a single very long instruction word (VLIW) processing core. The VLIW processing core is configured to process R×N-number of VLIW sub-instructions in parallel. In addition, the R-number of pipelines can be configured to operate independently as separately operating pipelines. In accordance with one embodiment of the present invention, each of the R-number of processing pipelines comprises S-number of register files, such that the processing core comprises R×S-number of register files. In accordance with another embodiment of the present invention, each of the R-number of processing pipelines comprises one register file for every two of the N-number of processing paths, such that S=N/2.

Abstract: A method and apparatus are disclosed for allocating functional units in a multithreaded very large instruction word (VLIW) processor. The present invention combines the techniques of conventional VLIW architectures and conventional multithreaded architectures to reduce execution time within an individual program, as well as across a workload. The present invention utilizes a compiler to detect parallelism. The disclosed multithreaded VLIW architecture exploits program parallelism by issuing multiple instructions, in a similar manner to single threaded VLIW processors, from a single program sequencer, and also supports multiple program sequencers, as in simultaneous multithreading. Instructions are allocated to functional units to issue multiple VLIW instructions to multiple functional units in the same cycle. The allocation mechanism of the present invention occupies a pipeline stage just before arguments are dispatched to functional units.

Abstract: The invention is a system and method for executing a program that comprises a plurality of basic blocks on a computer system that comprises a plurality of processing elements. The invention generates a branch instruction by one processing element of the plurality of processing elements, sends the branch instruction to the plurality of processing elements. The invention then independently branches to a target of the branch instruction by each of the processing elements of the plurality of processing elements when each processing element receives the sent branch instruction. At least one processing element of the plurality of processing elements receives the branch instruction at a time later than another processing element of the plurality of processing elements.

Abstract: According to the invention, a processing core is disclosed. The processing core includes one or more processing pipelines and a number of register flies. The processing pipelines having a total of N-number of processing paths, where each of the processing paths processes instructions on M-bit data words. Each of the number of register files has Q-number of registers that are each M-bits wide. The Q-number of registers within each of the plurality of register files are either private or global registers. When a value is written to one of said Q-number of said registers, which is a global register within one of said number of register files, the value is propagated to a corresponding global register in the other of the number of register files. When a value is written to one of said Q-number of the registers, which is a private register within one of said number of register files, the value is not propagated to a corresponding register in the other of said number of register files.

Abstract: A time multiplex changing function for priorities among threads is added to a multi-thread processor, and capability for large-scale out-of-order execution is achieved by confining the flows of data among threads, prescribing the execution order in the flow sequence, and executing a plurality of threads having data dependency either simultaneously or in time multiplex.

Abstract: As far as multimedia processing is concerned, a plurality of computations of a same type are often executed concurrently and hence a plurality of computing units having a same function are used and mode information for controlling the plurality of units by an instruction unit for one computing unit is prepared in each instruction to execute a plurality of computations with a single instruction.

Abstract: A processor that has a plurality of instruction slots each of which stores an instruction to be executed in parallel. One of the plurality of instruction slots is a first instruction slot and another a second instruction slot. A special instruction stored in the first instruction slot is executed by a first functional unit that executes instructions stored in the first instruction slot, and a second functional unit that executes instructions stored in the second instruction slot. An instruction stored in the second instruction slot is executed in parallel by a third functional unit that executes instructions stored in the second instruction slot.

Abstract: A data processor can assign a greater number of operations to instruction codes with shorter length, thereby implementing high performance, high code efficiency and low cost data processor. The data processor is a VLIW (Very Long Instruction Word) system that can execute a plurality of operations in parallel, and specify the execution sequence of the operations. It can assign a plurality of operations to the same operation code, and the operations that are executed in a second or subsequent sequence are limited to only predetermined operations among the plurality of operations.

Abstract: For use in a data processor comprising an instruction execution pipeline comprising N processing stages, a system and method of encoding constant operands is disclosed. The system comprises a constant generator unit that is capable of generating both short constant operands and long constant operands. The constant generator unit extracts the bits of a short constant operand from an instruction syllable and right justifies the bits in an output syllable. For long constant operands, the constant generator unit extracts K low order bits from an instruction syllable and T high order bits from an extension syllable. The right justified K low order bits and the T high order bits are combined to represent the long constant operand in one output syllable. In response to the status of op code bits located within a constant generation instruction, the constant generator unit enables and disables multiplexers to automatically generate the appropriate short or long constant operand.

Abstract: An apparatus and method for creating instruction groups for explicitly parallel architectures is provided. The apparatus and method accept instruction groups as input and determine a number of each possible type of instruction in the instruction group. Based on the number of each possible type of instruction in the instruction group, instruction bundling is performed such that the instructions in the instruction group are bundled into efficiently executed bundles. The instruction bundling further accommodates intra-bundle stop bundles in the event that more efficient bundles are not possible. The instruction bundling is performed based on a most restrictive instruction type placement first and proceeds to less restrictive instruction type placement.

Abstract: A subpipelined translation embodiment provides binary compatibility between current an future generations of DSPs. When retrieved from memory an entire fetch packet is assigned an operating mode (base instruction set or migrant instruction set) according to the current execution mode. The fetch packets from the instruction memory are parsed into execute packets and sorted by execution unit (dispatched) in a datapath shared by both execution modes (base and migrant). The two execution modes have separate control logic. Instructions from the dispatch datapath are decoded by either base architecture decode logic or the migrant architecture decode logic, depending on the execution mode bound to the parent fetch packet. Code processed by the migrant and base decode pipelines produces machine words that are selected by a multiplexer. The multiplexer is controlled by the operating mode bound to the fetch packet that produced the machine word.

Abstract: A computing system as described in which individual instructions are executable in parallel by processing pipelines, and instructions to be executed in parallel by different pipelines are supplied to the pipelines simultaneously. The system includes storage for storing an arbitrary number of the instructions to be executed. The instructions to be executed are tagged with pipeline identification tags indicative of the pipeline to which they should be dispatched. The pipeline identification tags are supplied to a system which controls a crossbar switch, enabling the tags to be used to control the switch and supply the appropriate instructions simultaneously to the differing pipelines.

Abstract: Super functional units are used to execute not only single super-instructions that take more than one issue slot, but also a number of equivalent regular VLIW instructions. Accordingly, the same hardware can thus be used to execute either a superoperation or a combination of regular operations, potentially combined with other smaller superoperations. Using super functional units in this way promotes efficient use of computing resources by making computing resources that might otherwise be used unnecessarily by superoperations available for use by single-slot instructions or by smaller superoperations. In some embodiments, a compiler analyzes program and other data to identify superoperations that can be reduced to equivalent single-slot instructions. The compiler maps these operations to a single slot of a super functional unit, reducing the computing resources occupied by the operation.

Abstract: The ManArray processor is a scalable indirect VLIW array processor that defines two preferred architectures for indirect VLIW memories. One approach treats the VIM as one composite block of memory using one common address interface to access any VLIW stored in the VIM. The second approach treats the VIM as made up of multiple smaller VIMs each individually associated with the functional units and each individually addressable for loading and reading during XV execution. The VIM memories, contained in each processing element (PE), are accessible by the same type of LV and XV Short Instruction Words (SIWs) as in a single processor instantiation of the indirect VLIW architecture. In the ManArray architecture, the control processor, also called a sequence processor (SP), fetches the instructions from the SIW memory and dispatches them to itself and the PEs. By using the LV instruction, VLIWs can be loaded into VIMs in the SP and the PEs.

Abstract: The present invention provides a method (FIG. 6) and an apparatus that enable spare instruction slots within a code module to be utilized opportunistically for insertion of instructions associated with correctness check functions. During the generation of the initial instruction schedule, the compiler examines the initial instruction schedule and determines locations of spare instruction slots that can potentially be utilized for insertion of the correctness check code sequences. If a sufficient number of spare instruction slots exist to accommodate the correctness check code sequences, the sequences are inserted into the instruction schedule. If an insufficient number of spare instruction slots exist to accommodate a code sequence, the compiler adds additional instruction slots if a sufficient number of additional instruction slots can be added for insertion of the check sequences without exceeding a run-time performance cost tolerance level designated by a user.

Abstract: A highly parallel data processing system includes an array of n processing elements (PEs) and a controller sequence processor (SP) wherein at least one PE is combined with the controller SP to create a Dynamic Merged Processor (DP) which supports two modes of operation. In its first mode of operation, the DP acts as one of the PEs in the array and participates in the execution of single-instruction-multiple-data (SIMD) instructions. In the second mode of operation, the DP acts as the controlling element for the array of PEs and executes non-array instructions. To support these two modes of operation, the DP includes a plurality of execution units and two general-purpose register files. The execution units are “shared” in that they can execute instructions in either mode of operation. With very long instruction word (VLIW) capability, both modes of operation can be in effect on a cycle by cycle basis for every VLIW executed.

Abstract: A VLIW processor for executing a sequence of very long instruction words having a plurality of operations to be executed in parallel. The VLIW processor has a plurality of functional units for parallel execution of the operations specified by the VLIW, an instruction register for holding the VLIW, and a condition flag for indicating the results of a comparison operation. The VLIW includes a conditional head and a plurality of slots, each slot including an operational code and any related operands. The conditional head has a plurality of conditional indicators, each conditional indicator uniquely corresponding to one operation and specifying a condition in which the operation is to be executed if the indicated condition exists. A control circuit is connected to the instruction register and the functional units to deliver the operation from the instruction register to the corresponding functional unit for execution when the condition exists.

Abstract: A data processing device having a PC controlling part for executing an operation of branch which has a first register for holding a result of decoding in an instruction decode unit, a register for holding a description indicating an execution condition of the operation (a value of field for designating condition), and a register for holding the description indicating a time for executing the operation (an address value of PC), wherein the execution condition is started when a value held in the register is in agreement with a PC value in accordance with the description of the register; and if the condition is satisfied, the PC controlling part executes the operation based on a content held in the register, whereby it is possible to delay the time for judging the execution condition during this delay, to thereby increase a degree of freedom in scheduling instructions such that the branch instruction is positioned prior to the operation instruction for determining the execution condition in the program.

Abstract: A VLIW instruction format is introduced having a set of control bits which identify subinstruction sharing conditions. At compilation the VLIW instruction is analyzed to identify subinstruction sharing opportunities. Such opportunities are encoded in the control bits of the instruction. Before the instruction is moved into the instruction cache, the instruction is compressed into the new format to delete select redundant occurrences of a subinstruction. Specifically, where a subinstruction is to be shared by corresponding functional processing units of respective clusters, the subinstruction need only appear in the instruction once. The redundant appearance is deleted. The control bits are decoded at instruction parsing time to route a shared subinstruction to the associated functional processing units.

Abstract: A pipelined data processing unit includes an instruction sequencer and n functional units capable of executing n operations in parallel. The instruction sequencer includes a random access memory for storing very-long-instruction-words (VLIWs) used in operations involving the execution of two or more functional units in parallel. Each VLIW comprises a plurality of short-instruction-words (SIWs) where each SIW corresponds to a unique type of instruction associated with a unique functional unit. VLIWs are composed in the VLIW memory by loading and concatenating SIWs in each address, or entry. VLIWs are executed via the execute-VLIW (XV) instruction. The iVLIWs can be compressed at a VLIW memory address by use of a mask field contained within the XV1 instruction which specifies which functional units are enabled, or disabled, during the execution of the VLIW. The mask can be changed each time the XV1 instruction is executed, effectively modifying the VLIW every time it is executed.

Abstract: Embodiments of an apparatus, method, and system provide for no-operation instruction (“NOP”) folding such that information regarding the presence of a NOP instruction in the instruction stream is folded into a buffer entry for another instruction. Information regarding a target NOP instruction is thus maintained in a buffer entry associated with an instruction other than the target NOP instruction. For at least one embodiment, NOP information is folded into entries of a re-order buffer.

Abstract: A 32-bit instruction 50 is composed of a 4-bit format field 51, a 4-bit operation field 52, and two 12-bit operation fields 59 and 60. The 4-bit operation field 52 can only include (1) an operation code “cc” that indicates a branch operation which uses a stored value of the implicitly indicated constant register 36 as the branch address, or (2) a constant “const”. The content of the 4-bit operation field 52 is specified by a format code provided in the format field 51.

Abstract: In one disclosed embodiment an instruction loop having at least one instruction is identified. For example, each instruction can be a VLIW packet comprised of several individual instructions. The instructions of the instruction loop are fetched from a program memory. The instructions are then stored in a register queue. For example, the register queue can be implemented with a head pointer which is adjusted to select a register in which to write each instruction that is fetched. It is then determined whether the processor requires execution of the instruction loop, for example, by checking a program counter (PC) value corresponding to each instruction. When the processor requires execution of the instruction loop, the instructions are output from the register queue. For example, the register queue can be implemented with an access pointer which is adjusted to select a register from which to output each instruction that is required.

Abstract: There is disclosed a data processor having a clustered architecture that comprises a plurality of clusters and an interrupt and exception controller. Each of the clusters comprises an instruction execution pipeline having N processing stages. Each of the N processing stages is capable of performing at least one of a plurality of execution steps associated with instructions being executed by the clusters. The interrupt and exception controller operates to (i) detect an exception condition associated with one of the executing instructions, wherein this executing instruction issued at time t0, and (ii) generate an exception in response to the exception condition upon completed execution of earlier ones of the executing instructions, these earlier executing instructions issued at time preceding t0.

Abstract: An apparatus and method for creating instruction groups for explicitly parallel architectures is provided. The apparatus and method gather information about the underlying architecture for use in an instruction group creation phase. The information gathered includes the number of each type of execution unit available and the number of bundles that can be dispatched concurrently by the architecture. The instruction group creation of the present invention includes three phases: a first phase for performing initial grouping, a second phase for hosting instructions from further down in the program instruction order if the instruction is not able to be added during the initial grouping phase, and a third optional phase for counting the number of bundles formed to thereby inform a Just-In-Time compiler of the amount of space need to be allocated in a code buffer.

Abstract: A compressed instruction format for a VLIW processor allows greater efficiency in use of cache and memory. Instructions are byte aligned and variable length. Branch targets are uncompressed. Format bits specify how many issue slots are used in a following instruction. NOPS are not stored in memory. Individual operations are compressed according to features such as whether they are resultless, guarded, short, zeroary, unary, or binary. Instructions are stored in compressed form in memory and in cache. Instructions are decompressed on the fly after being read out from cache.

Abstract: Method and apparatus for reducing or eliminating retirement logic in an out-of-order processor are disclosed. Instructions are processed using a processing unit capable of out-of-order processing and having architectural registers having an architectural state. Groups of instructions are prepared for processing by processing unit, wherein within each group to be processed the instructions producing the final state of an architectural register are changed so that they write to an output copy of the architectural state, the instructions reading architectural registers are changed to read from an input copy of the architectural state, and the instructions within each group producing results to architectural registers that would be overwritten by another instruction in the group are changed to write their results to temporary registers.

Abstract: An area of on-chip memory is allocated to store one or more tables of commonly-used opcodes. The normal opcode in the instruction is replaced with a shorter code identifying an index into the table. As a result, the instruction is compressed. For a VLIW architecture, in which an instruction includes multiple subinstructions (multiple opcodes), the instruction loading bandwidth is substantially reduced. Preferably, an opcode table is dynamically loaded. Different tasks are programmed with a respective table of opcodes to be stored in the opcode table. The respective table is loaded when task switching.

Abstract: A ManArray processor pipeline design addresses an indirect VLIW memory access problem without increasing branch latency by providing a dynamically reconfigurable instruction pipeline for SIWs requiring a VLIW to be fetched. By introducing an additional cycle in the pipeline only when a VLIW fetch is required, the present invention solves the VLIW memory access problem. The pipeline stays in an expanded state, in general, until a branch type or load VLIW memory type operation is detected returning the pipeline to a compressed pipeline operation. By compressing the pipeline when a branch type operation is detected, the need for an additional cycle for the branch operation is avoided. Consequently, the shorter compressed pipeline provides more efficient performance for branch intensive control code as compared to a fixed pipeline with an expanded number of pipeline stages.

Abstract: A processor system is formed from a plurality of processor elements (6). A plurality of registers (8) are provided for use with the processing elements and an instruction decoder (4) is configured to decode a first portion of at least one Very Long Instruction Word (VLIW) as a multiple register load instruction. A second larger portion of the VLIW is decoded as data to enable loading of a plurality of individual ones of a plurality of registers.

Abstract: A sideband VLIW processing technique is provided. The sideband VLIW processing technique utilizes processor executable code and sideband information that identifies grouping and scheduling of the processor instructions to be executed by a sideband VLIW processor. The sideband information is ignored by processors without sideband VLIW processing capability, thus providing backward compatibility for the processor executable code. The sideband VLIW processor does not have the run-time scheduling circuitry of superscalar processors and instead has circuitry to read and interpret sideband information. Multiple sets of sideband information can be provided for a single corresponding executable program, one set for each different sideband VLIW processor implementation.

Abstract: A method and system for decompressing a program word that is subsequently delivered to a processor for execution. Program word fields are compressed based on regularities between operations and operands. The resulting microcode, which describes the trajectory of the program, is stored in program memory and fed to dynamic program decompression devices, or dyprodes, which are assembled using registers and multiplexers and are driven by a clock, reset signals, and the microcode. At each cycle, the dyprodes produce an uncompressed field of the program word. The reassembled program word is then passed on to a processor for execution. The use of a dyprode system reduces program memory required to store code and reduces the size of the bus connecting a microprocessor to off-chip program memory.

Abstract: A data processor which includes a first processor for executing a first instruction set and a second processor for executing a second instruction set different from the first instruction set. When the first processor executes a predetermined instruction of the first instruction set the second processor executes an instruction of the second instructions set. The first processor may be a reduced instruction set computer (RISC) type processor, the second processor may be a very long instruction word (VLIW) type processor, the first instruction set may be a RISC instruction set and the second instruction set may be a VLIW instruction set. The predetermined instruction of the RISC instruction set executed by the first processor may be a branch instruction causing a branch to a specific address space at which VLIW instructions are stored. Thereafter, the VLIW instructions at the specific address space are executed by the VLIW type processor.

Abstract: In a processor executing plural instructions simultaneously, writin-destination-register numbers of the plural instructions to be executed simultaneously are compared, and kinds of operations to be executed by the plural instructions are changed in response to a comparison result. When the writing-destination-register numbers of the plural instructions are identical, a constant operation is applied to plural operation results obtained from the plural instructions to obtain an operation result and the operation result is written into the writing-destination-register instructed by the plural instructions. Results outputted from plural processing units are put together into one result and the result is stored in one register. Thus, register use efficiency and process efficiency are improved.

Abstract: A process for packing an instruction word including providing a word value representing an instruction word into which an operation is to be fit be equal to some initial value having a plurality of portions representing constraints, operating on the initial value of the value word with operation class values having a plurality of portions representing constraints of a new operation as the new operation is attempted to be fit into the instruction to affect the processor word value in a manner to indicate when the limit of any constraint for the instruction is reached, and determining a violation of any constraint to determine that the new operation does not fit the format.

Abstract: Mapping circuitry (40) comprises a first candidate output value producing unit (42) which produces a first candidate output value (C1) that differs by a first offset value (x) from a received input value (r). During operation of the first candidate output value producing unit (42) a second candidate output value producing unit (44) produces a second candidate output value (C2) that differs by a second offset value (y) from the received input value (r). One of the first and second candidate output values is within a preselected range of allowable output values and the other is outside that range. An in-range value determining unit (46) determines which one of the first and second candidate output values is within the range, and an output value selection unit (48) selects this value as the output value (p) corresponding to the received input value (r).

Abstract: Effective remote register file access time can be reduced in a clustered VLIW processor using partitioned register files and some additional hardware for pre-fetching remote registers. An instruction pre-fetcher and an instruction pre-decoder is used for pre-fetching and partially decoding instructions in order to pre-fetch the remote registers required for executing VLIWs at run-time, thus substantially reducing the number of inter-cluster copy instructions. The instructions (VLIWs) are scheduled taking into account the various hardware constraints such as limited inter-cluster communication bandwidth, inter-cluster communication delay, etc.

Abstract: A processor system includes a programmable very long instruction word (VLIW) processor which is closely coupled to a data memory. There is also provided a memory for storing instruction words for the VLIW processors. A memory access unit is coupled to a data memory and at least one input side is dedicated processor is coupled between a data input and the memory access unit. Furthermore, at least one output side dedicated processor is coupled between the memory access unit and the data output. The input and output side data processors perform operations common to a plurality of data processors on input and output data and the VLIW processor performs operations on data particular to a process being performed by the processor system. The VLIW processor is loaded with different sets of instruction words in dependence on the process being performed by the processor system.

Abstract: An information control pipeline (13) parallels the processor's instruction pipeline (3), contains digital control information in respect of the instruction placed in the instruction pipeline and accompanies that instruction until all component operations prescribed within the instruction have been executed. When at the end of the pipeline, the instruction is presented for execution to a respective functional execution unit (7) of the processor, the respective functional execution unit accesses and uses the control information as a condition to instruction execution. Depending upon the processor, the control information may contain one or more bits, referred to as enable bits, as may be set enabled, indicating that an associated operation in the instruction is to be executed, or by software set disabled, indicating that the associated operation is masked, such as by an exception handler (9) when returning from a resolved exception.

Abstract: A second decoder (114) of an instruction decode unit (119) decodes an operation code for a multiply-add operation, and a second operation unit (117) receives two data stored in a register file (115) to perform the multiply-add operation. In parallel with the operations of the second decoder (114) and the second operation unit (117), a first decoder (113) of the instruction decode unit (119) decodes an operation code for 2 data load, and an operand access unit (104) causes two data (e.g., n bits each) stored in an internal data memory (105) to be transferred in parallel in the form of combined 2n-bit data to a first operation unit (116). Then, two predetermined registers of the register file (115) store the respective n-bit data from the first operation unit (116).