Byte-word Rearranging, Bit-field Insertion Or Extraction, String Length Detecting, Or Sequence Detecting Patents (Class 712/300)
  • Patent number: 10832241
    Abstract: An example operation may include one or more of identifying a transaction from a blockchain node to be committed to a blockchain, determining available channels for assignment, assigning a channel to the blockchain node, and transmitting the transaction to the blockchain on the assigned channel.
    Type: Grant
    Filed: October 11, 2017
    Date of Patent: November 10, 2020
    Assignee: International Business Machines Corporation
    Inventors: Muhammad Tayyab Asif, Pralhad D. Deshpande, Raghav Sood, Yuan Yuan
  • Patent number: 10678541
    Abstract: An apparatus includes a decode unit to decode a permute instruction and a vector conflict instruction. A vector execution unit is coupled with the decode unit and includes a fully-connected interconnect. The fully-connected interconnect has at least four inputs to receive at least four corresponding data elements of at least one source vector. The fully-connected interconnect has at least four outputs. Each of the at least four inputs is coupled with each of the at least four outputs. The execution unit also includes a permute instruction execution logic coupled with the at least four outputs and operable to store a first vector result in response to the permute instruction. The execution unit also includes a vector conflict instruction execution logic coupled with the at least four outputs and operable to store a second vector result in a destination storage location in response to the vector conflict instruction.
    Type: Grant
    Filed: December 29, 2011
    Date of Patent: June 9, 2020
    Assignee: Intel Corporation
    Inventors: Andrew Thomas Forsyth, Dennis R. Bradford
  • Patent number: 10540321
    Abstract: A graphical user interface allows a customer to specify delimiters and/or patterns that occur in event data and indicate the presence of a particular field. The graphical user interface applies a customer's delimiter specifications directly to event data and displays the resulting event data in real time. Delimiter specifications may be saved as configuration settings and systems in a distributed setting may use the delimiter specifications to extract field values as the systems process raw data into event data. Extracted field values are used to accelerate search queries that a system receives.
    Type: Grant
    Filed: January 31, 2018
    Date of Patent: January 21, 2020
    Assignee: SPLUNK INC.
    Inventor: Jesse Miller
  • Patent number: 10418125
    Abstract: System and method of write deskew training for ×4 mode memory control interface configurations. Write leveling logic in the memory controller is adjusted to obtain a write leveling setting for delaying both first and second strobe signals associated with a byte. The adjustment is based on feedback of first set of bits of a byte and irrespective of the feedback of the second set of bits of the byte. The write leveling logic is then anchored at the write leveling setting, and a deskew delay line for the second strobe signal is adjusted to obtain a first deskew setting based on the feedback of the second set of bits. Thus, in write operations, the write leveling setting can be common within the byte even the two strobe signals are transmitted to or received from two different memory storage devices.
    Type: Grant
    Filed: July 19, 2018
    Date of Patent: September 17, 2019
    Assignee: Marvell Semiconductor
    Inventor: David Da Wei Lin
  • Patent number: 10405000
    Abstract: Methods and apparatus are provided for performing one-dimensional (1D) transform and coefficient scanning. An encoder may apply 1D transform in either a horizontal or a vertical direction. The encoder may then determine a coefficient scan order based on the 1D transform direction. The scan order may be determined to be in a direction orthogonal to the 1D transform direction. The encoder may further flip the coefficients prior to scanning. The flipping may also be in a direction orthogonal to the 1D transform direction. A decoder may receive indications from the encoder with respect to the 1D transform, coefficient scanning, and/or coefficient flipping. The decoder may perform functions inverse to those performed by the encoder based on the indications.
    Type: Grant
    Filed: November 23, 2015
    Date of Patent: September 3, 2019
    Assignee: VID SCALE, Inc.
    Inventors: Jiun-Yu Kao, Maryam Azimi Hashemi, Xiaoyu Xiu, Yuwen He, Yan Ye
  • Patent number: 10340945
    Abstract: Methods and systems for encoding of integers are discussed. For example, various methods and systems may utilize Huffman coding, Tunstall coding, Arithmetic Coding, LZ77 coding, LZ78 coding, LW coding, or Shannon Fano Elias coding to encode the integers.
    Type: Grant
    Filed: July 24, 2018
    Date of Patent: July 2, 2019
    Assignee: iDensify LLC
    Inventors: Dan E. Tamir, Peter Jeremy Wilson
  • Patent number: 10133752
    Abstract: A method and apparatus for a dynamic glyph based search includes an image server. The image server analyzes images to determine the content of an image. The image and data related to the determined content of the image are stored in an image database. A user can access the image server and search images using search glyphs. In response to selection of a generic-search glyph, the image server finds related images in the image database and the images are displayed to the user. In addition, refine-search glyphs are displayed to a user based on the selected generic-search glyph. One or more refine-search glyphs can be selected by a user to further narrow a search to specific people, locations, objects, and other image content.
    Type: Grant
    Filed: November 25, 2014
    Date of Patent: November 20, 2018
    Assignee: AT&T INTELLECTUAL PROPERTY I, L.P.
    Inventors: Lee Begeja, Robert J. Andres, David C. Gibbon, Steven Neil Tischer
  • Patent number: 10133570
    Abstract: A processor includes packed data registers, and a decode unit to decode a data element selection and consolidation instruction. The instruction is to have a first source packed data operand that is to have a plurality of data elements, and a second source operand that is to have a plurality of mask elements. Each mask element corresponds to a different data element in the same relative position. An execution unit is coupled with the decode unit. The execution unit, in response to the instruction, is to store a result packed data operand in a destination storage location that is to be indicated by the instruction. The result packed data operand is to include all data elements of the first source packed data operand, which correspond to unmasked mask elements of the second source operand, consolidated together in a portion of the result packed data operand.
    Type: Grant
    Filed: September 19, 2014
    Date of Patent: November 20, 2018
    Assignee: INTEL CORPORATION
    Inventor: Mazhar I Memon
  • Patent number: 10089341
    Abstract: The storage method comprises: acquiring a plurality of monitoring dimensionalities associated with each monitoring service and at least one pair of monitoring indicator data including an indicator name and an indicator value; converting the plurality of monitoring dimensionalities into a plurality of row keyword mapping values having the same length, respectively; combining monitoring time with the plurality of row keyword mapping values to form a row keyword, and setting the monitoring time in a fixed time position in the row keyword; and using the row keyword as an index to store a monitoring indicator in a distributed database. A dynamic adjustment of monitoring dimensionalities of data storage for the monitoring system is achieved in accordance with different monitoring services, thereby reducing maintenance costs and improving scalability.
    Type: Grant
    Filed: May 28, 2014
    Date of Patent: October 2, 2018
    Assignee: BEIJING JINGDONG SHANGKE INFORMATION TECHNOLOGY CO., LTD.
    Inventor: Xing Wen
  • Patent number: 9996347
    Abstract: Methods and apparatuses relating to a vector instruction with a register operand with an elemental offset are described. In one embodiment, a hardware processor includes a decode unit to decode a vector instruction with a register operand with an elemental offset to access a first number of elements in a register specified by the register operand, wherein the first number is a total number of elements in the register minus the elemental offset, access a second number of elements in a next logical register, wherein the second number is the elemental offset, and combine the first number of elements and the second number of elements as a data vector, and an execution unit to execute the vector instruction on the data vector.
    Type: Grant
    Filed: December 24, 2014
    Date of Patent: June 12, 2018
    Assignee: INTEL CORPORATION
    Inventors: Victor Lee, Ugonna Echeruo, George Chrysos, Naveen Mellempudi
  • Patent number: 9977676
    Abstract: Vector processing engines (VPEs) employing reordering circuitry in data flow paths between execution units and vector data memory to provide in-flight reordering of output vector data stored to vector data memory are disclosed. Related vector processor systems and methods are also disclosed. Reordering circuitry is provided in data flow paths between execution units and vector data memory in the VPE. The reordering circuitry is configured to reorder output vector data sample sets from execution units as a result of performing vector processing operations in-flight while the output vector data sample sets are being provided over the data flow paths from the execution units to the vector data memory to be stored. In this manner, the output vector data sample sets are stored in the reordered format in the vector data memory without requiring additional post-processing steps, which may delay subsequent vector processing operations to be performed in the execution units.
    Type: Grant
    Filed: November 15, 2013
    Date of Patent: May 22, 2018
    Assignee: QUALCOMM Incorporated
    Inventors: Raheel Khan, Fahad Ali Mujahid
  • Patent number: 9946721
    Abstract: Systems and methods for generating files in a virtual file system in the memory of a network system are discussed. The network system receives a filename including at least one file metadata. The file metadata includes a file size of the file, a random seed for generating content of the file, and modification information of the file. File content for the file may be generated based on the filename. The file content may then be provided to the network system.
    Type: Grant
    Filed: September 4, 2013
    Date of Patent: April 17, 2018
    Assignee: Google LLC
    Inventors: Dor Gross, Cosmos Nicolaou
  • Patent number: 9929745
    Abstract: An apparatus and method are described for performing vector compression. For example, one embodiment of a processor comprises: vector compression logic to compress a source vector comprising a plurality of valid data elements and invalid data elements to generate a destination vector in which valid data elements are stored contiguously on one side of the destination vector, the vector compression logic to utilize a bit mask associated with the source vector and comprising a plurality of bits, each bit corresponding to one of the plurality of data elements of the source vector and indicating whether the data element comprises a valid data element or an invalid data element, the vector compression logic to utilize indices of the bit mask and associated bit values of the bit mask to generate a control vector; and shuffle logic to shuffle/permute the data elements of the source vector to the destination vector in accordance with the control vector.
    Type: Grant
    Filed: September 26, 2014
    Date of Patent: March 27, 2018
    Assignee: Intel Corporation
    Inventors: Simon Rubanovich, David M. Russinoff, Amit Gradstein, John W. O'Leary, Zeev Sperber
  • Patent number: 9870547
    Abstract: Systems of demand and capacity management with machine-time accuracy are provided. The system includes an allocation planning module, an order management module, a capacity model, and a capacity management module. The allocation planning module receives a demand plan for a product. The capacity management module transforms the demand plan into a machine-time-based plan according to the capacity model, and reserves capacity according to the machine-time-based plan for the demand plan. The capacity management module further transforms a purchase order received by the order management module before a cutoff date for the product into a machine-time-based order, accepts the machine-time-based order and decreases the reservation capacity depending on the machine-time-based plan.
    Type: Grant
    Filed: January 19, 2009
    Date of Patent: January 16, 2018
    Inventors: Chung-Wen Wang, Chii-Ming M. Wu, Edwin Liou, Chiang-Sheng Chin
  • Patent number: 9785434
    Abstract: An apparatus, system and method of determining an extremum are disclosed. A reference location identifier and a reference extremum are coupled. An input extremum of an input data set is determined and a corresponding location identifier of the input extremum is also determined. The input extremum is compared with the reference extremum to determine an output extremum and output location identifier, based on the comparison.
    Type: Grant
    Filed: September 23, 2011
    Date of Patent: October 10, 2017
    Assignee: QUALCOMM Incorporated
    Inventors: Erich J. Plondke, Lucian Codrescu, Mao Zeng, Swaminathan Balasubramanian, David J. Hoyle
  • Patent number: 9787524
    Abstract: Methods and devices to allow multiple operating system images to simultaneously access a Fiber Channel fabric through a common host bus adapter port are described. For each requesting operating system image, a fabric switch maintains a unique port identifier value and a unique fabric channel address so that each operating system image may be uniquely identified across the fabric.
    Type: Grant
    Filed: July 23, 2002
    Date of Patent: October 10, 2017
    Assignee: Brocade Communications Systems, Inc.
    Inventors: Alberto Lutgardo, Robert N. Snively
  • Patent number: 9632980
    Abstract: An apparatus is described having instruction execution logic circuitry. The instruction execution logic circuitry has input vector element routing circuitry to perform the following for each of three different instructions: for each of a plurality of output vector element locations, route into an output vector element location an input vector element from one of a plurality of input vector element locations that are available to source the output vector element. The output vector element and each of the input vector element locations are one of three available bit widths for the three different instructions. The apparatus further includes masking layer circuitry coupled to the input vector element routing circuitry to mask a data structure created by the input vector routing element circuitry. The masking layer circuitry is designed to mask at three different levels of granularity that correspond to the three available bit widths.
    Type: Grant
    Filed: December 23, 2011
    Date of Patent: April 25, 2017
    Assignee: Intel Corporation
    Inventors: Elmoustapha Ould-Ahmed-Vall, Robert Valentine, Jesus Corbal, Suleyman Sair
  • Patent number: 9535954
    Abstract: Provided is a join processing device that performs a similarity join process to plural tuples using an edit distance threshold value ? (positive integer). The join processing device includes a join processing unit that excludes, from a target of edit distance calculation, a pair of tuples that do not have any common character in an end portion ranging from a head character or a tail character to a (?+1)th character in a join key string in each of the tuples.
    Type: Grant
    Filed: November 7, 2011
    Date of Patent: January 3, 2017
    Assignee: NEC CORPORATION
    Inventor: Kazuyo Narita
  • Patent number: 9477472
    Abstract: Method, apparatus, and program means for shuffling data. The method of one embodiment comprises receiving a first operand having a set of L data elements and a second operand having a set of L control elements. For each control element, data from a first operand data element designated by the individual control element is shuffled to an associated resultant data element position if its flush to zero field is not set and a zero is placed into the associated resultant data element position if its flush to zero field is not set.
    Type: Grant
    Filed: July 2, 2012
    Date of Patent: October 25, 2016
    Assignee: Intel Corporation
    Inventors: William W. Macy, Jr., Eric L. Debes, Patrice L. Roussel, Huy V. Nguyen
  • Patent number: 9400826
    Abstract: A method for content extraction and modeling by a computer system for incorporating the content into a domain model including the steps of extracting by an acquisition module content stored on a computer readable medium of at least one data source, determining whether the content is structured or unstructured; wherein structured content has a first content model associated therewith defining at least a format of the structured content and unstructured content has no model associated therewith. Upon a condition in which the content is structured, incorporating the structured content into the domain model; and, upon a condition in which the content is unstructured, determining by the computer system a second content model to transform the unstructured content into newly structured content and incorporating the newly structured content into the domain model.
    Type: Grant
    Filed: June 25, 2013
    Date of Patent: July 26, 2016
    Assignee: Outside Intelligence, Inc.
    Inventors: Daniel Ryan Adamson, Victor Fernandovich Comas Lijachev
  • Patent number: 9329783
    Abstract: Embodiments of the present invention provide a data processing system and a data processing method. An MMIO address of a data request is obtained, where data stored in a PCIe storage device can be directly obtained from the MMIO address, and according to the MMIO address, a network adapter can directly read the data from the PCIe storage device of the data processing system, and transmit the data to a second data processing system, or directly write the data received from the second data processing system into the PCIe storage device. Therefore, the processing system can implement transmitting data directly from the PCIe storage device to the network adapter without using memory. During data transmission between the two data processing systems, a usage ratio of a resource, such as memory and a CPU, is reduced, and efficiency of data transmission is improved.
    Type: Grant
    Filed: May 5, 2015
    Date of Patent: May 3, 2016
    Assignee: Huawei Technologies Co., Ltd.
    Inventors: Jian He, Guangyu Shi, Xiaoke Ni, Norbert Egi, Xiancai Li, Yu Liu, Huawei Liu
  • Patent number: 9323524
    Abstract: Techniques for packing and unpacking data from a source register using a particular shift instruction are provided. The shift instructions takes, as input, a source register that contains a plurality of elements and a shift count register that contains a plurality of shift counts. Each shift count indicates how much to shift bits from the source registers. Where “source” bits are shifted (or copied) to in an output register depends on the position of the shift count in the shift count register. The shift counts may correspond to one or more bytes from the source register. The shift instruction may initiate a left shift operation or a right shift operation.
    Type: Grant
    Filed: September 16, 2013
    Date of Patent: April 26, 2016
    Assignee: Oracle International Corporation
    Inventor: Albert Martin
  • Patent number: 9271229
    Abstract: Methods, systems, and media for partial downloading in wireless distributed networks are provided. In some embodiments, methods for selecting numbers of symbols to be transmitted on a plurality of channels are provided, the methods comprising: for each of the plurality of channels, calculating using a hardware processor an increase in power that will be used by that channel if it transmits a symbol; selecting one of the plurality of channels with the smallest increase in power using the hardware processor; and allocating the symbol to the one of the plurality of channels using the hardware processor.
    Type: Grant
    Filed: July 22, 2013
    Date of Patent: February 23, 2016
    Assignee: The Trustees of Columbia University in the City of New York
    Inventors: Chen Gong, Xiaodong Wang
  • Patent number: 9244840
    Abstract: A method and circuit arrangement selectively swizzle data in one or more levels of cache memory coupled to a processing unit based upon one or more swizzle-related page attributes stored in a memory address translation data structure such as an Effective To Real Translation (ERAT) or Translation Lookaside Buffer (TLB). A memory address translation data structure may be accessed, for example, in connection with a memory access request for data in a memory page, such that attributes associated with the memory page in the data structure may be used to control whether data is swizzled, and if so, how the data is to be formatted in association with handling the memory access request.
    Type: Grant
    Filed: December 12, 2012
    Date of Patent: January 26, 2016
    Assignee: International Business Machines Corporation
    Inventors: Jamie R. Kuesel, Mark G. Kupferschmidt, Paul E. Schardt, Robert A. Shearer
  • Patent number: 9247079
    Abstract: An information processing apparatus includes first electronic circuit and one or a plurality of second electronic circuits. The first electronic circuit has a first buffer for storing information, and is configured to execute predetermined first information processing by reading out information from a memory connected via a first transmission path, and write the information processed by the first information processing into the memory. The one or plurality of second electronic circuits have a second buffer for storing information, and are connected to the first electronic circuit via a second transmission path different from the first transmission path, and the one or plurality of second electronic circuits are configured to execute second information processing different from the first information processing. The first electronic circuit is configured to execute the first information processing, using the second buffer of the second electronic circuit that is in an unused state and the first buffer.
    Type: Grant
    Filed: January 21, 2014
    Date of Patent: January 26, 2016
    Assignee: KYOCERA Document Solutions Inc.
    Inventor: Yuki Yamamoto
  • Patent number: 9239791
    Abstract: A method and circuit arrangement selectively swizzle data in one or more levels of cache memory coupled to a processing unit based upon one or more swizzle-related page attributes stored in a memory address translation data structure such as an Effective To Real Translation (ERAT) or Translation Lookaside Buffer (TLB). A memory address translation data structure may be accessed, for example, in connection with a memory access request for data in a memory page, such that attributes associated with the memory page in the data structure may be used to control whether data is swizzled, and if so, how the data is to be formatted in association with handling the memory access request.
    Type: Grant
    Filed: March 13, 2013
    Date of Patent: January 19, 2016
    Assignee: International Business Machines Corporation
    Inventors: Jamie R. Kuesel, Mark G. Kupferschmidt, Paul E. Schardt, Robert A. Shearer
  • Patent number: 9218184
    Abstract: Method, apparatus, and program means for performing bitstream buffer manipulation with a SIMD merge instruction. The method of one embodiment comprises determining whether any unprocessed data bits for a partial variable length symbol exist in a first data block is made. A shift merge operation is performed to merge the unprocessed data bits from the first data block with a second data block. A merged data block is formed. A merged variable length symbol comprised of the unprocessed data bits and a plurality of data bits from the second data block is extracted from the merged data block.
    Type: Grant
    Filed: March 15, 2013
    Date of Patent: December 22, 2015
    Assignee: Intel Corporation
    Inventors: Julien Sebot, William W. Macy, Jr., Eric L. Debes, Huy V. Nguyen
  • Patent number: 9213548
    Abstract: An information processing apparatus generates first and second trees representing a dependency relationship among instructions from first code. The information processing apparatus then adjusts the height of the shorter one of the first and second trees by inserting pseudo instructions that do not cause any difference in data before and after operation in the shorter tree, and also shuffles the order of instructions existing at the same depth from the root, according to operation types in at least one of the first and second trees. The information processing apparatus compares the first and second trees subjected to the height adjustment and the order shuffling with each other to determine combinations of an instruction of the first tree and an instruction of the second tree.
    Type: Grant
    Filed: March 26, 2013
    Date of Patent: December 15, 2015
    Assignee: FUJITSU LIMITED
    Inventors: Shuichi Chiba, Takashi Arakawa
  • Patent number: 9176847
    Abstract: A method of and system for managing diagnostic information is disclosed. The method and system may include creating a data space in volatile memory. The data space may be configured to collect a selected diagnostic information. The selected diagnostic information may include a first diagnostic information from a first source and a second diagnostic information from a second source. The method and system may include collecting in the data space the selected diagnostic information. The method and system may include releasing from the data space at least a portion of the selected diagnostic information in response to a triggering event.
    Type: Grant
    Filed: May 22, 2013
    Date of Patent: November 3, 2015
    Assignee: International Business Machines Corporation
    Inventors: Joseph V. Malinowski, Miguel A. Perez, David C. Reed, Max D. Smith
  • Patent number: 9135323
    Abstract: An example of a system comprises a fingerprint calculator configured to receive data structure information and create a fingerprint as a function of the data structure information, a code generator configured to generate modified machine code, the modified machine code including the fingerprint embedded therein, a fingerprint identifier configured to identify the fingerprint in data received from a data dump, a data structure lookup table including the fingerprint and the data structure information associated with the fingerprint stored thereon, and a data interpreter configured to interpret, using data from the data dump and the data structure information, the data structure of at least a portion of the data from the data dump.
    Type: Grant
    Filed: September 13, 2012
    Date of Patent: September 15, 2015
    Assignee: Raytheon Company
    Inventors: Jon Wada, Mark A. Miller
  • Patent number: 9104820
    Abstract: The present invention is to provide a semiconductor device that can correctly switch endians on the outside even if the endian of a parallel interface is not recognized on the outside. The semiconductor device includes a switching circuit and a first register. The switching circuit switches between whether a parallel interface with the outside is to be used as a big endian or a little endian. A first register holds control data of the switching circuit. The switching circuit regards the parallel interface as the little endian when first predetermined control information, that is unchanged in the values of specific bit positions even if its high-order and low-order bit positions are transposed, is supplied to the first register, and regards the parallel interface as the big endian when second predetermined control information, that is unchanged in the values of specific bit positions even if its high-order and low-order bit positions are transposed, is supplied to the first register.
    Type: Grant
    Filed: February 20, 2015
    Date of Patent: August 11, 2015
    Assignee: Renesas Electronics Corporation
    Inventors: Goro Sakamaki, Yuri Azuma
  • Patent number: 9052844
    Abstract: A computer-implemented method of and a device, such as a base station for a headset, for arranging text items in a predefined order, comprising storing, in the memory of a peripheral device, a collection of multiple text items arranged in multiple sets of text items and in multiple groups of text items; storing a respective code item with a respective group of text items; and storing a sort key that has values that designate a predefined order of the text items in each set. The sort key is appended to the text items and comprises at least one character with a value within the Private Use range of the Unicode format.
    Type: Grant
    Filed: June 14, 2012
    Date of Patent: June 9, 2015
    Assignee: GN Netcom A/S
    Inventor: Christian Paulsen
  • Patent number: 9047069
    Abstract: A computer implemented method selects K extreme elements of a list of N elements by partitioning each of the N elements into a plurality of sections. For each section the method selects a threshold selection determining at least K extreme entries from the list. This iteratively compares a corresponding section to a section threshold, counts a number of sections which are more extreme than the section threshold, increasing (or decreasing) the section threshold if the count is greater than K and decreasing (or increasing) the section threshold if the count is less than K. The method forms a combined threshold by concatenation of said section thresholds in order, compares each of the N elements to the combined threshold, and selects at least K elements from the set of N elements more extreme than the combined threshold.
    Type: Grant
    Filed: April 12, 2012
    Date of Patent: June 2, 2015
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Constantin Bajenaru, Michael Livshitz, Mingjian Yan, Jing Jiang
  • Patent number: 9015453
    Abstract: An apparatus includes an instruction decoder, first and second source registers and a circuit coupled to the decoder to receive packed data from the source registers and to unpack the packed data responsive to an unpack instruction received by the decoder. A first packed data element and a third packed data element are received from the first source register. A second packed data element and a fourth packed data element are received from the second source register. The circuit copies the packed data elements into a destination register resulting with the second packed data element adjacent to the first packed data element, the third packed data element adjacent to the second packed data element, and the fourth packed data element adjacent to the third packed data element.
    Type: Grant
    Filed: December 29, 2012
    Date of Patent: April 21, 2015
    Assignee: Intel Corporation
    Inventors: Alexander D. Peleg, Yaakov Yaari, Millind Mittal, Larry M. Mennemeier, Benny Eitan
  • Patent number: 8966227
    Abstract: The present invention is to provide a semiconductor device that can correctly switch endians on the outside even if the endian of a parallel interface is not recognized on the outside. The semiconductor device includes a switching circuit and a first register. The switching circuit switches between whether a parallel interface with the outside is to be used as a big endian or a little endian. A first register holds control data of the switching circuit. The switching circuit regards the parallel interface as the little endian when first predetermined control information, that is unchanged in the values of specific bit positions even if its high-order and low-order bit positions are transposed, is supplied to the first register, and regards the parallel interface as the big endian when second predetermined control information, that is unchanged in the values of specific bit positions even if its high-order and low-order bit positions are transposed, is supplied to the first register.
    Type: Grant
    Filed: March 5, 2014
    Date of Patent: February 24, 2015
    Assignee: Renesas Electronics Corporation
    Inventors: Goro Sakamaki, Yuri Azuma
  • Patent number: 8909901
    Abstract: In one embodiment, the present invention includes logic to receive a permute instruction, first and second source operands, and control values, and to perform a permute operation based on an operation between at least two of the control values so that selected portions of the first and second source operands or a predetermined value can be stored into elements of a destination. Multiple permute instructions may be combined to perform efficient table lookups. Other embodiments are described and claimed.
    Type: Grant
    Filed: December 28, 2007
    Date of Patent: December 9, 2014
    Assignee: Intel Corporation
    Inventors: Cristina Anderson, Mark Buxton, Doron Orenstien, Bob Valentine
  • Patent number: 8868885
    Abstract: A device system and method for processing program instructions, for example, to execute intra vector operations. A fetch unit may receive a program instruction defining different operations on data elements stored at the same vector memory address. A processor may include different types of execution units each executing a different one of a predetermined plurality of elemental instructions. Each program instruction may be a combination of one or more of the elemental instructions. The processor may receive a vector of data elements stored non-consecutively at the same vector memory address to be processed by a same one of the elemental instructions and a vector of configuration values independently associated with executing the same elemental instruction on the non-consecutive data elements. At least two configuration values may be different to implement different operations by executing the same elemental instruction using the different configuration values on the vector of non-consecutive data elements.
    Type: Grant
    Filed: November 18, 2010
    Date of Patent: October 21, 2014
    Assignee: Ceva D.S.P. Ltd.
    Inventors: Yaakov Dekter, Michael Boukaya, Shai Shpigelblat, Moshe Steinberg
  • Patent number: 8838946
    Abstract: An apparatus includes an instruction decoder, first and second source registers and a circuit coupled to the decoder to receive packed data from the source registers and to unpack the packed data responsive to an unpack instruction received by the decoder. A first packed data element and a third packed data element are received from the first source register. A second packed data element and a fourth packed data element are received from the second source register. The circuit copies the packed data elements into a destination register resulting with the second packed data element adjacent to the first packed data element, the third packed data element adjacent to the second packed data element, and the fourth packed data element adjacent to the third packed data element.
    Type: Grant
    Filed: December 29, 2012
    Date of Patent: September 16, 2014
    Assignee: Intel Corporation
    Inventors: Alexander Peleg, Yaakov Yaari, Millind Mittal, Larry M. Mennemeier, Benny Eitan
  • Patent number: 8793475
    Abstract: An apparatus includes an instruction decoder, first and second source registers and a circuit coupled to the decoder to receive packed data from the source registers and to unpack the packed data responsive to an unpack instruction received by the decoder. A first packed data element and a third packed data element are received from the first source register. A second packed data element and a fourth packed data element are received from the second source register. The circuit copies the packed data elements into a destination register resulting with the second packed data element adjacent to the first packed data element, the third packed data element adjacent to the second packed data element, and the fourth packed data element adjacent to the third packed data element.
    Type: Grant
    Filed: December 29, 2012
    Date of Patent: July 29, 2014
    Assignee: Intel Corporation
    Inventors: Alexander Peleg, Yaakov Yaari, Millind Mittal, Larry M. Mennemeier, Benny Eitan
  • Patent number: 8793469
    Abstract: A computer, circuit, and computer-readable medium are disclosed. In one embodiment, the processor includes an instruction decoder unit that can decode a macro instruction into at least one micro-operation with a set of data fields. The resulting micro-operation has at least one data field that is in a compressed form. The instruction decoder unit has storage that can store the micro-operation with the compressed-form data field. The instruction decoder unit also has extraction logic that is capable of extracting the compressed-form data field into an uncompressed-form data field. After extraction, the instruction decoder unit also can send the micro-operation with the extracted uncompressed-form data field to an execution unit. The computer also includes an execution unit capable of executing the sent micro-operation.
    Type: Grant
    Filed: December 17, 2010
    Date of Patent: July 29, 2014
    Assignee: Intel Corporation
    Inventors: Kameswar Subramaniam, Anthony Wojciechowski, Jonathan D. Combs
  • Patent number: 8782320
    Abstract: In one embodiment, a multistage interconnection network (MIN) has two or more configurable stages, each stage having a plurality of switches. The network has one or more unused input terminals, each mapped using fixed switch connections to an unused output terminal. The network also has a set of used input terminals that are selectively mapped to a set of used output terminals based on values of control signals supplied to the stages. Each stage receives a different control signal, and each control signal is generated by cyclically shifting a control seed by a corresponding cyclic-shift value. Fixing the mappings of the unused terminals ensures that the used input terminals are not mapped to any unused output terminals. By storing only the control seed, memory requirements are reduced over networks that explicitly store individual control signals for all of the stages.
    Type: Grant
    Filed: November 9, 2010
    Date of Patent: July 15, 2014
    Assignee: LSI Corporation
    Inventor: Kiran Gunnam
  • Patent number: 8769251
    Abstract: A data processing apparatus and method are provided for converting data values from a first endian format to a second endian format. Swizzle circuitry is provided for receiving a block of data containing at least one data value, and for converting each data value from the first endian format to the second endian format. The swizzle circuitry comprises first swizzle circuitry for performing a re-ordering operation on the block of data assuming the at least one data value contained therein is of a first size, in order to produce re-ordered data. Second swizzle circuitry is provided which is responsive to an indication that the at least one data value is of a size different to the first size to perform an additional re-ordering operation on the re-ordered data having regard to the size of the at least one data value in order to convert each data value to the second endian format.
    Type: Grant
    Filed: December 13, 2006
    Date of Patent: July 1, 2014
    Assignee: ARM Limited
    Inventors: Philippe Luc, Norbert Bernard Eugéne Lataille, Florent Begon, Nicolas Chaussade
  • Patent number: 8769256
    Abstract: An operating system switching method is provided. The operating system switching method is for a computer system comprising a control unit, a memory unit, and a storage unit, wherein the storage unit comprises a first operating system and a second operating system. The steps of the method include: loading the first operating system and the second operating system into a first memory space and a second memory space of the memory unit, respectively, and setting the first memory space and the second memory space to a working state and a standby state, respectively; and performing a first switching of the operating systems, and setting the first memory space and the second memory space to the standby state and the working state.
    Type: Grant
    Filed: May 18, 2011
    Date of Patent: July 1, 2014
    Assignee: Via Technologies, Inc.
    Inventors: Chin-Hwaun Wu, Chung-Ching Huang, Kuo-Han Chang, Tai-Yu Lin
  • Patent number: 8700885
    Abstract: A semiconductor device correctly switches endian modes regardless of the current endian mode of an interface. The semiconductor device includes a switching circuit and a first register. The switching circuit switches an interface to be used in big endian or little endian mode. The first register holds control data of the switching circuit. The switching circuit sets the interface in little endian mode when first predetermined control information is supplied to the first register, and sets the interface in big endian mode when second predetermined control information is supplied to the first register. The control information can be correctly inputted without being influenced by the endian setting status.
    Type: Grant
    Filed: June 19, 2013
    Date of Patent: April 15, 2014
    Assignee: Renesas Electronics Corporation
    Inventors: Goro Sakamaki, Yuri Azuma
  • Patent number: 8639914
    Abstract: An apparatus includes an instruction decoder, first and second source registers and a circuit coupled to the decoder to receive packed data from the source registers and to unpack the packed data responsive to an unpack instruction received by the decoder. A first packed data element and a third packed data element are received from the first source register. A second packed data element and a fourth packed data element are received from the second source register. The circuit copies the packed data elements into a destination register resulting with the second packed data element adjacent to the first packed data element, the third packed data element adjacent to the second packed data element, and the fourth packed data element adjacent to the third packed data element.
    Type: Grant
    Filed: December 29, 2012
    Date of Patent: January 28, 2014
    Assignee: Intel Corporation
    Inventors: Alexander Peleg, Yaakov Yaari, Millind Mittal, Larry M. Mennemeier, Benny Eitan
  • Patent number: 8607033
    Abstract: An apparatus having a first circuit and a second circuit is disclosed. The first circuit may be configured to generate a plurality of packed items by extracting-and-packing a plurality of input data words based on a bit mask. The second circuit may be configured to (i) receive the packed items from the first circuit, (ii) sequentially buffer the packed items in a plurality of registers, at least one of the packed items crossing a boundary between a current one of the registers and a next one of the registers, and (iii) write the packed items in the current register to a memory in response to the current register becoming full.
    Type: Grant
    Filed: September 3, 2010
    Date of Patent: December 10, 2013
    Assignee: LSI Corporation
    Inventors: Nimrod Alexandron, Alexander Rabinovitch, Leonid Dubrovin
  • Patent number: 8601176
    Abstract: Techniques for providing improved data distribution to and collection from multiple memories are described. Such memories are often associated with and local to processing elements (PEs) within an array processor. Improved data transfer control within a data processing system provides support for radix 2, 4 and 8 fast Fourier transform (FFT) algorithms through data reordering or bit-reversed addressing across multiple PEs, carried out concurrently with FFT computation on a digital signal processor (DSP) array by a DMA unit. Parallel data distribution and collection through forms of multicast and packet-gather operations are also supported.
    Type: Grant
    Filed: July 10, 2012
    Date of Patent: December 3, 2013
    Assignee: Altera Corporation
    Inventors: Edwin Franklin Barry, Nikos P. Pitsianis, Kevin Coopman
  • Patent number: 8601246
    Abstract: An apparatus includes an instruction decoder, first and second source registers and a circuit coupled to the decoder to receive packed data from the source registers and to unpack the packed data responsive to an unpack instruction received by the decoder. A first packed data element and a third packed data element are received from the first source register. A second packed data element and a fourth packed data element are received from the second source register. The circuit copies the packed data elements into a destination register resulting with the second packed data element adjacent to the first packed data element, the third packed data element adjacent to the second packed data element, and the fourth packed data element adjacent to the third packed data element.
    Type: Grant
    Filed: June 27, 2002
    Date of Patent: December 3, 2013
    Assignee: Intel Corporation
    Inventors: Alexander Peleg, Yaakov Yaari, Millind Mittal, Larry M. Mennemeier, Benny Eitan
  • Patent number: 8576879
    Abstract: A communication system for transmitting data, for example, within a System-in-Package. The system includes a first circuit configured for: a) dividing the data into a plurality of packets having a determined size; and b) creating for each of the packets a transmission segment including a segment header and the respective packet as payload. The system also includes a second circuit configured for: a) separating the transmission segments into a plurality of physical units, where the physical units have a determined size; and b) transmitting the physical units over a physical communication channel. In particular, the segment header includes at least one field that identifies the number of physical units that are to be transmitted.
    Type: Grant
    Filed: May 27, 2011
    Date of Patent: November 5, 2013
    Assignees: STMicroelectronics (Grenoble 2) SAS, STMicroelectronics S.r.l.
    Inventors: Alberto Scandurra, Giuseppe Guarnaccia, Ignazio Antonino Urzi'
  • Patent number: 8543736
    Abstract: A data processing circuit is disclosed in the present invention. The data processing circuit includes a decoder and a number of N-stage circuits. The circuits receive input data from at least a memory and separate the input data into N stages. The circuit process and store the N input data simultaneously to decrease the time of data processing in the data processing circuit.
    Type: Grant
    Filed: September 8, 2010
    Date of Patent: September 24, 2013
    Assignee: Etron Technology, Inc.
    Inventors: Chien-Chou Chen, Ming-Sung Huang, Wen Min Lu