Abstract: Disclosed herein includes a system, a method, and a device for reading and writing sparse data in a neural network accelerator. A mask identifying byte positions within a data word having non-zero values in memory can be accessed. Each bit of the mask can have a first value or a second value, the first value indicating that a byte of the data word corresponds to a non-zero byte value, the second value indicating that the byte of the data word corresponds to a zero byte value. The data word can be modified to have non-zero byte values stored at an end of a first side of the data word in the memory, and any zero byte values stored in a remainder of the data word. The modified data word can be written to the memory via at least a first slice of a plurality of slices that is configured to access the first side of the data word in the memory.

Abstract: In response to a replicate partition instruction specifying partition information defining positions of a plurality of variable size partitions within a result vector, an instruction decoder (20) controls the processing circuitry (80) to generate a result vector in which each partition having more than one data element comprises data values or element indices of a sequence of data elements of a source vector starting or ending at a selected data element position. This instruction can be useful for accelerating processing of data structures smaller than the vector length.

Abstract: A packet filtering system uses linked zero-based binary search trees to filter received packets. The binary search trees may be generated from filter conditions defining filter parameters for filtering packets.

Abstract: A word completion system based on a partial but exact template that entails a finite number of matches. A primary component is a close ended template made up of cues representing one or more characters, constrained by the exact number of characters in the desired word. It can be edited with pinpoint accuracy to regenerate a new result set in real time to reflect the change. The exact number of characters in the template can be indicated by a discrete signal with a designated gesture or keying in a number. The system is substantially interactive without requiring command line input or a scripting language. A delimiter or a designated signal is used to select an entry from the result set to complete the target word. The proposed method is inherently deterministic and extensible to different writing systems, and adaptable and portable to a wide range of hardware platforms.

Abstract: Disclosed herein includes a system, a method, and a device for reading and writing sparse data in a neural network accelerator. A plurality of slices can be established to access a memory having an access size of a data word. A first slice can be configured to access a first side of the data word in memory. Circuitry can access a mask identifying byte positions within the data word having non-zero values. The circuitry can modify the data word to have non-zero byte values stored starting at an end of the first side, and any zero byte values stored in a remainder of the data word. A determination can be made whether a number of non-zero byte values is less than or equal to a first access size of the first slice. The circuitry can write the modified data word to the memory via at least the first slice.

Abstract: In a method of operating a computer system, an instruction loop is executed by a processor in which each iteration of the instruction loop accesses a current data vector and an associated current vector predicate. The instruction loop is repeated when the current vector predicate indicates the current data vector contains at least one valid data element and the instruction loop is exited when the current vector predicate indicates the current data vector contains no valid data elements.

Abstract: An object of the invention is to quickly provide an effective recovery plan for a delay problem occurring at a manufacturing site. A dynamic production planning system includes a dynamic production planning device, and the dynamic production planning device includes a process actual result storage unit that includes a record of time spent on production for each item and process, a process plan actual result storage unit that includes a production facility of which usage is planned and assumed work time thereof for each item and process, and a recovery scenario generating unit configured to calculate, for each item and process, an index indicating a risk of a delay using the time spent on production and the production facility of which usage is planned and the assumed work time thereof for each item and process.

Abstract: A method for sorting of a vector in a processor is provided that includes performing, by the processor in response to a vector sort instruction, sorting of values stored in lanes of the vector to generate a sorted vector, wherein the values are sorted in an order indicated by the vector sort instruction, and storing the sorted vector in a storage location.

Abstract: Disclosed herein are systems and methods for packing stream outputs of a geometry shader into an output buffer. In one aspect, an exemplary method comprises generating, using vertices of primitives received from one or more geometry shaders, a stream output data together with an index buffer, where each absent vertex is replaced with a primitive restart, rebuilding the index buffer to a list format; and unwrapping the index data of the rebuilt index buffer to a packed buffer.

Abstract: Disclosed herein are systems and methods for reading input data into a geometry shader by rebuilding an index buffer. In one aspect, an exemplary method comprises constructing T-vectors for one-element ranges of the index buffer by defining each T-vector as a 4-component vector, calculating T-vectors for ranges [0; i] for all vertices of the index buffer by prefix scanning, for each vertex and for each primitive featuring the vertex, determining if the primitive is complete, and for each complete primitive, calculating an offset in an output index buffer using a component of the T-vector used to indicate, for the vertex, a number of complete primitives inside the range and a component that indicates a number of vertices since a last primitive restart, and writing an index value in an output index buffer, and reading input data into the geometry shader in accordance with the written index values.

Abstract: A sorter sorts a list of elements using a plurality of registers. Each register stores a value of at most one element. Each register receives an input from a previous one of the registers indicating whether the previous one of the registers is storing a value of a list element before storing a value of a list element. Each register supplies an indication to a next register whether the register is storing a list element value. A register sends a stored value and the register identification to a register stack. The register stack uses the value as an index to store a pointer to the register. In that way a sorted list is created in the register stack. A register stores list location information for one or more occurrences of a value stored by the register. Overflow of list location information is handled in a duplicate values stack.

Abstract: An example operation may include one or more of identifying a transaction from a blockchain node to be committed to a blockchain, determining available channels for assignment, assigning a channel to the blockchain node, and transmitting the transaction to the blockchain on the assigned channel.

Abstract: An apparatus includes a decode unit to decode a permute instruction and a vector conflict instruction. A vector execution unit is coupled with the decode unit and includes a fully-connected interconnect. The fully-connected interconnect has at least four inputs to receive at least four corresponding data elements of at least one source vector. The fully-connected interconnect has at least four outputs. Each of the at least four inputs is coupled with each of the at least four outputs. The execution unit also includes a permute instruction execution logic coupled with the at least four outputs and operable to store a first vector result in response to the permute instruction. The execution unit also includes a vector conflict instruction execution logic coupled with the at least four outputs and operable to store a second vector result in a destination storage location in response to the vector conflict instruction.

Abstract: A graphical user interface allows a customer to specify delimiters and/or patterns that occur in event data and indicate the presence of a particular field. The graphical user interface applies a customer's delimiter specifications directly to event data and displays the resulting event data in real time. Delimiter specifications may be saved as configuration settings and systems in a distributed setting may use the delimiter specifications to extract field values as the systems process raw data into event data. Extracted field values are used to accelerate search queries that a system receives.

Abstract: System and method of write deskew training for ×4 mode memory control interface configurations. Write leveling logic in the memory controller is adjusted to obtain a write leveling setting for delaying both first and second strobe signals associated with a byte. The adjustment is based on feedback of first set of bits of a byte and irrespective of the feedback of the second set of bits of the byte. The write leveling logic is then anchored at the write leveling setting, and a deskew delay line for the second strobe signal is adjusted to obtain a first deskew setting based on the feedback of the second set of bits. Thus, in write operations, the write leveling setting can be common within the byte even the two strobe signals are transmitted to or received from two different memory storage devices.

Abstract: Methods and apparatus are provided for performing one-dimensional (1D) transform and coefficient scanning. An encoder may apply 1D transform in either a horizontal or a vertical direction. The encoder may then determine a coefficient scan order based on the 1D transform direction. The scan order may be determined to be in a direction orthogonal to the 1D transform direction. The encoder may further flip the coefficients prior to scanning. The flipping may also be in a direction orthogonal to the 1D transform direction. A decoder may receive indications from the encoder with respect to the 1D transform, coefficient scanning, and/or coefficient flipping. The decoder may perform functions inverse to those performed by the encoder based on the indications.

Abstract: Methods and systems for encoding of integers are discussed. For example, various methods and systems may utilize Huffman coding, Tunstall coding, Arithmetic Coding, LZ77 coding, LZ78 coding, LW coding, or Shannon Fano Elias coding to encode the integers.

Abstract: A method and apparatus for a dynamic glyph based search includes an image server. The image server analyzes images to determine the content of an image. The image and data related to the determined content of the image are stored in an image database. A user can access the image server and search images using search glyphs. In response to selection of a generic-search glyph, the image server finds related images in the image database and the images are displayed to the user. In addition, refine-search glyphs are displayed to a user based on the selected generic-search glyph. One or more refine-search glyphs can be selected by a user to further narrow a search to specific people, locations, objects, and other image content.

Abstract: A processor includes packed data registers, and a decode unit to decode a data element selection and consolidation instruction. The instruction is to have a first source packed data operand that is to have a plurality of data elements, and a second source operand that is to have a plurality of mask elements. Each mask element corresponds to a different data element in the same relative position. An execution unit is coupled with the decode unit. The execution unit, in response to the instruction, is to store a result packed data operand in a destination storage location that is to be indicated by the instruction. The result packed data operand is to include all data elements of the first source packed data operand, which correspond to unmasked mask elements of the second source operand, consolidated together in a portion of the result packed data operand.

Abstract: The storage method comprises: acquiring a plurality of monitoring dimensionalities associated with each monitoring service and at least one pair of monitoring indicator data including an indicator name and an indicator value; converting the plurality of monitoring dimensionalities into a plurality of row keyword mapping values having the same length, respectively; combining monitoring time with the plurality of row keyword mapping values to form a row keyword, and setting the monitoring time in a fixed time position in the row keyword; and using the row keyword as an index to store a monitoring indicator in a distributed database. A dynamic adjustment of monitoring dimensionalities of data storage for the monitoring system is achieved in accordance with different monitoring services, thereby reducing maintenance costs and improving scalability.

Abstract: Methods and apparatuses relating to a vector instruction with a register operand with an elemental offset are described. In one embodiment, a hardware processor includes a decode unit to decode a vector instruction with a register operand with an elemental offset to access a first number of elements in a register specified by the register operand, wherein the first number is a total number of elements in the register minus the elemental offset, access a second number of elements in a next logical register, wherein the second number is the elemental offset, and combine the first number of elements and the second number of elements as a data vector, and an execution unit to execute the vector instruction on the data vector.

Abstract: Vector processing engines (VPEs) employing reordering circuitry in data flow paths between execution units and vector data memory to provide in-flight reordering of output vector data stored to vector data memory are disclosed. Related vector processor systems and methods are also disclosed. Reordering circuitry is provided in data flow paths between execution units and vector data memory in the VPE. The reordering circuitry is configured to reorder output vector data sample sets from execution units as a result of performing vector processing operations in-flight while the output vector data sample sets are being provided over the data flow paths from the execution units to the vector data memory to be stored. In this manner, the output vector data sample sets are stored in the reordered format in the vector data memory without requiring additional post-processing steps, which may delay subsequent vector processing operations to be performed in the execution units.

Abstract: Systems and methods for generating files in a virtual file system in the memory of a network system are discussed. The network system receives a filename including at least one file metadata. The file metadata includes a file size of the file, a random seed for generating content of the file, and modification information of the file. File content for the file may be generated based on the filename. The file content may then be provided to the network system.

Abstract: An apparatus and method are described for performing vector compression. For example, one embodiment of a processor comprises: vector compression logic to compress a source vector comprising a plurality of valid data elements and invalid data elements to generate a destination vector in which valid data elements are stored contiguously on one side of the destination vector, the vector compression logic to utilize a bit mask associated with the source vector and comprising a plurality of bits, each bit corresponding to one of the plurality of data elements of the source vector and indicating whether the data element comprises a valid data element or an invalid data element, the vector compression logic to utilize indices of the bit mask and associated bit values of the bit mask to generate a control vector; and shuffle logic to shuffle/permute the data elements of the source vector to the destination vector in accordance with the control vector.

Abstract: Systems of demand and capacity management with machine-time accuracy are provided. The system includes an allocation planning module, an order management module, a capacity model, and a capacity management module. The allocation planning module receives a demand plan for a product. The capacity management module transforms the demand plan into a machine-time-based plan according to the capacity model, and reserves capacity according to the machine-time-based plan for the demand plan. The capacity management module further transforms a purchase order received by the order management module before a cutoff date for the product into a machine-time-based order, accepts the machine-time-based order and decreases the reservation capacity depending on the machine-time-based plan.

Abstract: Methods and devices to allow multiple operating system images to simultaneously access a Fiber Channel fabric through a common host bus adapter port are described. For each requesting operating system image, a fabric switch maintains a unique port identifier value and a unique fabric channel address so that each operating system image may be uniquely identified across the fabric.

Abstract: An apparatus, system and method of determining an extremum are disclosed. A reference location identifier and a reference extremum are coupled. An input extremum of an input data set is determined and a corresponding location identifier of the input extremum is also determined. The input extremum is compared with the reference extremum to determine an output extremum and output location identifier, based on the comparison.

Abstract: An apparatus is described having instruction execution logic circuitry. The instruction execution logic circuitry has input vector element routing circuitry to perform the following for each of three different instructions: for each of a plurality of output vector element locations, route into an output vector element location an input vector element from one of a plurality of input vector element locations that are available to source the output vector element. The output vector element and each of the input vector element locations are one of three available bit widths for the three different instructions. The apparatus further includes masking layer circuitry coupled to the input vector element routing circuitry to mask a data structure created by the input vector routing element circuitry. The masking layer circuitry is designed to mask at three different levels of granularity that correspond to the three available bit widths.

Abstract: Provided is a join processing device that performs a similarity join process to plural tuples using an edit distance threshold value ? (positive integer). The join processing device includes a join processing unit that excludes, from a target of edit distance calculation, a pair of tuples that do not have any common character in an end portion ranging from a head character or a tail character to a (?+1)th character in a join key string in each of the tuples.

Abstract: Method, apparatus, and program means for shuffling data. The method of one embodiment comprises receiving a first operand having a set of L data elements and a second operand having a set of L control elements. For each control element, data from a first operand data element designated by the individual control element is shuffled to an associated resultant data element position if its flush to zero field is not set and a zero is placed into the associated resultant data element position if its flush to zero field is not set.

Abstract: A method for content extraction and modeling by a computer system for incorporating the content into a domain model including the steps of extracting by an acquisition module content stored on a computer readable medium of at least one data source, determining whether the content is structured or unstructured; wherein structured content has a first content model associated therewith defining at least a format of the structured content and unstructured content has no model associated therewith. Upon a condition in which the content is structured, incorporating the structured content into the domain model; and, upon a condition in which the content is unstructured, determining by the computer system a second content model to transform the unstructured content into newly structured content and incorporating the newly structured content into the domain model.

Abstract: Embodiments of the present invention provide a data processing system and a data processing method. An MMIO address of a data request is obtained, where data stored in a PCIe storage device can be directly obtained from the MMIO address, and according to the MMIO address, a network adapter can directly read the data from the PCIe storage device of the data processing system, and transmit the data to a second data processing system, or directly write the data received from the second data processing system into the PCIe storage device. Therefore, the processing system can implement transmitting data directly from the PCIe storage device to the network adapter without using memory. During data transmission between the two data processing systems, a usage ratio of a resource, such as memory and a CPU, is reduced, and efficiency of data transmission is improved.

Abstract: Techniques for packing and unpacking data from a source register using a particular shift instruction are provided. The shift instructions takes, as input, a source register that contains a plurality of elements and a shift count register that contains a plurality of shift counts. Each shift count indicates how much to shift bits from the source registers. Where “source” bits are shifted (or copied) to in an output register depends on the position of the shift count in the shift count register. The shift counts may correspond to one or more bytes from the source register. The shift instruction may initiate a left shift operation or a right shift operation.

Abstract: Methods, systems, and media for partial downloading in wireless distributed networks are provided. In some embodiments, methods for selecting numbers of symbols to be transmitted on a plurality of channels are provided, the methods comprising: for each of the plurality of channels, calculating using a hardware processor an increase in power that will be used by that channel if it transmits a symbol; selecting one of the plurality of channels with the smallest increase in power using the hardware processor; and allocating the symbol to the one of the plurality of channels using the hardware processor.

Abstract: A method and circuit arrangement selectively swizzle data in one or more levels of cache memory coupled to a processing unit based upon one or more swizzle-related page attributes stored in a memory address translation data structure such as an Effective To Real Translation (ERAT) or Translation Lookaside Buffer (TLB). A memory address translation data structure may be accessed, for example, in connection with a memory access request for data in a memory page, such that attributes associated with the memory page in the data structure may be used to control whether data is swizzled, and if so, how the data is to be formatted in association with handling the memory access request.

Abstract: An information processing apparatus includes first electronic circuit and one or a plurality of second electronic circuits. The first electronic circuit has a first buffer for storing information, and is configured to execute predetermined first information processing by reading out information from a memory connected via a first transmission path, and write the information processed by the first information processing into the memory. The one or plurality of second electronic circuits have a second buffer for storing information, and are connected to the first electronic circuit via a second transmission path different from the first transmission path, and the one or plurality of second electronic circuits are configured to execute second information processing different from the first information processing. The first electronic circuit is configured to execute the first information processing, using the second buffer of the second electronic circuit that is in an unused state and the first buffer.

Abstract: A method and circuit arrangement selectively swizzle data in one or more levels of cache memory coupled to a processing unit based upon one or more swizzle-related page attributes stored in a memory address translation data structure such as an Effective To Real Translation (ERAT) or Translation Lookaside Buffer (TLB). A memory address translation data structure may be accessed, for example, in connection with a memory access request for data in a memory page, such that attributes associated with the memory page in the data structure may be used to control whether data is swizzled, and if so, how the data is to be formatted in association with handling the memory access request.

Abstract: Method, apparatus, and program means for performing bitstream buffer manipulation with a SIMD merge instruction. The method of one embodiment comprises determining whether any unprocessed data bits for a partial variable length symbol exist in a first data block is made. A shift merge operation is performed to merge the unprocessed data bits from the first data block with a second data block. A merged data block is formed. A merged variable length symbol comprised of the unprocessed data bits and a plurality of data bits from the second data block is extracted from the merged data block.

Abstract: An information processing apparatus generates first and second trees representing a dependency relationship among instructions from first code. The information processing apparatus then adjusts the height of the shorter one of the first and second trees by inserting pseudo instructions that do not cause any difference in data before and after operation in the shorter tree, and also shuffles the order of instructions existing at the same depth from the root, according to operation types in at least one of the first and second trees. The information processing apparatus compares the first and second trees subjected to the height adjustment and the order shuffling with each other to determine combinations of an instruction of the first tree and an instruction of the second tree.

Abstract: A method of and system for managing diagnostic information is disclosed. The method and system may include creating a data space in volatile memory. The data space may be configured to collect a selected diagnostic information. The selected diagnostic information may include a first diagnostic information from a first source and a second diagnostic information from a second source. The method and system may include collecting in the data space the selected diagnostic information. The method and system may include releasing from the data space at least a portion of the selected diagnostic information in response to a triggering event.

Abstract: An example of a system comprises a fingerprint calculator configured to receive data structure information and create a fingerprint as a function of the data structure information, a code generator configured to generate modified machine code, the modified machine code including the fingerprint embedded therein, a fingerprint identifier configured to identify the fingerprint in data received from a data dump, a data structure lookup table including the fingerprint and the data structure information associated with the fingerprint stored thereon, and a data interpreter configured to interpret, using data from the data dump and the data structure information, the data structure of at least a portion of the data from the data dump.

Abstract: The present invention is to provide a semiconductor device that can correctly switch endians on the outside even if the endian of a parallel interface is not recognized on the outside. The semiconductor device includes a switching circuit and a first register. The switching circuit switches between whether a parallel interface with the outside is to be used as a big endian or a little endian. A first register holds control data of the switching circuit. The switching circuit regards the parallel interface as the little endian when first predetermined control information, that is unchanged in the values of specific bit positions even if its high-order and low-order bit positions are transposed, is supplied to the first register, and regards the parallel interface as the big endian when second predetermined control information, that is unchanged in the values of specific bit positions even if its high-order and low-order bit positions are transposed, is supplied to the first register.

Abstract: A computer-implemented method of and a device, such as a base station for a headset, for arranging text items in a predefined order, comprising storing, in the memory of a peripheral device, a collection of multiple text items arranged in multiple sets of text items and in multiple groups of text items; storing a respective code item with a respective group of text items; and storing a sort key that has values that designate a predefined order of the text items in each set. The sort key is appended to the text items and comprises at least one character with a value within the Private Use range of the Unicode format.

Abstract: A computer implemented method selects K extreme elements of a list of N elements by partitioning each of the N elements into a plurality of sections. For each section the method selects a threshold selection determining at least K extreme entries from the list. This iteratively compares a corresponding section to a section threshold, counts a number of sections which are more extreme than the section threshold, increasing (or decreasing) the section threshold if the count is greater than K and decreasing (or increasing) the section threshold if the count is less than K. The method forms a combined threshold by concatenation of said section thresholds in order, compares each of the N elements to the combined threshold, and selects at least K elements from the set of N elements more extreme than the combined threshold.

Abstract: An apparatus includes an instruction decoder, first and second source registers and a circuit coupled to the decoder to receive packed data from the source registers and to unpack the packed data responsive to an unpack instruction received by the decoder. A first packed data element and a third packed data element are received from the first source register. A second packed data element and a fourth packed data element are received from the second source register. The circuit copies the packed data elements into a destination register resulting with the second packed data element adjacent to the first packed data element, the third packed data element adjacent to the second packed data element, and the fourth packed data element adjacent to the third packed data element.

Abstract: The present invention is to provide a semiconductor device that can correctly switch endians on the outside even if the endian of a parallel interface is not recognized on the outside. The semiconductor device includes a switching circuit and a first register. The switching circuit switches between whether a parallel interface with the outside is to be used as a big endian or a little endian. A first register holds control data of the switching circuit. The switching circuit regards the parallel interface as the little endian when first predetermined control information, that is unchanged in the values of specific bit positions even if its high-order and low-order bit positions are transposed, is supplied to the first register, and regards the parallel interface as the big endian when second predetermined control information, that is unchanged in the values of specific bit positions even if its high-order and low-order bit positions are transposed, is supplied to the first register.

Abstract: In one embodiment, the present invention includes logic to receive a permute instruction, first and second source operands, and control values, and to perform a permute operation based on an operation between at least two of the control values so that selected portions of the first and second source operands or a predetermined value can be stored into elements of a destination. Multiple permute instructions may be combined to perform efficient table lookups. Other embodiments are described and claimed.

Abstract: A device system and method for processing program instructions, for example, to execute intra vector operations. A fetch unit may receive a program instruction defining different operations on data elements stored at the same vector memory address. A processor may include different types of execution units each executing a different one of a predetermined plurality of elemental instructions. Each program instruction may be a combination of one or more of the elemental instructions. The processor may receive a vector of data elements stored non-consecutively at the same vector memory address to be processed by a same one of the elemental instructions and a vector of configuration values independently associated with executing the same elemental instruction on the non-consecutive data elements. At least two configuration values may be different to implement different operations by executing the same elemental instruction using the different configuration values on the vector of non-consecutive data elements.

Abstract: An apparatus includes an instruction decoder, first and second source registers and a circuit coupled to the decoder to receive packed data from the source registers and to unpack the packed data responsive to an unpack instruction received by the decoder. A first packed data element and a third packed data element are received from the first source register. A second packed data element and a fourth packed data element are received from the second source register. The circuit copies the packed data elements into a destination register resulting with the second packed data element adjacent to the first packed data element, the third packed data element adjacent to the second packed data element, and the fourth packed data element adjacent to the third packed data element.

Abstract: A computer, circuit, and computer-readable medium are disclosed. In one embodiment, the processor includes an instruction decoder unit that can decode a macro instruction into at least one micro-operation with a set of data fields. The resulting micro-operation has at least one data field that is in a compressed form. The instruction decoder unit has storage that can store the micro-operation with the compressed-form data field. The instruction decoder unit also has extraction logic that is capable of extracting the compressed-form data field into an uncompressed-form data field. After extraction, the instruction decoder unit also can send the micro-operation with the extracted uncompressed-form data field to an execution unit. The computer also includes an execution unit capable of executing the sent micro-operation.