Abstract: A pipeline video decoder and decompression system handles a plurality of separately encoded bit streams arranged as a single serial bit stream of digital bits and having separately encoded pairs of control codes and corresponding data carried in the serial bit stream. The pipeline system employs a plurality of interconnected stages to decode and decompress the single bit stream, including a start code detector. When in a search mode, the start code detector searches for a specific start code corresponding to one of multiple compression standards. The start code detector responding to the single serial bit stream generates control tokens and data tokens. A respective one of the tokens includes a plurality of data words. Each data word has an extension bit which indicates a presence of additional words therein. The data words are thereby unlimited in number.

Abstract: The bits comprising a computer data structure are reversed rapidly and efficiently using a combination of data partitioning and table look ups. In an exemplary embodiment, the invention is employed in the pre-processing of Advanced Configuration and Power Interface (ACPI) tables stored in little-endian format for use by a big-endian operating system.

Abstract: The invention is a method for dynamically converting the byte-ordering of a data structure of a resource type from a first format to a second format, the first format being incompatible with the second format. The method comprises the following steps: (a) creating a template which corresponds to the data structure of the resource type, the template having a structure in a third format which is compatible with the first and second formats; (b) linking the template to the resource type; and (c) converting automatically the byte-ordering of the data structure of the resource type from the first format to the second format using the template.

Abstract: A method is disclosed for comparing a pattern sequence with a variable length key. A first bit of this sequence is identified by a pointer, the length and the location of the key are identified by a code word (W, S), the method includes a preliminary step of identifying the sequence and then performing a comparison with the variable length key.

Abstract: A method for transmitting data between a microprocessor and an external memory module through external package pins of the microprocessor, which includes the steps of: a) deciding N-bit full sized data to be transferred by using M, wherein N and M are positive integers and N is greater than M; b) sequentially transferring N/M number of M-bit divided data; c) temporarily storing N/M number of M-bit divided data; and d) combining the N/M number of M-bit divided data into the N-bit full sized data.

Abstract: An input data word contains multiple abutting input data values An. The input data word is split into two intermediate data words into which respective high order portions and low order portions of the data values are written spaced apart by vacant portions. Each intermediate data word may then be subject to one or more data processing operations with bits of the results extending into the vacant portions without corrupting adjacent data values. Finally, the intermediate data words may be recombined to produce result data values.

Abstract: A method and apparatus for analyzing and formatting strings of data, such as data derived from software processes running on two data processors. In one embodiment, a plurality of different data strings are initialized building a symbol array, and finding differences within the data by analyzing various relationships within the data strings, such as the existence of unique strings. A computer program and apparatus for synthesizing logic implementing the aforementioned methodology are also disclosed.

Abstract: A pipeline video decoder and decompression system handles a plurality of separately encoded bit streams arranged as a single serial bit stream of digital bits and having separately encoded pairs of control codes and corresponding data carried in the serial bit stream. The pipeline system employs a plurality of interconnected stages to decode and decompress the single bit stream, including a start code detector. When in a search mode, the start code detector searches for a specific start code corresponding to one of multiple compression standards. The start code detector responding to the single serial bit stream generates control tokens and data tokens. A respective one of the tokens includes a plurality of data words. Each data word has an extension bit which indicates a presence of additional words therein. The data words are thereby unlimited in number.

Abstract: A multi-standard video decompression apparatus has a plurality of stages interconnected by a two-wire interface arranged as a pipeline processing machine. Control tokens and DATA Tokens pass over the single two-wire interface for carrying both control and data in token format. A token decode circuit is positioned in certain of the stages for recognizing certain of the tokens as control tokens pertinent to that stage and for passing unrecognized control tokens along the pipeline. Reconfiguration processing circuits are positioned in selected stages and are responsive to a recognized control token for reconfiguring such stage to handle an identified DATA Token. A wide variety of unique supporting subsystem circuitry and processing techniques are disclosed for implementing the system.

Abstract: A crossbar is implemented within multimedia facilities of a processor to perform vector permute operations, in which the bytes of a source operand are reordered in the target output. The crossbar is then reused for other instructions requiring multiplexing or shifting operations, particularly those in which the size of additional multiplexers or the size and delay of a barrel shifter is significant. A wide shift operation, for example, may be performed with one cycle latency by the crossbar and one additional layer of multiplexers or a small barrel shifter. The crossbar facility thus gets reused with improved performance of the instructions now sharing the crossbar and a reduction in the total area required by a multimedia facility within a processor.

Abstract: An endian conversion apparatus includes a first switch. The first switch inputs an input byte data, a data size signal, an endian switch signal and a byte enable data to output an output byte data on which a second endian representation is performed. The input byte data includes a plurality of byte data on which a first endian representation is performed. The data size signal indicates the number of bytes to be recognized as a unit data. The endian switch signal indicates an execution of an endian conversion. The byte enable data indicates a byte position to be recognized as the unit data. The first endian representation is performed on the byte enable data. The first switch outputs the output byte data having the number of bytes indicated by the data size signal when the endian switch signal indicates the execution. An array of the byte position indicated by the byte enable data is maintained in the output byte data.

Abstract: When one or more storage data are coincident with single search data (105), an associative memory with a shortest mask producing function carries out logical multiplication for all of mask information corresponding to the coincident storage data with a mask valid state as true. The result of logical multiplication is used as shortest mask information. In a primary searching operation, the associative memory with a shortest mask producing function is supplied with the search data (105) to provide the shortest mask information on shortest mask lines. Then, as a secondary searching operation, the shortest mask information thus extracted is used as the search data and supplied to the associative memory with a shortest mask producing function. Among the coincident storage data, only a mask match line connected to a particular word having mask information coincident with the shortest mask information is selected as the secondary search result.

Abstract: A packet processor having a general-purpose arithmetic operator and another dedicated circuit, which extracts a particular field from the general-purpose register as object field, on which the predetermined general-purpose arithmetic operation is to be performed by the general-purpose arithmetic operator and writes a result of the arithmetic operation by the general-purpose arithmetic operator into the general-purpose register as updated information of the particular field. Based on the extraction and write process of the packet field designated by software (instructions), the packet processor realizes high flexibility and high speed processing.

Abstract: A table storing a state transition rule is arranged in a memory. By referencing the table based on input data, the process to be performed for the input data is determined and executed. Additionally, a process capability can be changed by altering a setting in this table. As a result, a data processing device that can perform the processes for general-purpose data, such as a stream data process, etc., at high speed, and can flexibly change a capability according to the circumstances.

Abstract: A method for optimizing bus transactions in a data processing system is provided. A bus transaction optimizer receives an original bus transaction request which includes an original start address of a target memory for the original bus transaction, an original byte size for a number of bytes for the original bus transaction, and an original bus command for the original bus transaction. The bus transaction optimizer generates multiple bus transaction requests in response to a determination that the original byte size is greater than or equal to a predetermined multiple transfer byte size data value. The multiple bus transaction requests may include at least one high-performance bus transaction request and at least one low-performance bus transaction request.

Abstract: An apparatus and method of performing random bit swapping including bit (single bit) swapping, nibble (4-bit) swapping, byte (8-bit) swapping, and half word (16-bit) swapping including a matrix of rows of two-to-one multiplexers. Each row of multiplexers shares the same control signal such that all of the multiplexer in a given row either outputs a “non-swapped” bit value or a “swapped” bit value. In addition, multiplexers are grouped within rows to allow 2-bit, 4-bit, 8-bit, and n-bit swaps in each consecutive row. Depending on the shared multiplexer controls for each row, the matrix can be programmed to perform any swapping function or possible bit pattern. The number of bits output by the matrix determines the number of rows used, e.g., an 8-bit dataword uses 3 rows, 16-bit word uses 4 rows, 2N-bit word uses N rows.

Abstract: The present invention comprises an efficient system and method for writing specific bytes in a wide-word configured memory. A memory controller is configured to write from a wide-word databus to specific bytes in a wide-word addressed memory. The memory controller uses wide-word memory addresses which possess resolution capable of addressing specific bytes, and, in addition, data mask bytes which inhibit data write operations to those bytes in a wide-word which are not intended to be written in a given memory write operation. In one embodiment of the present invention, data mask bytes are created by shifting predetermined bit patterns to the right by an amount calculated by arithmetically combining bits in the wide-word memory address. A flexible individual address generating scheme allows memory write operations which do not depend upon the memory write operation's data boundaries being evenly aligned with the boundaries of wide-words.

Abstract: A programmable data communications device is provided to process multiple streams of data according to multiple protocols. The device is equipped with a co-processor including multiple, programmable processors allowing data to be operated on by multiple protocols. The programmable processors within the co-processor include extended instruction sets including instructions providing the operations of zero stuffing, CRC computation, partial compare, conditional move, and trie traversal. These instructions allow the processor(s) of the co-processor to more efficiently execute programs implementing data communications protocols. Since each processor is programmable, protocols standards which change may be accommodated. A network device equipped with the co-processor can handle multiple simultaneous streams of data and can implement multiple protocols on each data stream. The protocols can execute within the co-processor either independently of each other, or in conjunction with each other.

Abstract: A crossbar is implemented within multimedia facilities of a processor to perform vector permute operations, in which the bytes of a source operand are reordered in the target output. The crossbar is then reused for other instructions requiring multiplexing or shifting operations, particularly those in which the size of additional multiplexers or the size and delay of a barrel shifter is significant. A vector pack instruction with saturation detection, for example, may be performed with one cycle latency by the crossbar and a correction multiplexer for substituting saturated values. The crossbar facility thus gets reused with improved performance of the instructions now sharing the crossbar and a reduction in the total area required by a multimedia facility within a processor.

Abstract: A novel method and apparatus is disclosed for locating the first most, or least, significant set bit in a bit-string. The present invention breaks down the bit-string into a plurality of shorter sub-strings so that boolean operations can be performed directly to the shorter sub-strings for determining the location of the most/least significant set bit. Furthermore, this method can be repeatedly used to reduce the length of the shorter sub-string after the most/least significant sub-string is located. Particularly, this method of repeatedly dividing the bit-string greatly increases the speed of locating the set bit.

Abstract: A length decoder that rapidly calculates the group lengths of groups of variable length data words is provided. In accordance with one embodiment, a length decoder includes a length estimator and a length selector. The length estimator, estimates a length for each data word assuming the data word is the first member of a group. The length selector then selects the proper estimate based upon the actual length of the data word. Specifically, one embodiment of the length decoder can be used to calculate the length of instruction groups in a stack based computing system.

Abstract: A method and system for efficiently transferring data between a host computer and a peripheral component which is removably coupled to the host computer. In one embodiment of the present invention, a peripheral component driver such as, for example, a network interface card driver receives a request from a peripheral component, such as, for example, a network interface card, to transfer data from the peripheral component to memory of the host computer. The data to be transferred requires a first block of memory in the host computer wherein the first block of the memory has a first size. The present embodiment then allocates a second block of memory in the host computer to receive the data from the peripheral component. In the present invention, the second block of memory has a second size which is greater than the first size. Additionally, the second block of memory comprises an integer unit of the memory.

Abstract: A computer and a method of operating a computer is disclosed which allow manipulation of data values in the context of the execution of so-called "packed instructions". Packed instructions are carried out on packed operands. A packed operand comprises a data string consisting of a plurality of sub-strings, each defining a particular data value or object. The invention relates to a restructuring instruction which allows objects to be reorganized within a data string thereby minimizing loading and storing operations to memory.

Abstract: The invention provides a data packing device that packs selected bits of input data into an output data. The data packing device includes a data positioner, an output latch, and output selector and a controller. The data positioner positions the bits of the input data relative to bit positions of the output latch so that the selected bits from the input data may be packed. The output latch includes a first portion and a second portion which are packed alternately in a ping-pong manner. The controller is implemented using state machines where one state machine is allocated for packing a specific number of bits selected from the input data into the output data. Thus, the controller includes a number of state machines where each state machine corresponds to one selected number of bits of the input data that may be selected to be packed. For input data in bytes, the controller includes eight state machines.

Abstract: A multimedia facility within a processor employs a crossbar to perform operations requiring byte reordering. Prior to the cycle in which an instruction is executed, the instruction is checked to determine if the instruction is a predetermined type of instruction. If not, the operand which should contain encoded crossbar selects is filled with zeros before presentation to the crossbar select generation logic. If the instruction is one of the predetermined type of instructions, however, the real operand containing the encoded crossbar selects is presented to the crossbar select generation logic. As a result, only crossbar selects which designate byte 0 of the source operand as the source need to be qualified with a signal verifying the instruction being executed. The fanout of the qualification signal is thus reduced to an acceptable level, at which 1 cycle latency and 1 cycle throughput may be achieved.

Abstract: A compiler has optimization processing part which comprise a loop normalization processing part for normalizing a loop structure in an intermediate language program, a subscript expression analyzing part for analyzing the presence or not of non-aligned access in the normalized loop structure, an SIMD instruction converting part for modifying an intermediate code so to perform computing of the array elements by using an SIMD instruction sequence, and a non-aligned access processing part for recognizing parts which are not word-aligned access in the array elements on a main storage subjected to the SIMD computing and converting a part of the non-aligned access into a combination of wored-aligned access instructions and shift instructions with logical instructions.

Abstract: An apparatus and method for performing vertical parallel operations on packed data is described. A first set of data operands and a second set of data operands are accessed. Each of these sets of data represents graphical data stored in a first format. The first set of data operands is convereted into a converted set and the second set of data operands is replicated to generate a replicated set. A vertical matrix multiplication is performed on the converted set and the replicated set to generate transformed graphical data.

Abstract: One aspect of the invention relates to a method for processing load instructions in a superscalar processor having a data cache and a register file. In one embodiment, the method includes the steps of dispatching a misaligned load instruction to access a block of data that is misaligned in the cache; while continuing to dispatch aligned instructions: generating a first access and a final access to the cache in response to the misaligned load instruction; storing data retrieved from the first access until data from the final access is available; reassembling the data from the first and final access into the order required by the load instruction; and storing the re-assembled data to the register file.

Abstract: In a longest coincidence data detecting apparatus, a control section distributes an external data to the N M-bit associative memory units to satisfy a relation of X.sub.ij =Y.sub.Nj+i where each of N and M is an integer more than 1, 0.ltoreq.i<N, 0.ltoreq.j<M, i and j are integers, X.sub.ij is a j-th bit of the i-th one of the N associative memory units, and Y.sub.k is a k-th bit of the external data. Each of the N associative memory units compares a distributed portion of the external data and a corresponding portion of an internal data in a designated bit region from a most significant bit of the distributed portion, and outputs a matching signal when the distributed portion of the external data portion and the corresponding portion of the internal data are coincident with each other in the designated bit region.

Abstract: An improved load data formatter and methods for improving load data formatting and for cache line data organization are disclosed. The load data formatter includes a data selection mechanism, the data selection mechanism receiving a data cache line of a predetermined organization, and the data selection mechanism further supporting adjacent word swapping in the cache line. The load data formatter further includes at least two word selectors coupled to an output of the data selection mechanism, the at least two word selectors forming a doubleword on a chosen word boundary of the cache line. In a further aspect, the predetermined organization of the cache line is provided by grouping each corresponding bit of each byte in a cache line of data together, and expanding the grouping with an organization formed by one bit from a same byte within each word.

Abstract: A system and method for aligning data in stack memory in a data processing system where the stack memory provides temporary storage for storing parameters for a function call. The method first determines if any of the parameters in the function being call are of a selected type. If a parameter is of a selected type, code is generated for aligning the parameter on a stricter boundary than the default boundary for the stack memory. Code is then generated to align the remaining parameters in the function call on the default boundary in the stack memory. The aligned parameter in the stack provides a reference point which is used by the called function to align locally scoped variables in the stack. By aligning a parameter of a selected type on stricter boundary in the stack, for example, a double precision floating point aligned on an 8 byte boundary, the execution performance of the compiled program code is improved.

Abstract: A programmable data communications device is provided to process multiple streams of data according to multiple protocols. The device is equipped with a co-processor including multiple, programmable processors allowing data to be operated on by multiple protocols. The programmable processors within the co-processor include extended instruction sets including instructions providing the operations of zero stuffing, CRC computation, partial compare, conditional move, and trie traversal. These instructions allow the processor(s) of the co-processor to more efficiently execute programs implementing data communications protocols. Since each processor is programmable, protocols standards which change may be accommodated. A network device equipped with the co-processor can handle multiple simultaneous streams of data and can implement multiple protocols on each data stream. The protocols can execute within the co-processor either independently of each other, or in conjunction with each other.

Abstract: A method and apparatus allowing for the direct manipulation of bit fields contained in a memory source. Logic circuitry performs a process wherein bit segments and bit fields contained in respective data strings are manipulated or moved along respective data strings, wherein the bit fields may not be aligned in accordance with data bytes contained in a respective data string. Additionally, the logic circuitry may mask any bits not associated with either the bit segment and the bit field in the respective data strings. The logic circuitry performs an arithmetic operation, wherein the masked respective data strings are arithmetically coupled to each other providing a resultant data string, the resultant data string containing the arithmetic result of the bit segment and the bit field segment as a bit field result. The logic circuitry can pass forward masks of the bit field result and any partially modified byte(s) instead of an entire mask of the respective data strings.

Abstract: Detecting an encoding system used to encode computer readable text or data across a wide variety of encoding systems. When a user attempts to download and use text or data on his or her computer, encoded data is passed from the desired text or data file to a series of code readers. Each code reader is programmed to read encoded data according to the rules of a given encoding system. When a given code reader is unable to validate a byte of data according to the encoding system rules associated with that reader, that reader is deactivated. This process of elimination leads to a single reader and a single encoding system. If the list of readers is not eliminated to a single reader, ambiguity resolution is performed to narrow the list of readers to a single reader. Once the list of active readers is narrowed to one, the encoding system associated with that reader is returned as the encoding system with which the data is encoded.

Abstract: A method and apparatus are provided for reducing the number of cache line data transfers among components of a computer system, thus reducing the amount of traffic on a bus and increasing overall system performance. A sideband communication line is provided to transfer information from a source cache agent pertaining to redundant data strings occurring in a cache line to a destination cache agent. If redundant data strings occur in a cache line, the transfer of one or more portions of a cache line from the source to the destination can be canceled. Redundancy logic is provided to detect occurrences of redundant data strings located in a given cache line, generate and transfer redundancy bits when predetermined redundant data strings occur and decode redundancy bits at a destination cache agent to determine whether redundant data strings occur in subsequent cache lines to be transferred.

Abstract: A circuit for eliminating bubble errors occurring in a thermal code, which is comprised of a plurality of data bits, and its operation method are disclosed. The circuit is implemented by a plurality of interchange units, each of which processes one of the data bits, respectively. When any two successive data bits present a predetermined pattern, an interchange operation between the associated interchange units is continuously performed until the predetermined pattern is completely removed. Accordingly, the electronic bubble evaporation circuit developed in accordance with the present invention can eliminate bubble errors occurring in the thermal code even if the bubbles occur randomly.

Abstract: A programmable data communications device is provided to process multiple streams of data according to multiple protocols. The device is equipped with a co-processor including multiple, programmable processors allowing data to be operated on by multiple protocols. The programmable processors within the co-processor include extended instruction sets including instructions providing the operations of zero stuffing, CRC computation, partial compare, conditional move, and trie traversal. These instructions allow the processor(s) of the co-processor to more efficiently execute programs implementing data communications protocols. Since each processor is programmable, protocols standards which change may be accommodated. A network device equipped with the co-processor can handle multiple simultaneous streams of data and can implement multiple protocols on each data stream. The protocols can execute within the co-processor either independently of each other, or in conjunction with each other.

Abstract: A processor implemented method of modifying a string of a regular language, which includes at least two symbols and at least two predetermined substrings. Upon receipt of the string, the processor determines an initial position within the string of a substring matching one of the preselected substrings. To make this determination, the processor either matches symbols of the string starting from the left and proceeding to the right or by starting from the right and proceeding to the left. After identifying the initial position, the processor then selects either the longest or the shortest of the preselected substrings. The processor then replaces the matching substring with the string of the lower language associated with the selected preselected substring and outputs the modified string.

Abstract: Apparatus, methods and computer program products are disclosed that enable a compiler to generate efficient code to access stack registers on a register stack. The invention operates by transforming a three-operand instruction, within a compiler's intermediate representation, to one or more fewer-than-three-operand instructions. The invention also transforms the instruction's operand addressing from an access to a pseudo-named register to an access to a stack register through stack offset into a register stack. The invention also determines the register stack state at each instruction responsive to register stack permutations and maps the stack offset accordingly for each subsequent access to a stack register.

Abstract: An apparatus for use in a computer system comprises a first storage area and a circuit, coupled to the first storage area, configured to perform a comparison of a data element A with a data element B. In response to a single instruction, the circuit performs the comparison and outputs a condition field of at least one bits when the comparison of A and B is TRUE, or else the circuit outputs the ones-complement of the condition field when the comparison of A and B is FALSE. The circuit may be used in conjunction with a sequence of instructions to select bits from a first data element and bits from a second data element using the one or more condition field bits.

Abstract: An instruction (also called a "bit reversal instruction") for reversing the order of bits in an input signal is implemented by reusing one or more components in a datapath normally found in a processor. Specifically, a bit reversal instruction is implemented by reuse of a shifter unit normally used in a datapath to shift bits of an input signal. The shifter unit includes three stages: a first stage formed by a number of input multiplexers, a second stage formed by, for example, a left shifter, and a third stage formed by a number of output multiplexers. When using a left shifter to implement the bit reversal instruction, the input multiplexers are not used. Instead, the left shifter is used to shift bits of the input signal left by a number that is inverse of the number of bits to be reversed. Thereafter, the output multiplexers reverse the order of bits generated by the left shifter, thereby completing the bit reversal instruction.

Abstract: A system device of a PC, XT or AT type computer having an ISA bus is provided with a dynamic 32-bit bus by packing circuits or PACs (142, 152) located on user add-on cards. Each PAC includes a state machine (200) which controls four tag registers (210, 211, 212, 213), four input data registers (220, 221, 222, 223), four output data registers (240, 241, 242, 243), and an output multiplexer (250). The four tag registers are for storing a byte-high enable signal BHEN and system address bits SA[1:0] associated with bytes, words, and doublewords presented to the PAC during bus write cycles. The four input data registers are for storing the bytes, words, and doublewords presented to the PAC during bus write cycles. These bytes, words, and doublewords are steered to appropriate bit positions in the input data registers by four steering circuits (214, 215, 216, 217), which are controlled by the platform type signal CR2B2.sub.-- 1 and by the output of a decoder decoding the outputs of the tag registers.

Abstract: An endian domain conversion circuit for converting data packets transmitted between two bus interfaces. The novel system advantageously eliminates any requirement for a large bit switch within the circuit's write data path. Instead, endian conversion intelligence is placed into the read data path. Double words (dwords) are individually received from an incoming data packet and bytes are parallel stored into the same byte location of several different first-in-first-out (FIFO) memories. In one example, the dwords are 32-bits each and the number FIFO memories used is four. An entire input data packet is received in this manner, incrementing the write address of the FIFO memories for each dword. Depending on the type of endian domain conversion required, if at all, endian conversion control circuitry of the present invention controls the manner in which the four exemplary FIFO memories are read (via a read pointer) and the manner which their data is supplied over the output bus to generate the output data.

Abstract: This invention describes a numeric intensive development environment for producing code for various fixed point DSP's and providing a debug capability that assists the user by displaying various data from the DSP in various formats. The DSP code is created in a DSP-C language which is based on low level assembly language tools enhanced with extensive native mathematical representation formats and high level language syntax. This provides the advantage of handling numeric representation in high level language and optimizing the code for speed and compactness in low level language. Once the code is created in DSP-C it can be connected to a DSP through a driver and driver interface. The driver interface allows the code to be universal with a different driver being used to connect the code to different DSP's. In debug mode data from a target DSP is continuously fetched allowing the user to make real time modifications to the code and get real time feed back of the results.

Abstract: A data transposition system reorders successive input groups of N data elements received in column order into corresponding output groups of data elements arranged in row order. The system includes a memory having N data element storage locations and a transposition address generator for repetitively generating a series of different sequences of address signals. The address signals of each sequence are sequentially applied to the memory for reading the data elements stored at the addressed storage locations for providing the output groups of data elements. Each read data element is replaced with the data element of the next input group corresponding in order to the order of the respective address signal within its associated sequence.