Abstract: Data processing engines are provided that include an electronic display, a decoding functionality selector, a decoding functionality generator in communication with the decoding functionality selector, and a decoding functionality verifier, each configured as described anywhere herein. Related methods of automatically constructing platform-independent decoders for encoded digital data encoded in particular formats are also provided as described anywhere herein.

Abstract: An apparatus for protecting a processor includes an input interface and protection circuitry. The input interface is configured to monitor code instructions that are processed by the processor, one or more of which code instructions including one or more error-detection bits. The protection circuitry is configured to detect an error in the program code using the error-detection bits, and to initiate a responsive action in response to detecting the error.

Abstract: A method includes provisioning a first Virtual Network Function (VNF) component on a first virtual machine, the first virtual machine being supported by a first physical computing system, provisioning a second VNF component directly on a second physical computing system, and using, within a telecommunications network, a VNF that includes both the first VNF component running on the first virtual machine and the second VNF component running directly on the second physical computing system. The method further includes, with a VNF manager, determining that a third VNF component should be provisioned, and in response to determining that the third VNF component is capable of utilizing a hardware accelerator associated with a third physical computing system, implementing the third VNF component on the third physical computing system.

Abstract: A processing system includes a processor with a branch predictor including one or more branch target buffer tables. The processor also includes a branch prediction pipeline including a throttle unit and an uncertainty accumulator. The processor assigns an uncertainty value for each of a plurality of branch predictions generated by the branch predictor and adds the uncertainty value for each of the plurality of branch predictions to an accumulated uncertainty counter associated with the uncertainty accumulator. The throttle unit of the branch prediction pipeline throttles operations of the branch prediction pipeline based on the accumulated uncertainty counter.

Abstract: Systems and methods for instruction decoding using hash tables. An example method of constructing a decoding tree comprises: generating an aggregated vector of differentiating bit scores representing at least a subset of a set of processor instructions; identifying, based on the aggregated vector of differentiating bit scores, one or more opcode bit positions; and constructing a hash table implementing a current level of a decoding tree representing the subset of the set of processor instructions, wherein the hash table is indexed by one or more opcode bits identified by the one or more opcode bit positions.

Abstract: Pre-translated code for an emulated application may be retrieved and executed to translate data from the emulated application into a form compatible with the client device before receiving a request for the emulated application from the client device. The translated data may be delivered to the client device platform over a network after receiving the request for the emulated application from the client device.

Abstract: Examples described herein emulate a processing architecture using multiple translations of the same source binary. A first translation binary includes compiler optimizations not present in a second translation binary. During runtime, a dispatcher directs control flow of a CPU when branch instructions are reached. Specifically, a dispatcher directs a CPU to execute instructions in the first translation binary, and accesses the second translation binary when an instruction is to a target that is not addressable in the first translation binary. The first and second translation binaries enable a target processing architecture to emulate a source processing architecture without just-in-time compilation or other runtime interpretation.

Abstract: Various embodiments include nested emulation for a source application and source emulator. Duplicate source ISA libraries redirect the source emulator library calls to a target library, thereby forcing the native emulator through proper emulation channels between first and second ISAs. Other embodiments concern accelerating dynamic linking by determining certain function calls that, rather than being processed through emulation of PLT code, are instead directly called without the need for PLT code translation. Some embodiments address both nested emulation and accelerated dynamic linking but other embodiments include one of nested emulation and accelerated dynamic linking. Other embodiments are described herein.

Abstract: Techniques are described that enable restoring interrupted program execution from a checkpoint without the need for cooperation from the computer's operating system. These techniques can be implemented by modifying existing code using an automated tool that adds instructions for enabling restoring interrupted program execution.

Abstract: A device may receive an indication to evaluate a first portion of program code and a second portion of program code provided in a first section of a user interface. The device may evaluate the first portion of program code and the second portion of program code. The device may generate a first result corresponding to the first portion of program code and may generate a second result corresponding to the second portion of program code based on evaluating the first portion of program code and the second portion of program code. The device may provide the first result and the second result in a second section of the user interface. The second section may be separate from the first section. The device may provide a correspondence indicator that indicates a correspondence between the first result and the first portion of program code.

Abstract: Examples described herein emulate a processing architecture using multiple translations of the same source binary. A first translation binary includes compiler optimizations not present in a second translation binary. During runtime, a dispatcher directs control flow of a CPU when branch instructions are reached. Specifically, a dispatcher directs a CPU to execute instructions in the first translation binary, and accesses the second translation binary when an instruction is to a target that is not addressable in the first translation binary. The first and second translation binaries enable a target processing architecture to emulate a source processing architecture without just-in-time compilation or other runtime interpretation.

Abstract: An apparatus includes a processor. The processor includes two memories. The first memory stores one set of instructions. The second memory stores another set of instructions that are longer than the set of instructions in the first memory. An instruction in the set of instructions in the first memory is used as a pointer to a corresponding instruction in the set of instructions in the second memory.

Abstract: A data processing device and method are provided. The data processing device includes a code storage unit storing an original code to be translated into a machine language code, a code analyzer analyzing the original code stored in the code storage unit, a register allocator allocating a predesignated register for a command included in the original code based on the result of analysis, and a code executor executing a machine language code generated using the allocated register.

Abstract: A hardware accelerator is used to execute a floating-point byte-code in an information processing device. For a floating-point byte-code, a byte-code accelerator BCA feeds an instruction stream for using a FPU to a CPU. When the FPU is used, first the data is transferred to the FPU register from a general-purpose register, and then an FPU operation is performed. For data, such as a denormalized number, that cannot be processed by the FPU, in order to call a floating-point math library of software, the processing of the BCA is completed and the processing moves to processing by software. In order to realize this, data on a data transfer bus from the CPU to the FPU is snooped by the hardware accelerator, and a cancel request is signaled to the CPU to inhibit execution of the FPU operation when corresponding data is detected in a data checking part.