Abstract: In one embodiment, a processor includes: a plurality of cores each comprising a multi-threaded core to concurrently execute a plurality of threads; and a control circuit to concurrently enable at least one of the plurality of cores to operate in a single-threaded mode and at least one other of the plurality of cores to operate in a multi-threaded mode. Other embodiments are described and claimed.

Abstract: A field programmable gate array (FPGA) including a configurable interconnect fabric connecting a plurality of logic blocks, the configurable interconnect fabric and the logic blocks being configured to implement a data masking circuit configured to: receive input data including data values at a plurality of indices of the input data; select between a data value of the data values and an alternative value using a masking multiplexer to generate masked data, the masking multiplexer being controlled by a mask value of a plurality of mask values at indices corresponding to the indices of the input data; and output the masked data. In some examples, the configurable interconnect fabric and the logic blocks are further configured to implement a mask generation circuit configured to generate the mask values. In some examples, the mask values are received from external memory.

Abstract: A method for executing new instructions is provided. The method is used in a processor and includes: receiving an instruction; when the received instruction is an unknown instruction, executing a conversion program by an operating system, wherein the conversion program executes the following steps: determining whether the received instruction is a new instruction; converting the received instruction into at least one old instruction when the received instruction is a new instruction; and executing the at least one old instruction.

Abstract: Implementing a camouflage of current traces generated by a hardware component having one or more set of digital elements defining a plurality of operational datapaths comprises adjusting (761) one or more working condition(s) of the hardware component, measuring (762) a reaction of the hardware component to the working condition(s) by a logic test circuit through processing data operations along a reference datapath having a minimum duration corresponding to at least the longest of the operational datapaths, and in response to detecting an error (763) along the reference datapath, modifying (764) the working condition(s) so that the error generated by the logic test circuit is cancelled. Applications to countermeasures to side-channel attacks.

Abstract: A system may determine that two instructions may be combined based on a processing power of the processor and a size of the instructions, fuse the two instructions into a pair, map the two instructions with a single register tag, write the register tag into a mapper with bits indicating that the register tag is for a first instruction of the two instructions, write the register tag into the mapper with bits indicating that the register tag is for a second instruction of the two instructions, write the fused instruction pair into an issue queue, issue the fused instruction pair to a vector-scalar transformation units (VSU), and execute the two instructions.

Abstract: A method for storing data in a storage system having solid-state memory is provided. The method includes determining portions of the solid-state memory that have a faster access rate and portions of the solid-state memory that have a slower access rate, relative to each other or to a threshold. The method includes writing data bits of erasure coded data to the portions of the solid-state memory having the faster access rate, and writing one or more parity bits of the erasure coded data to the portions of the solid-state memory having the slower access rate. A storage system is also provided.

Abstract: The technology disclosed herein determining one or more vulnerable instructions in workload code and determining one or more additional instructions to be inserted in the workload code based at least in part on a power model of a system bus of a processor, when a power model of a processor is dependent on an order of instructions of workload code, inserting the one or more additional instructions with dependency to the workload code to produce complementary power consumption of the system bus to power consumption of the system bus from executing the one or more vulnerable instructions; and when the power model is not dependent on the order of instructions of workload code, inserting the one or more additional instructions without dependency to the workload code to produce complementary power consumption of the system bus to power consumption of the system bus from executing the one or more vulnerable instructions.

Abstract: A method for a controller to execute a program comprising a sequence of functions on an accelerator with a pipelined architecture comprising a microcode buffer. The method comprises executing a function of the program as a sequence of operations, wherein the sequence of operations is represented by a sequence of templates, determining whether the template is non-colliding with previously inserted templates in the microcode buffer, determining whether data in local memory will be referenced before all previously inserted templates have taken effect, determining whether registers will be referenced before all previously inserted templates in the microcode buffer have taken effect, when it is determined that the template fits, that resources are available, that local data memory accesses will not collide, and that register accesses will not collide: creating a sequence of microcode instructions in the template, and inserting the template into the microcode buffer.

Abstract: A method for executing new instructions is provided. The method is used in a processor and includes: receiving an instruction; when the received instruction is an unknown instruction, the processor executes the following steps through a conversion program: determining whether the received instruction is a new instruction; and converting the received instruction into at least one old instruction when the received instruction is a new instruction; and simulating the execution of the received instruction by executing the at least one old instruction.

Abstract: A method performed by a solid state drive is described. The method includes, on a channel that internally couples a controller of the solid state drive to a storage device of the solid state drive, sending write data for a program operation to be performed by one of the storage device's logical units in separate chunks over the channel. The method also includes inserting higher priority traffic items of other logical units of the storage device in between the separate chunks.

Abstract: A superscalar processor has a thread mode of operation for supporting multiple instruction execution threads which are full data path wide instructions, and a micro-thread mode of operation where each thread supports two micro-threads which independently execute instructions. An executed instruction sets a micro-thread mode and an executed instruction sets the thread mode.

Abstract: A coprocessor with register renaming is disclosed. An apparatus includes a plurality of processors and a coprocessor respectively configured to execute processor instructions and coprocessor instructions. The coprocessor receives coprocessor instructions from ones of the processors. The coprocessor includes an array of processing elements and a result register set comprising storage elements respectively distributed within the array of processing elements. For a given member of the array of processing elements, a corresponding storage element is configured to store coprocessor instruction results generated by the given member. The result register set implements a plurality of contexts to store respective coprocessor states corresponding to coprocessor instructions received from different processors.

Abstract: A method for executing new instructions is provided. The method is used in a processor and includes: receiving an instruction; when the received instruction is an unknown instruction, executing a conversion program by an operating system, wherein the conversion program executes the following steps: determining whether the received instruction is a new instruction; converting the received instruction into at least one old instruction when the received instruction is a new instruction; and executing the at least one old instruction.

Abstract: Techniques are described for metadata processing that can be used to encode an arbitrary number of security policies for code running on a processor. Metadata may be added to every word in the system and a metadata processing unit may be used that works in parallel with data flow to enforce an arbitrary set of policies. In one aspect, the metadata may be characterized as unbounded and software programmable to be applicable to a wide range of metadata processing policies. Techniques and policies have a wide range of uses including, for example, safety, security, and synchronization. Additionally, described are aspects and techniques in connection with metadata processing in an embodiment based on the RISC-V architecture.

Abstract: The present disclosure includes a feedback framework that receives feedback for a component of an information technology platform. The component includes the feedback framework, the information technology platform, a software application, a web browser, a client device, a client instance, or a virtual server. The feedback framework obtains context information associated with the feedback. The context information includes a system log, a screenshot, a web address of a web browser of the client device, version information, and/or the like. The feedback framework also determines an identity of the component by executing a handler. The feedback framework then determines a notification to send based on the identity of the component, and sends the notification with the feedback and the context information.

Abstract: Disclosed herein are systems and method for instruction tightly-coupled memory (iTIM) and instruction cache (iCache) access prediction. A processor may use a predictor to enable access to the iTIM or the iCache and a particular way (a memory structure) based on a location state and program counter value. The predictor may determine whether to stay in an enabled memory structure, move to and enable a different memory structure, or move to and enable both memory structures. Stay and move predictions may be based on whether a memory structure boundary crossing has occurred due to sequential instruction processing, branch or jump instruction processing, branch resolution, and cache miss processing. The program counter and a location state indicator may use feedback and be updated each instruction-fetch cycle to determine which memory structure(s) needs to be enabled for the next instruction fetch.

Abstract: The technology disclosed relates to runtime execution of configuration files on reconfigurable processors with varying configuration granularity. In particular, the technology disclosed relates to a runtime logic that is configured to receive a set of configuration files for an application, and load and execute a first subset of configuration files in the set of configuration files and associated application data on a first reconfigurable processor. The first reconfigurable processor has a first level of configurable granularity. The runtime logic is further configured to load and execute a second subset of configuration files in the set of configuration files and associated application data on a second reconfigurable processor. The second reconfigurable processor has a second level of configurable granularity that is different from the first level of configurable granularity.

Abstract: An apparatus comprises capability checking circuitry 86 to perform a capability validity checking operation to determine whether use of a capability satisfies one or more use-limiting conditions. The capability comprises a pointer and pointer-use-limiting information specifying the one or more use-limiting conditions. The one or more use-limiting conditions comprise at least an allowable range of addresses for the pointer. In response to a capability write request requesting that a capability is written to a memory location associated with a capability write target address, when capability write address tracking is enabled, capability write address tracking circuitry 200 updates a capability write address tracking structure 100 based on the capability write target address.

Abstract: Techniques for system recovery using a failover processor are disclosed. A first processor, with a first instruction set, is configured to execute operations of a first type; and a second processor, with a second instruction set different from the first instruction set, is configured to execute operations of a second type. A determination is made that the second processor has failed to execute at least one operation of the second type within a particular period of time. Responsive to determining that the second processor has failed to execute at least one operation of the second type within the particular period of time, the first processor is configured to execute both the operations of the first type and the operations of the second type.

Abstract: A method of an escape reorder mode for neural network model compression, is performed by at least one processor, and includes determining whether a frequency count of a codebook index included in a predicted codebook is less than a predetermined value, the codebook index corresponding to a neural network. The method further includes, based on the frequency count of the codebook index being determined to be greater than the predetermined value, maintaining the codebook index, and based on the frequency count of the codebook index being determined to be less than the predetermined value, assigning the codebook index to be an escape index of 0 or a predetermined number. The method further includes encoding the codebook index, and transmitting the encoded codebook index.

Abstract: The present disclosure provides a chip fault diagnosis method, which includes: determining an interrupt flag of an interrupt flag register based on first data identifying an interrupt state in the interrupt flag register; and determining a fault state of chip interrupt corresponding to the interrupt flag based on the interrupt flag. By adopting the technical solution provided by the present disclosure, a fault of the interrupt can be diagnosed in time, and the interrupt can be processed in time.

Abstract: A method of converting a data stored in a memory from a first format to a second format is disclosed. The method includes extending a number of bits in the data stored in a double data rate (DDR) memory by one bit to form an extended data. The method further includes determining whether the data stored in the DDR is signed or unsigned data. Moreover, responsive to determining that the data is signed, a sign value is added to the most significant bit of the extended data and the data is copied to lower order bits of the extended data. Responsive to determining that the data is unsigned, the data is copied to lower order bits of the extended data and the most significant bit is set to an unsigned value, e.g., zero. The extended data is stored in an on-chip memory (OCM) of a processing tile of a machine learning computer array.

Abstract: Techniques are described for metadata processing that can be used to encode an arbitrary number of security policies for code running on a processor. Metadata may be added to every word in the system and a metadata processing unit may be used that works in parallel with data flow to enforce an arbitrary set of policies. In one aspect, the metadata may be characterized as unbounded and software programmable to be applicable to a wide range of metadata processing policies. Techniques and policies have a wide range of uses including, for example, safety, security, and synchronization. Additionally, described are aspects and techniques in connection with metadata processing in an embodiment based on the RISC-V architecture.

Abstract: Techniques for signal handling between programs associated with different addressing modes in a computer system are described herein. An aspect includes, based on a signal occurring during execution of a first program in a first runtime environment, wherein the first program and the first runtime environment are associated with a first addressing mode, invoking a first signal exit routine associated with the first addressing mode. Another aspect includes allocating a signal information area (SIA) by the first signal exit routine. Another aspect includes calling a second signal exit routine associated with a second addressing mode that is different from the first addressing mode with an address of the SIA. Another aspect includes allocating a mirror SIA by the second signal exit routine. Another aspect includes handling the signal, and resuming execution based on the handling of the signal.

Abstract: A simulation method and a simulation system are provided. The simulation system may be divided into an execution model and a processor model based on a JIT emulation engine. The execution model can call the JIT emulation engine to execute instructions, and obtain influence of instructions on a processor architectural status. The processor model may simulate an internal process of a target processor and determine whether to start/end a speculation. The execution model and the processor model may interact through a specific protocol. After the speculation is started, the simulation method may store an application running scene when the speculation is started, and redirect influence of speculation instructions on a memory to a memory snapshot. After the speculation is ended, the simulation method may also restore the application running scene to a status before the speculation is started, and cancel influence of the speculation instructions on the memory.

Abstract: An integrated circuit such as, for example a graphics processing unit (GPU), includes a dynamic power controller for adjusting operating voltage and/or frequency. The controller may receive current power used by the integrated circuit and a predicted power determined based on instructions pending in a plurality of processors. The controller determines adjustments that need to be made to the operating voltage and/or frequency to minimize the difference between the current power and the predicted power. An in-system reinforced learning mechanism is included to self-tune parameters of the controller.

Abstract: An instruction execution method includes the following steps: translating a macro-instruction into a first micro-instruction and a second micro-instruction, and marking first binding information on the first micro-instruction, and marking second binding information on the second micro-instruction; and simultaneously retiring the first micro-instruction and the second micro-instruction according to the first binding information and the second binding information. The first micro-instruction and the second micro-instruction are adjacent to one another in the micro-instruction storage space.

Abstract: Methods, apparatus and computer program products are provided for the visualization of software execution. One method comprises: generating, using a static code analysis, a data flow diagram illustrating a plurality of possible code execution paths of software code; marking, using an execution profiler, a particular execution path through the data flow diagram for a specific execution scenario; and enriching one or more nodes in the data flow diagram marked with the particular execution path for the specific execution scenario with information extracted from one or more application logs. The marked data flow diagram may be enriched, for example, by extracting a particular portion of a log file and tagging a corresponding portion of the data flow diagram with the extracted particular portion of the log file. The extracted log information may comprise, for example, a timestamp, a log category, a software module name, a function name and/or contextual information.

Abstract: A non-volatile memory device having at least one non-volatile flash memory formatted with physical addresses to read and write data that is organized into blocks of data, wherein the blocks of data are organized into pages of data, and wherein the pages of data are organized into cells of data. The non-volatile memory device includes a non-volatile memory controller to direct read and write requests to the non-volatile flash memory for the storage and retrieval of data. The non-volatile memory controller includes a flash translation layer to correlate read and write requests for data having a logical address between the reading and writing the data to physical address location of the non-volatile flash memory. The flash translation layer, when writing to a physical address location, chooses between a wear-leveling circuit and a wear-limiting circuit to select the physical address location.

Abstract: In accordance with embodiments of the invention, a set of Microinstructions define a set of primitives or instructions to execute a business process modeling language in accordance with the semantics defined by the language. The Microinstructions define atomic operations that can be executed as part of a running process. The Microinstructions can be combined into Microprograms which map to business processes of the business process modeling language, for example BPMN. The Microprograms can be compiled using a suitable compiler into any execution language. The Microinstructions thereby provide flexibility for executing business process modeling languages in any business process execution language.

Abstract: A microcontroller is provided and includes a reset pin, a reset circuit, and a first logical circuit. A first reset signal is generated at the reset pin when the microcontroller is powered on. The reset circuit receives the first reset signal and generates a second reset signal. The reset circuit includes a plurality of flipflops. After the microcontroller is powered on, the reset circuit switches a state of the second reset signal according to the first reset signal when an output combination of a plurality of output values of the plurality of flipflops is not a specific value. The first logical circuit performs a first initialization operation when the state of the second reset signal is switched. When the second reset signal is switched, the reset circuit sets the output combination of the plurality of output values of the plurality of flipflops to the specific value.

Abstract: A multi-branch determination syntax optimization apparatus includes: a memory that retains multi-branch determination syntax including tokens; a database that retains (1) CPU performance information being a parameter depending on a CPU incorporated in the multi-branch determination syntax optimization apparatus and set based on time required for multi-branch determination processing and (2) frequently-appearing token table representing types and rates of appearance of tokens sorted in order of appearance frequency in a query that statically analyzes a source code and performs lexical analysis in advance; and a conversion section that executes determination for the multi-branch determination syntax by referring to the CPU performance information and the frequently-appearing token table, and creates a branch code converted to make a speculatively executable branch for the token type having a high frequency of appearance and to make a branch using the jump table for the token type having a low frequency of appea

Abstract: A method, tangible computer-readable medium and apparatus for concurrently executing subsystems in a graphical model is provided. An embodiment can transform a conventional graphical model supporting single threaded execution into a model supporting multi-threaded execution through the replacement of a single block. The transformed model may support concurrent execution of a plurality of subsystems using a plurality of threads when the graphical model executes. An embodiment provides a user interface that allows a user to intuitively configure a model for current execution of the subsystems.

Abstract: A circuit arrangement and method support compression and expansion of instruction opcodes by detecting successive address targeting and decoding a first opcode of an instruction into a second opcode in response to detecting successive address targeting. The circuit arrangement and method execute instructions in an instruction stream and detect successive address targeting by two or more instructions in the instruction stream without the targeted address being utilized as a source address in an instruction executed between the first and second instructions in the instruction stream. Then, based on that detection, the opcode of the second instruction is modified, changed, or appended to such that a different opcode is indicated by the second instruction, such that executing the second instruction causes a different unique type of operation to be performed.

Abstract: A method, apparatus, and program product execute instructions of an instruction stream and detect logically non-significant operations in the instruction stream. Then, based on that detection, a target or source address of a subsequent instruction is adjusted. In some instances, doing so enables a greater number of addresses, e.g., registers, to be accessed in a given number of bit positions within an instruction format.

Abstract: A microcontroller includes a plurality of primary registers, a secondary register and a central processing unit (CPU). The primary registers store a plurality of primary data respectively. Each primary data has a first width. The secondary register includes the plurality of primary registers and stores a secondary data having a second width. The secondary data includes a combination of the plurality of primary data. The CPU executes a first instruction in a first mode in which a primary data is fetched for operation and executes a second instruction in a second mode in which the secondary data is fetched for operation.

Abstract: A data processing device and method are provided. The data processing device includes a code storage unit storing an original code to be translated into a machine language code, a code analyzer analyzing the original code stored in the code storage unit, a register allocator allocating a predesignated register for a command included in the original code based on the result of analysis, and a code executor executing a machine language code generated using the allocated register.