Abstract: An aspect includes a plurality of throttle controllers having a modular hierarchy comprising a plurality of levels within each of a plurality of processor cores that control a plurality of throttling actions. The throttling actions include dynamic adjustment of execution suspension within the processor cores. A plurality of input throttle events at each of the processor cores is resolved based on the modular hierarchy. A chip controller coupled to the processor cores can synchronize the throttling actions between the processor cores.

Abstract: The invention relates to a controller (1) comprising a control unit (2), which communicates with at least one input and/or output unit (10) via a data transmission channel (3, 6) for exchange of process data (P). The controller (1) has predetermined power saving process data (V) for power-saving states (En), which are associated with the input/output units (10), and is designed to access the predetermined power-saving process data (V) instead the exchanged process data (P) when in the power saving state.

Abstract: In an embodiment, a processor includes a schedule logic to schedule a set of instructions for execution in an execution logic of the processor and a power analysis logic having a first calculation logic to calculate a maximum dynamic capacitance for at least a portion of the processor and a second calculation logic to calculate a dynamic capacitance estimate for execution of the set of instructions. A rescheduling of the set of instructions may occur based on a comparison of the dynamic capacitance estimate and the maximum dynamic capacitance. Other embodiments are described and claimed.

Abstract: Described herein are a method and a system for smart power management in electronic devices. Specifically, an electronic device with multiple processors is designed for fitness and health monitoring of a subject. When the device receives a task, it determines whether the task is high power consuming. In response to the determining that the task is high power consuming; the device enables a high-speed processor for the task. Otherwise the device enables a low-speed processor to perform the task.

Abstract: In one embodiment, a processor includes at least one core to execute instructions and a power control logic to receive power capability information from a plurality of devices to couple to the processor and allocate a platform power budget to the devices, set a first power level for the devices at which the corresponding device is allocated to be powered, communicate the first power level to the devices, and dynamically reduce a first power to be allocated to a first device and increase a second power to be allocated to a second device responsive to a request from the second device for a higher power level. Other embodiments are described and claimed.

Abstract: Embodiments of a method that allow the adjustment of performance settings of a computing system are disclosed. One or more functional units may include multiple monitor circuits, each of which may be configured to monitor a given operational parameter of a corresponding functional unit. Upon detection of an event related to a monitored operational parameter, a monitor circuit may generate an interrupt. In response to the interrupt a processor may adjust one or more performance settings of the computing system.

Abstract: Methods, systems, and apparatus, including computer programs encoded on a computer storage medium, for reducing processor latency through the use of dedicated cores. In one aspect, a method includes a multi-core processor having n cores, including, selecting k cores of the n cores of the multi-core processor to perform dedicated low-latency operations for the n-core processor, where k is less than n, m cores are unselected, and each core of the multi-core processor has a rated core capacity. The methods operate the selected k cores at less than the rated core capacity such that k cores are collectively underutilized by an underutilized capacity and operate one or more of the m cores at a capacity in excess of the rated core capacity such that the m cores operate at a collective capacity that exceeds a collective capacity of the rated core capacities of the m cores.

Abstract: A technique of processing instructions for execution by a processor includes determining whether a first property of a first instruction and a second property of a second instruction are compatible. The first instruction and the second instruction are grouped in an instruction group in response to the first and second properties being compatible and a feedback value generated by a feedback function indicating the instruction group has been historically beneficial with respect to a benefit metric of the processor. Group formation for the first and second instructions is performed according to another criteria, in response to the first and second properties being incompatible or the feedback value indicating the grouping of the first and second instructions has not been historically beneficial.

Abstract: A processor is provided having a common supply rail, and one or more processor cores, where the one or more processor cores share the common supply rail. Each processor core(s) includes a core dIPC value output and a core throttling signal input, and a chip power management logic, which has at least one input for inputting the core dIPC value, a threshold register for a dIPC threshold value, a chip dIPC register for a current global dIPC value, at least one chip dIPC history register for a historic global dIPC value, a subtractor providing an absolute difference of an average historic global dIPC derived from the historic global dIPC value and the current global dIPC value, a magnitude comparator providing a throttling signal when the absolute difference is above the dIPC threshold value, and at least one output for outputting a core throttling signal to the processor core(s).

Abstract: In one embodiment, the present invention includes a processor having multiple cores to independently execute instructions, a first sensor to measure a first power consumption level of the processor based at least in part on events occurring on the cores, and a hybrid logic to combine the first power consumption level and a second power consumption level. Other embodiments are described and claimed.

Abstract: A system includes a power management unit that may monitor the power consumed by a processor including a plurality of processor core. The power management unit may throttle or reduce the operating frequency of the processor cores by applying a number of throttle events in response to determining that the plurality of cores is operating above a predetermined power threshold during a given monitoring cycle. The number of throttle events may be based upon a relative priority of each of the plurality of processor cores to one another and an amount that the processor is operating above the predetermined power threshold. The number of throttle events may correspond to a portion of a total number of throttle events, and which may be dynamically determined during operation based upon a proportionality constant and the difference between the total power consumed by the processor and a predetermined power threshold.

Abstract: A processor for processing loop instructions can include an instruction reorder structure and a loop processing controller. The instruction reorder structure is configured to store decoded instructions according to program order and issue the decoded instructions for execution out of program order. The loop processing controller is configured to detect a loop in the decoded instructions stored in the instruction reorder structure and cause the instruction reorder structure to reissue the decoded instructions that form the loop for re-execution.

Abstract: A system and method for reducing power consumption through issue throttling of selected problematic instructions. A power throttle unit within a processor maintains instruction issue counts for associated instruction types. The instruction types may be a subset of supported instruction types executed by an execution core within the processor. The instruction types may be chosen based on high power consumption estimates for processing instructions of these types. The power throttle unit may determine a given instruction issue count exceeds a given threshold. In response, the power throttle unit may select given instruction types to limit a respective issue rate. The power throttle unit may choose an issue rate for each one of the selected given instruction types and limit an associated issue rate to a chosen issue rate. The selection of given instruction types and associated issue rate limits is programmable.

Abstract: An apparatus includes a processor. The processor includes two memories. The first memory stores one set of instructions. The second memory stores another set of instructions that are longer than the set of instructions in the first memory. An instruction in the set of instructions in the first memory is used as a pointer to a corresponding instruction in the set of instructions in the second memory.

Abstract: A method for reducing the number of load instructions in the load reorder queue (LRQ) that are searched when a load instruction is executed by a processor, including dispatching the load instructions; inserting the load instructions in the LRQ in program order; clearing a load received data field; executing the load instructions; checking load reorder queue (LRQ) entries; re-executing the load instruction of the matching LRQ entry; continuing execution; getting the load data; setting the load received data field; comparing a load sequence number (LSQN) of each load instruction to a snoop_safe register contents; ANDing all the load received data bits if the LSQN is greater in magnitude to the snoop_safe; setting the snoop_safe register to the LSQN of the load instruction; searching the LRQ entry; and setting a load_peril_snoop register to the LRQ index value where the first load instruction younger to the snoop_safe was found.

Abstract: A method for reducing entries searched in a load reorder queue (LRQ) when snoop instructions are executed by a processor, including checking load reorder queue (LRQ) entries located between a load_peril_snoop register and a lrq_tail register for addresses matching the address of the snoop; and setting a snooped bit in the LRQ entry for any matches found.

Abstract: In one embodiment, a processor comprises a retire unit and a load/store unit coupled thereto. The retire unit is configured to retire a first store memory operation responsive to the first store memory operation having been processed at least to a pipeline stage at which exceptions are reported for the first store memory operation. The load/store unit comprises a queue having a first entry assigned to the first store memory operation. The load/store unit is configured to retain the first store memory operation in the first entry subsequent to retirement of the first store memory operation if the first store memory operation is not complete. The queue may have multiple entries, and more than one store may be retained in the queue after being retired by the retire unit.

Abstract: A method and system for processing out of order frames received by a host bus adapter is provided. The method includes, determining if a current frame is out of order; determining if a frame is within a range of transfer for an Exchange; and creating (or appending if not the first out-of-order frame) an out of order list if the current frame is a first out of order frame. The method also includes, determining if an entry in an out of order list has a relative offset value of zero; determining if at least one entry has a relative offset value equal to a total transfer length of an Exchange; and determining if every non-zero starting relative offset has a matching entry. The method also scans an out of order list and combines a last entry with an entry whose starting point matches the end point of the last entry.