Using Static Prediction, E.g., Branch Taken Strategy (epo) Patents (Class 712/E9.052)
  • Patent number: 12067399
    Abstract: A processor may include a bias prediction circuit and an instruction prediction circuit to provide respective predictions for a conditional instruction. The bias prediction circuit may provide a bias prediction whether a condition of the conditional instruction is biased true or biased false. The instruction prediction circuit may provide an instruction prediction whether the condition of the conditional instruction is true of false. Responsive to a bias prediction that the condition of the conditional instruction is biased true or biased false, the processor may use the bias prediction from the bias prediction circuit to speculatively process the conditional instruction. Otherwise, the processor may use the instruction prediction from the instruction prediction circuit to speculatively process the conditional instruction.
    Type: Grant
    Filed: February 1, 2022
    Date of Patent: August 20, 2024
    Assignee: Apple Inc.
    Inventors: Ian D Kountanis, Douglas C Holman, Wei-Han Lien, Pruthivi Vuyyuru, Ethan R Schuchman, Niket K Choudhary, Kulin N Kothari, Haoyan Jia
  • Patent number: 11593185
    Abstract: A processing system comprising multiple tiles and an interconnect between the tiles. The interconnect is used to communicate between a group of some or all of the tiles according to a bulk synchronous parallel scheme, whereby each tile in the group performs an on-tile compute phase followed by an inter-tile exchange phase with the exchange phase being held back until all tiles in the group have completed the compute phase. Each tile in the group has a local exit state upon completion of the compute phase. The instruction set comprises a synchronization instruction for execution by each tile upon completion of its compute phase to signal a sync request to logic in the interconnect. In response to receiving the sync request from all the tiles in the group, the logic releases the next exchange phase and also makes available an aggregated a state of all the tiles in the group.
    Type: Grant
    Filed: November 19, 2019
    Date of Patent: February 28, 2023
    Assignee: GRAPHCORE LIMITED
    Inventors: Simon Christian Knowles, Alan Graham Alexander