Abstract: A reference signal input of a delay locked loop is connected to receive a reference clock. The delay locked loop provides a drive clock that drives a clock distribution tree. One of the endpoints of the clock distribution tree is connected to a feedback reference of the delay locked loop. By using one the endpoints as a feedback loop to the delay locked loop the signal received at components attached to the endpoints of the distribution tree can be synchronized to the reference input received at the delay locked loop.

Abstract: A processor executes image processing under control of a clock facility, such that a sequence of C effective clock cycles will effect a processing operation of a predetermined amount of image information. In particular, the processor has programming means for implementing programmable stall clock cycles interspersed between the effective clock cycles for implementing a programmable slowdown factor S, such that a modified number of C*S overall clock cycles will effect processing of the predetermined amount of digital signal information.

Abstract: A real-time power conservation and thermal management apparatus and method for portable computers employs a monitor (40) to determine whether a CPU may rest based upon a real-time sample of the CPU activity and temperature levels and to activate a hardware selector(500, 510, 520, 530) to carry out the monitor's determination. If the monitor determines the CPU may rest, the hardware selector reduces CPU clock time (280); if the CPU is to be active, the hardware selector returns the CPU to its previous high speed clock level (330). Switching back into full operation from its rest state occurs without a user having to request it and without any delay in the operation of the computer while waiting for the computer to return to a “ready” state. Furthermore, the monitor adjusts the performance level of the computer to manage power conservation and thermal management in response to the real-time sampling of CPU activity (10) and temperature (24).

Abstract: A technique for compensating for duty cycle distortion in an output data signal generated by a synchronous dynamic random access memory device (SDRAM) is provided. The output latch of the SDRAM is driven by an output clock signal generated by a delay lock loop (DLL). The output clock signal is phase-shifted relative to a reference clock signal received by the DLL such that the data removed from the output latch is synchronous with the reference clock signal. Further the duty cycle of the output clock signal is adjusted in a phase inverse relationship to the duty cycle distortion introduced by the output latch. As a result, the output data signal has reduced duty cycle distortion.

Abstract: A method includes maintaining an indication of a pending event with respect to each of a number of threads supported within a multithreaded processor. An indication is also maintained of an active or inactive state for each of the multiple threads. A clock disable condition is detected. This clock disable condition may be indicated by the absence of pending events with respect to each of the multiple threads and an inactive state for each of the multiple threads. A clocks signal, if enabled, is then disabled with respect to at least one functional unit within the multithreaded processor responsive to the detection of the clock disable condition.

Abstract: A chipset to support multiple CPU's and a layout method thereof. Those independent signal lines for delivering high frequency clock signals of the chipset are isolated from using by other signals without being multiplexed. Trace length of the independent signal line is shorter than that of the others. The spaces between the independent signal line and others are also larger than that between other signal lines. Signal transmission quality is significantly upgraded because the high frequency clock signal is not multiplexed and isolated from others.

Abstract: The processor, upon fetching a sleep command, stops its own operation and outputs an internal power-down signal. The power-down control circuit outputs, upon receiving the internal power-down signal from the processor, a control signal to put a volatile semiconductor memory connected to the system bus into a self refresh mode. Thus, the processor can simply fetch the sleep command to put the semiconductor memory into the self refresh mode. Since system programs need not include any processing program for putting the semiconductor memory into the self refresh mode, the software processing can be prevented from being complicated. As a result, it is possible to reduce the burden on the program developers.

Abstract: An interface between synchronous and asynchronous data transfer includes a plurality of stages coupled to each other to form a pipeline for data transfer. The plurality of stages include a first stage which performs synchronous to asynchronous data transfer, at least one intermediate stage which performs asynchronous to asynchronous data transfer and a last stage which performs asynchronous to synchronous data transfer. A synchronous clock path propagates a timing signal across the plurality of stages to enable the first and last stages to perform operations when the timing signal is present at that stage.

Abstract: An IC card having a storage memory including a program storage unit for storing a program and a data storage unit for storing data and a central processing unit for executing a predetermined process in accordance with the program to process the data, the program including one or more data process units each having a process instruction for giving an execution instruction to the central processing unit, wherein a data process order is randomly exchanged and a dummy process is added to thereby reduce the dependency of consumption current of an IC chip upon the data process.

Abstract: The present invention relates to a technique for accessing memory units in a data processing apparatus. The data processing apparatus comprises of plurality of memory units for storing data values, a processor core for issuing an access request specifying an access to be made to the memory units in relation to a data value, and a memory controller for performing the access specified by the access request. Attribute generation logic is provided for determining from the access request one or more predetermined attributes verifying which of the memory units should be used when performing the access. However, the memory controller does not wait until such determination has been performed by the attribute generation logic before beginning the access.

Abstract: Method of compensating for a delay between clock signals for a semiconductor integrated circuit having a plurality of devices synchronous to a plurality of clock signals, including the steps of (1) searching for devices between which a data transmission path is set up synchronous to different clock signals among the plurality of devices, and (2) adding a plurality of delays only to between the devices having the data transmission path set up therebetween for compensating for the delay coming from a difference of clock signals, whereby solving non-uniformity of clock signals by using a small number of delays.

Abstract: In a memory controller, a serial data including an instruction bit train with addition of a start bit, a clock signal, a chip enable signal, and a reset signal are inputted. During the active period in which the chip enable signal is being inputted, the serial data is stored depending on the clock signal and an enabling signal is generated based on the end timing of active period. Thereby, memory access is executed depending on contents of the instruction bit train. However, when the relevant apparatus is reset during the active period, generation of the enabling signal based on the end timing of the active period is inhibited.

Abstract: A clock generation circuit for generating clocks having a plurality of frequencies by which a suitable frequency for each task can be supplied such that the power consumption is reduced. A clock generation unit is provided for generating a clock with a constant frequency, with a counter operating in synchronization with the clock for counting pulses of the clock, a comparator for comparing a counter value of the counter with the number of pulses of a clock having a desired frequency, and an output gate for controlling the supply and stopping of pulses of the clock input from the clock generation unit based on a comparison result of the comparator.

Abstract: An efficient clock start and stop apparatus for clock forwarded system I/O. The apparatus may include a buffer coupled to receive incoming data from a data source. The buffer is clocked by a first clock signal that is provided by the data source. The buffer is configured to store the incoming data in a plurality of sequential lines in response to the first clock signal. The buffer may be further configured to store a plurality of bits in a plurality of occupied-bit registers. Each one of the plurality of occupied-bit registers indicates that data is present in a corresponding sequential line in the buffer. The apparatus may further include a clock gate circuit coupled to the buffer and configured to provide a second clock signal. The clock gate circuit may be further configured to start the second clock signal when valid data is present in the buffer and to stop the second clock signal when no data is present in the buffer.

Abstract: A coupling circuit for coupling a data signal from a first clock domain defined by a first clock signal to a second clock domain defined by a second clock signal. A phase comparator determines whether the first clock signal leads the second clock signal. If so, the data signal is clocked from the first clock domain at a time after a start signal that is later than if the clock signal does not lead the second clock signal. Alternatively, if the first clock signal leads the second clock signal, the data signal may be clocked to the second clock domain at a time after a start signal that is earlier than if the clock signal does not lead the second clock signal.

Abstract: A data processing device formed in a single semiconductor chip. The data processing device includes an electronic processor, and on-chip peripheral circuitry ordinarily operative together. Further included, are means for selectively entering externally supplied data into the electronic processor and on-chip peripheral circuitry, for starting and stopping operations of the electronic processor and the on-chip peripheral circuitry independently of each other in an emulation mode of operation.

Abstract: A clock signal generating circuit includes an oscillator portion that sustains a ramped oscillating clock signal in a memory storage device electrically connected to the oscillator portion, a switch portion that supplements electrical energy to the oscillator portion, and a cycle controller connected to the oscillator portion and the switch portion to supplement energy to the oscillator portion when a peak voltage or current level of the clock signal falls below a predetermined value.

Abstract: A clock controller and clock generating method are provided for AC self-test timing analysis of a logic system. The controller includes latch circuitry which receives a DC input signal at a data input, and a pair of continuous out-of-phase clock signals at capture and launch clock inputs thereof. The latch circuitry outputs two overlapping pulses responsive to the DC input signal going high. The two overlapping pulses are provided to waveform shaper circuitry which produces therefrom two non-overlapping pulses at clock speed of the logic system to be tested. The two non-overlapping pulses are a single pair of clock pulses which facilitate AC self-test timing analysis of the logic system.

Abstract: A processor, comprising a monitor for, depending on the respective embodiment, measuring the relative amount of idle time, activity time, or idle time and activity time within the processor, results of the measuring being used by the processor for controlling a clock speed of the processor. Yet other embodiments disclose, depending upon the respective embodiment, a processor, comprising a monitor for measuring the relative amount of idle time, activity time or idle time and activity time within the processor, results of the measuring being used by the processor to control power dissipation associated with the processor.

Abstract: A method and apparatus for controlling processor clock rates of a synchronous multi-processor system in response to an environmental condition of a processor. In one embodiment, a processor-reported an environmental condition is stored in a register and all processors are interrupted simultaneously. Upon interrupt, each processor reads the contents of the register and responds by adjusting its local clock rate synchronously with the other processors. In another embodiment, the processor's environmental status is polled by software control. Upon notification of an environmental condition, the software control notifies each processor to adjust its local clock rate synchronously with the other processors.

Abstract: An integrated circuit chip that receives data on an asynchronous communications bus from an external device and receives data from asynchronous internal device is capable of switching from synchronous operation to asynchronous operation without any loss of data. The chip does not switch off the system clock while there is activity on the communications bus. Additionally, the communications bus has a minimum event time greater than the time fo one and a half cycles of the system clock plus enough timing margin for an asynchronous update to occur.

Abstract: A method and related system for transferring data between systems having different clock domains. A skip signal generation circuit calculates substantially simultaneously with the transfer of data which signals of the faster clock domain should be skipped to ensure proper operation. The skip signal generation circuit makes this determination using values representing the faster and slower frequencies of each clock domain. These values are obtained either from preset values integrated in some form onto the microprocessor substrate, or may be written to the microprocessor by external circuitry and software. The skip signal generation circuit is capable of calculating skip patterns for any ratio of faster to slower frequency and is not constrained to have integer or half-integer ratios of the faster and slower clock domains.

Abstract: A controller and a control method of an integrated memory provided in a system LSI used in television receiver or other video appliance are disclosed. In the memory controller of the invention, when a clock signal suspend command signal not synchronized with a synchronization signal is entered, a suspend command signal synchronized with the synchronization signal is generated. The clock signal supplied in the integrated memory is suspended according to a synchronized suspend command signal. Since the clock signal supply is suspended only while the integrated memory is in idling state, the power consumption of the system LSI can be saved without breaking down the integrated memory.

Abstract: A microcomputer malfunction preventive apparatus that halts supplying of a clock signal to a microcomputer when fluctuations in a supply voltage deviate from an acceptable range, and resumes supplying of the clock signal to the microcomputer when the fluctuations return to the acceptable range.

Abstract: A timer processing section 10 instructs a transmission processing section 11 to control load in accordance with a time schedule stored in a program storage section 12. The transmission processing section 11 is connected to a two-wire signal line and gives a load control instruction to each terminal to which load is connected according to a time-division multiplex transmission system. The time schedule stored in a program storage section 12 is a set of the address related to the load to be controlled and the control contents and the control time of the load. Therefore, when the time set according to the time schedule is reached, the load specified by the address is controlled.

Abstract: According to one embodiment, a computer system is disclosed. The computer system includes a first clock receiver, one or more clock traces coupled to the clock generator, and clock generator coupled to the one or more clock traces. The clock generator gates clock signals to the first clock receiver in response to detecting that the clock traces have been disconnected from electrical ground.

Abstract: A processor, comprising a monitor for measuring the relative amount of Input/Output (I/O) within the processor, results of the measuring being used by the processor for controlling a clock speed of the processor. Another embodiment discloses a processor, comprising a monitor for measuring the relative importance of Input/Output (I/O) within the processor, results of the measuring being used by the processor for controlling a clock speed of said processor. Still another embodiment discloses a processor, comprising a monitor for measuring the relative amount of time between Input/Output (I/O) within the processor, results of the measuring being used by the processor for controlling a clock speed of the processor.

Abstract: A method and apparatus for limiting a processor clock frequency includes an overclocking prevention circuit. The overclocking prevention circuit includes a frequency limiting circuit having programmable fusible elements. The frequency limiting circuit outputs a signal identifying a maximum processor clock frequency based on the state of each of the fusible elements. A comparator circuit compares a selected processor clock frequency to the maximum processor clock frequency to determine if the selected processor clock frequency is permitted. If the selected processor clock frequency is not permitted, then the processor is not allowed to operate at the selected clock frequency.

Abstract: A high-speed pipeline device includes n data path circuits connected in cascade between an input terminal and an output terminal. N data passing circuits have transmission times {T1, . . . , Tn} each less than a period P of a reference clock signal, at least one of the transmission times differing from another. N pipe registers connect to the input terminals of the data path circuits to latch data passed from a previous stage or the input terminal. A control signal generating circuit produces n pipeline control signals in response to the reference clock signal. N−1 of the pipeline control signals are generated in cascade from preceding pipeline control signals, and an (n)th pipeline control signal is generated directly from the reference clock signal. The control signal generating circuit provides the n pipeline control signals to the n pipe register, so that the total transmission time from the input terminals to the output terminals is minimal.

Abstract: A circuit and method for stopping a clock tree while maintaining PLL lock. A clock circuit includes a locked loop circuit and a clock tree distribution network. The locked loop circuit receives an input clock signal and generates a PLL output clock depending upon a feedback signal. The clock tree is coupled to the locked loop circuit and conveys the PLL output clock to a plurality of clocked circuit elements. The clock circuit further includes a gating circuit and a feedback delay circuit. The gating circuit is coupled between the locked loop circuit the clock tree distribution network and selectively inhibits the PLL output clock from clocking the clock tree distribution network. The feedback delay circuit provides the feedback signal, which represents a delayed version of the PLL output clock, during operation including when the gating circuit inhibits the PLL output clock from clocking the clock tree.

Abstract: The invention provides a method of automatically overclocking CPUs for a computer system by using a frequency generator with functions of tuning frequency and monitoring, and applying a numeric method to get the frequency for booting a computer system. When a computer system is powered on and enters the overclocking process, the built-in parameters storing booting settings are loaded and backed up to be referenced in the next trial of booting. The frequency of overclocking is calculated by a numeric method according to the highest frequency generated by the frequency generator and the frequency of front side bus of the system. The built-in parameters are then stored to boot up a computer system at next time. Once the configuration of the computer system is changed, the values of parameters are invalid and need to be recalculated by entering the overclocking process. Using this automatic method, overclocking can be done in a shorter time than overclocking manually.

Abstract: In a clock management apparatus for a synchronous network system, when the quality of a clock signal is deteriorated, the clock signal is switched to another clock signal automatically to continue synchronous communication. Clock signals are received and extracted by transmission/receiving units of the synchronous network system. A plurality of clock signals including the extracted clock signals and a clock signal from an external clock are selectively switched by a clock switching unit, and a master clock signal is selected and output based on quality information transferred with each clock signal. The master clock signal is applied to a clock generator generate a clock signal. A quality control table is used to convert quality information into associated quality levels. A quality determination processing unit issues an alarm when the quality level of the master clock signal is deteriorated beyond a threshold provided by a synchronization management table.

Abstract: A multithread pipelined instruction decoder to clock, clear and stall an instruction decode pipeline of a multi-threaded machine to maximize performance and minimize power. A shadow pipeline shadows the instruction decode pipeline maintaining a the thread-identification and instruction-valid bits for each pipestage of the instruction decoder. The thread-id and valid bits are used to control the clear, clock, and stall of each pipestage of the instruction decoder. Instructions of one thread can be cleared without impacting instructions of another thread in the decode pipeline. In some cases, instructions of one thread can be stalled without impacting instructions of another thread in the decode pipeline. In the present invention, pipestages are clocked only when a valid instruction needs to advance in order to conserve power and to minimize stalling.

Abstract: A microcomputer comprises a selecting unit for selecting one of a plurality of clock signals generated by a plurality of clock generating sources according to a selection instruction from a central processing unit or CPU, a clock generation stop unit, responsive to a stop instruction to stop generation of a clock signal other than the selected clock signal from the CPU, for causing a corresponding clock generating source to stop the generation of the clock signal, and an unauthorized stop process detecting unit, responsive to a stop instruction to stop the generation of the selected clock signal from the CPU, for determining that the CPU has provided an instruction to perform an unauthorized process of causing a selected clock generating source to stop the generation of the selected clock signal.

Abstract: A microcomputer with a built-in flash memory includes a flash controller for controlling writing/erasing of the flash memory in accordance with a command from a CPU. The flash controller produces a CPU rewriting mode designating signal and a busy signal during writing/erasing of the flash memory. In response to the two signals, awaiting mode controller implements a waiting mode by outputting a control signal to open and close an AND gate using the control signal, thereby halting a supply of a clock signal to the CPU in the waiting mode. The microcomputer can reduce the load on software for writing/erasing of the flash memory, and the load on developing software.

Abstract: A system is provided to transfer parallel incoming data from an interface device with an external timing domain, for reading in an internal timing domain, without the use of external control signals. System constraints are reduced by permitting an infinite delay to occur in the byte clock timing through the interface device. The system tolerates a specified drift of the byte clock after initialization which may be the result of thermal changes in the interface device, for example. If the specified drift is exceeded, the system is able to reinitialize timing to reestablish the specified byte clock drift, and so continue the transfer of data from the interface device. A method of transferring data using an internal timing domain, from an interface device having an external timing domain, is also provided.

Abstract: An asynchronous logic circuit allows a host Controller or hub to enter a low power state with its clock suspended. When a power manager calls for a low power state, the clock in the host or hub is suspended and the asynchronous logic circuit is engaged. The asynchronous logic circuit can detect events on the port while the host or hub is in the low power mode. The asynchronous logic circuit generates a downstream signal if required and sends out a wake up signal to the power manager. After the host or hub is awake, the host or hub regains control of the bus and the asynchronous logic circuit is disengaged.

Abstract: A data processing device formed in a single semiconductor chip. The data processing device includes an electronic processor, and on-chip peripheral circuitry ordinarily operative together. Further included, are means for selectively entering externally supplied data into the electronic processor and on-chip peripheral circuitry, for starting and stopping operations of the electronic processor and the on-chip peripheral circuitry independently of each other in an emulation mode of operation.

Abstract: A semiconductor integrated circuit has a CPU for executing various processes, at least one hardware module for receiving instructions from the CPU and executing the instructions, and a power management device for controlling the supply of a clock signal to the CPU so as to stop the clock signal to the CPU if the CPU has an idle time to start the next process. The power management device stops the supply of the clock signal to the CPU during a period in which the CPU can sleep, thereby reducing the power consumption of the CPU.

Abstract: A system including a component (e.g., a processor) with a clock and a thermal management controller that monitors a temperature in the system. The thermal management controller varies the component between different performance states (e.g., cycles the processor between a high and a low performance state) when an over-temperature condition is detected. The thermal management controller further throttles the clock of the component while in the low performance state until the over-temperature condition is removed.

Abstract: A portable electronic device and method manage battery-produced power without lowering sound quality for music and other sound effects. In the present invention, an operation clock of the CPU of the portable electronic device and a processing wait time for image drawing are dynamically controlled. When there is no sound emission request, the CPU runs at a low clock rate. Where there is a sound emission request, the CPU runs at a high clock speed. When the sound emission ends, the CPU returns to the low clock rate. A user senses no apparent change, as the CPU slows screen drawing speed at high clock speed and increases screen drawing speed at low clock speed.

Abstract: In a bus reset process of an IEEE-1394 transceiver circuit, a signal is transmitted to a serial bus and a signal from the bus is received and applied to a higher layer. When a transmit bus reset signal is detected in the transmitted signal, a masking signal is exclusively applied to the higher layer in response to the start timing of the transmit bus reset signal. A receive bus reset signal is detected in the received signal. A count operation is started for incrementing a count value in response to the start timing of the detected receive bus reset signal until the count value exceeds a predetermined value. The received signal is then exclusively applied to the higher layer in response to the end timing of the count operation.

Abstract: A method and apparatus for processing interrupts in a computing system include processing for ordering a plurality of interrupts for at least one processor. Such interrupts include system event interrupts, external device interrupts, and may further include power management interrupts, interprocessor interrupts, and/or intraprocessor interrupts. Such processing continues by generating an interrupt enable/disable signal based on the current context of a corresponding processor such that when the processor is performing a particular task which should not be interrupted, an interrupt signal is prevented from being provided to the processor. The processing also includes generating masking information to provide enable/disable masking information regarding each of the plurality of interrupts. As such, the computing system may enable/disable on a per interrupt basis the processing of a given interrupt.

Abstract: In a method for time coordination of the transmission of cyclic data values on a bus to which data transmitters and data receivers are connected, each data transmitter is assigned a cycle time in which it periodically transmits its data values, wherein the cycle times are integer multiples of a minimum cycle time. Furthermore, each data value is assigned a delay time related to the start of the cycle time of its data transmitter. A synchronization message is transmitted via the bus to each data transmitter with a period corresponding to the cycle time of the respective data transmitter and has a phase which is specific for the data transmitter with respect to the start of the minimum cycle time. The reception of its synchronization message in each data transmitter initiates the transmission of its data values with the respective delay time.

Abstract: The number of executed instructions (Iu) in a user mode as one of performance indexes of a computer, and the total number of executed instructions (It) as one of power consumption indexes are used. These parameters have a relationship of E−It/Iu with energy index E. An operating speed (operating frequency) of CPU is increased or decreased so that a value of the performance index may be increased within a range of the power consumption index specified by a user, or a value of the energy index E may be decreased. By doing so, power management processing may be performed, which balances the power saving with the performance.

Abstract: A method for scheduling events between first and second video processing devices coupled together wherein each device having at least one event timer for storing a scheduled event. The method involves programming first event information into the first device, comparing the first event information to each event previously scheduled in the first device for determining conflicts therebetween, sending a message representing the first event information to the second device, comparing the first event information to each event previously scheduled in the second device for determining conflicts therebetween. A user may be provided with information regarding conflicts and may be notified that a password is required for the first event and the respective event timer is enabled in response to receiving the password entered into the first device.

Abstract: The present invention relates to a method for reducing electromagneic emission, especially in connection with high-performance real-time systems, and more specifically for complying with the EMC (ElectroMagnetic Compatibility) thereof, and in order to acheive a reduced electromagnetic emission, it is according to the invention suggested to control the access to the CPU (Central Processing Unit) bus for thereby through power-down to reduce said bus-activity and thereby reduce the electromagnetic emission therefrom.

Abstract: A programmable timer is disclosed for use in conjunction with a microcontroller circuit. The timer is used as part of a time slice arbiter in a real time operating system, which arbiter manages device routines by allocating them to distinct code time slices executable by such microcontroller. The set up of time slices, including their number, sequence, duration, etc., can be configured and optimized to achieve a desired system performance level based on characteristics of an associated system bus, devices on the bus, etc. The timer operates as a hardware controller to direct the interrupt handler to various entry points in the corresponding routines associated with interrupt based devices on a system bus.

Abstract: A coupling circuit for coupling a data signal from a first clock domain defined by a first clock signal to a second clock domain defined by a second clock signal. A phase comparator determines whether the first clock signal leads the second clock signal. If so, the data signal is clocked from the first clock domain at a time after a start signal that is later than if the clock signal does not lead the second clock signal. Alternatively, if the first clock signal leads the second clock signal, the data signal may be clocked to the second clock domain at a time after a start signal that is earlier than if the clock signal does not lead the second clock signal.

Abstract: A microcomputer includes an external pulse signal capturing section and a clock switching software section. The external pulse signal capturing section, operating in synchronization with a low frequency operation clock signal, captures an external pulse signal such as a remote control signal. The clock switching software section decodes the data portion of the input pulse signal obtained by the external pulse signal capturing section, and switches the operation clock signal from a low frequency operation clock signal to a high frequency operation clock signal when the decoded result is a power-on instruction. The microcomputer can solve a problem of a conventional microcomputer in that it can sometimes misidentify noise input to its remote control terminal as a remote control signal, and hence switches the operation clock signal from a low frequency sub-clock signal in an idle mode to a high frequency main clock signal in a normal operation mode, thereby impairing effective power saving.