Abstract: A system includes an input unit (2) to which failure information corresponding to failure modes of constituents indicating software and hardware, a system configuration information and a standard value of system availability are inputted, a producing unit (32) producing a fault tree based on the system configuration information, a calculating unit (34) calculating unavailability corresponding to the failure modes based on a result of analyzing the failure information, and calculating system availability based on the calculated unavailability and the fault tree, a determining unit (35) determining whether the system availability meets the standard value, an extracting unit (36) extracting a basic event related to an increase in the system availability when the system availability is determined to be below the standard value, and resetting units (38, 39) resetting new unavailability and the like based on whether it is possible to reduce the unavailability of the extracted basic event.

Abstract: A system and method for assessing and remedying accessibility of websites is provided. The method includes receiving a website address for assessment, an accessibility guideline and level of assessment to be performed from the user. The method further includes crawling the website for extracting information. The information comprises HTML tags used in designing a webpage. Thereafter, the website is scanned for checking conformance to one or more accessibility parameters. Finally, one or more assessment reports are provided to the user.

Abstract: A method for field error checking begins by decoding a predetermined pattern of a field of a frame to produce a decoded pattern. The method continues by determining, for the decoded pattern, a path metric distance of a predetermined state of a plurality of states of the decoding. The method continues by comparing the path metric distance with an excepted path metric distance for the predetermined state. The method continues by indicating a field error when the path metric distance compares unfavorably with the excepted path metric distance.

Abstract: An apparatus has at least one processing unit to generate a request having a request privilege level. At least one resource exists in the apparatus to receive the request and determine if the request is allowable. The apparatus includes an error handler that determines the nature of an error and performs a reset based upon the privilege level of the request that cause the error.

Abstract: Aspects of configurable logic for hardware bug workaround in integrated circuits may comprise detecting within a chip at least one condition that would likely result in an occurrence of a hardware bug prior to the hardware bug occurring. Upon the detection of the condition, at least one trigger event may be generated within the chip via at least one debug signal, and the trigger event may be utilized to execute workaround code that may prevent the occurrence of the hardware bug. The debug signal may be generated inside the chip and/or outside the chip. The trigger event may be generated by combining a plurality of debug signals within the chip with at least one input or output signal of the chip.

Abstract: A system having a processor, a printed circuit board, and an adapter board, coupled to the processor through the printed circuit board. The adapter board provides a first signal having a first state when the adapter board is in a proper operating condition and a second state when the adapter board is in an improper condition. The adapter board produces a second signal having the second state for less than a predetermined time when an adapter board requires a reset signal from the processor. The adapter board combines the first signal with the second signal a single signal fed to the processor through the printed circuit board. When the processor detects that the single signal is in the second state for a time less than the predetermined period of time, the process interprets the single signal as indicating the adapter board requires a reset.

Abstract: A graphics processing unit has a reduced memory space shadow memory as a source of state information for performing validation of commands. The reduced memory space shadow memory is smaller in size than a full version of state variables associated with an abstract state machine representation of a class of commands received from a software driver.

Abstract: A compiler for incorporating error detection into executable code generates conventional assembler language object code from a source code file. The compiler identifies an error detection segment (EDS) in the assembler code, where the EDS includes a subset of basic blocks in the assembler code. The compiler also identifies register and memory references in the EDS and inserts a set of instructions into the EDS. The inserted instructions record an entry state and an exit state of the referenced registers and memory locations. The state information is stored in a checkpoint portion of system memory. The compiler may generate shadow EDS code including instructions mirroring the instructions in the main EDS and verifying instructions that compare results produced by the mirroring instructions with results produced by the main EDS. The shadow EDS initiates an error recovery process if results produced by the shadow EDS and the main EDS differ.

Abstract: A test circuit for testing a command signal at a package level in a semiconductor device includes: a logic level determining unit for determining logic levels of a plurality of command flag signals in response to a plurality of internal command signals in a test mode; a storage unit for storing the plurality of command flag signals in response to a store control signal and outputting the plurality of command flag signals in series in response to an output control signal; and an output unit for driving an output signal of the storage unit to a data pad.

Abstract: The present invention provides for an apparatus employed to debug a program operating in a supplemental processor when the processor's registers are not readable directly by the debugging operation of a main processor. A program operating in main memory halts due to operational errors. The program code lines save to a cache. In the main processor, a pool of memory is reserved. A copy of the data from the nominally inaccessible supplementary processor registers also transfers to the reserved storage area for processing of the program needing debugging. After the program debugging is complete, a copy of the contents of the memory pool is restored to the memory of the target supplemental processor. A copy of the local store register state and remaining local store data returns to main memory.

Abstract: Methods and systems for facilitating fault tolerance in a non-hot-standby configuration of a network routing system are provided. According to one embodiment, a method is provided for replacing an active processing engine with a non-hot-standby processing engine. Multiple processing engines within a network routing system are configured. The processing engines include an active processing engine having one or more software contexts, representative of a set of objects implementing a virtual router, for example, and a non-hot-standby processing engine having no pre-created software contexts corresponding to the one or more software contexts. Responsive to determining a fault associated with the active processing engine, the active processing engine is dynamically replaced with the non-hot-standby processing engine by creating replacement software contexts within the non-hot-standby processing engine corresponding to the one or more software contexts.

Abstract: Mechanisms for operating in recovery mode while ensuring reliable message processing for messages received during the recovery operation mode. Upon receiving a message corresponding to a particular message transaction, the instance responsible for that message transaction determines from state information corresponding to the transaction, whether or not that instance is operating in normal mode, or recovery mode. If the state information reflects normal operation mode, then the instance processes the message. If recover mode, then the instance evaluates whether or not the message is a normal message suitable for normal operation mode, or a recovery message suitable for recovery operation mode. If the message is a normal message, then the message is placed in a persistent queue for later processing. If the message is a recovery message, the message is processed. Upon completion of recovery, the normal message in the queue may be processed.

Abstract: A processing system is set forth that includes a processor, read only memory storing an operating system image file accessible by the processor, and random access memory that is also accessible by the processor. The processing system also includes a boot program that is executable by the processor to initialize the processing system in response, for example, to a power-on event, reset event, or a wake-up event. A power-on event occurs when power is initially provided to the processing system while a wake-up event occurs when the processing system is to exit a low-power mode of operation. A reset event occurs when, for example, a fault is detected that causes the system to restart. The boot program selectively performs a full boot copy of the operating system image file from the read only memory to the random access memory or a fast boot copy of only predetermined portions of the operating system image file from the read only memory to the random access memory.

Abstract: A method for detecting a malfunction in a state machine is described. The state machine has an operation modeled by a set of states linked to each other by transitions, the state machine generating, upon each transition, output signals according to input signals comprising signals generated during a previous transition. During a transition, the method comprises steps of generating at least one control signal according to a control signal generated during a previous transition, determining an expected value of the control signal, and comparing the control signal with the expected value.

Abstract: An apparatus, system, and method are disclosed for recovering multivolume data. In one embodiment, a backup module physically backs up a plurality of source volumes to plurality of backup volumes. A data set size module may also capture a data set size for a data set during the physical backup. A retrieval module retrieves metadata for the data set from a catalog. A location module locates the data set on the plurality of backup volumes using the metadata. A recovery module recovers the data set as a recovered data set from the plurality of backup volumes. In one embodiment, a verification module verifies that the recovered data set is successfully recovered.

Abstract: Embodiments include a controller apparatus, a computerized apparatus, a device, an apparatus, and a method. A controller-apparatus includes a monitoring circuit for detecting a computational error corresponding to an execution of an instruction of a sequence of instructions by a processor subsystem having an adjustable operating parameter. The controller apparatus also includes a recovery circuit for rolling back an execution of the sequence of instructions to a checkpoint in response to the detected computational error. The controller apparatus further includes a control circuit for adjusting the adjustable operating parameter in response to a performance criterion.

Abstract: Mechanisms for adaptively entering and exiting recovery mode. When a message is received from a particular message transaction, the appropriate processing instance is loaded from persistent memory to system memory. The processing instance then determines from its own state information whether or not it is in recovery mode. This indication of recovery or normal mode may be set by a system-wide recovery detection module. If the processing instance determines that it is in normal mode, then the processing instance executes code appropriate for normal operation without needing to execute any recovery code at all. If, on the other hand, the processing instance determines that it is in recovery mode, then it executes recovery code. Once the recovery code has completed successfully, the processing instance may then cause its own normal mode.

Abstract: An integrated circuit includes a first deserializer that deserializes serial data containing at least one of test instructions and/or data in a first format. A monitor module communicates with the first deserializer and interprets the test instructions and data using the first format. A frame capture module receives test results according to the interpreted test instructions and data. A first control module communicates with the frame capture module and generates first format control data. The frame capture module packages the test results and the first format control data into frames. A first serializer serializes the frames.

Abstract: Restoration of data is facilitated in the storage system by combining data snapshots made by the storage system itself with data recovered by application programs or operating system programs. This results in snapshots which can incorporate crash recovery features incorporated in application or operating system software in addition to the usual data image provided by the storage subsystem.

Abstract: Passive replication methods and systems to facilitate fault tolerance in a network routing system are provided. In one embodiment, a fault associated with a processing engine (PE) of a network routing system is detected by monitoring the health of the network routing system PEs. Responsive to detecting a fault (e.g., a link failure, a failure of a virtual router (VR) or a failure of the PE): VRs that were operating on the PE prior to detection of the fault are identified; configuration information (e.g., a set of command lines in a configuration file) associated with the identified VRs is identified; and the identified VRs are dynamically recreated on a new PE based on the configuration information. For example, a command line interface engine may replay the command line set with a new slot ID and a PE ID of the new PE to recreate the VRs on the new PE.

Abstract: A method for monitoring the execution of a sequence of instruction codes in an integrated circuit comprising a central processing unit provided for executing such instruction codes. In one embodiment, the method comprises producing current cumulative signatures during the execution of a sequence, until a final cumulative signature is obtained, producing an error signal having a value active by default while the current cumulative signature is different to an expected signature, measuring a predetermined time interval that is substantially longer than the presumed duration of execution of the sequence, masking the error signal during the measurement of the time interval, and lifting the masking of the error signal when the time interval expires.

Abstract: A method of diagnosing semiconductor device functional testing failures by combining deterministic and functional testing to create a new test pattern based on functional failure by determining the location of the type of error in the failing circuit. This is accomplished by identifying the failing vector during the functional test, observing the states of the failed device by unloading the values of the latches from the LSSD scan chain before the failing vector, generating a LOAD from the unloaded states of the latches, applying the generated LOAD as the first event of a newly created independent LSSD deterministic pattern, applying the primary inputs and Clocks that produced the failure to a correctly operating device, unloading the output of the correctly operating device to generate a deterministic LSSD pattern; and applying the generated deterministic LSSD pattern to the failing device to diagnose the failure using existing LSSD deterministic tools.

Abstract: An aspect based recovery system and method is provided. The state of a device may be defined by one or more aspects of the device. Aspects may include graphical user interface, database, security, user configuration, site configuration, and current user. Using this aspect-based definition, the current state of the device may be monitored. For example, the current state of the system may be determined by examining the aspects which define the state. Moreover, using this aspect-based definition, the current state of the device may be modified. Aspects may be changed so that the state of the system may be changed to a predetermined state.

Abstract: A POST (power on self test) debug system and method applicable to an electronic device is proposed. First, a reading module reads a POST code of a sub-routine to be executed when the electronic device is started up to execute a power on self test, and sends the POST code to a processing module. When the processing module receives the POST code, the processing module temporarily stores the POST code and detects whether the temporarily stored POST code has been changed at a predefined time interval. If no, the processing module records the temporarily stored POST code such that a user can fine reason for error according to the recorded POST code and repair the system timely. Such a debug system is simple and easy to implement.

Abstract: Systems and methods for asynchronous multi-channel data communications are provided. In one embodiment, a system in accordance with the invention includes a plurality of redundant pairs of computer systems, a plurality of actuators, and a plurality of line replaceable units. Each of the line replaceable units is coupled to one of the actuators, and each of the line replaceable units is configured to receive synchronous digital control data from each pair of computer systems of the plurality of redundant pairs of computer systems. The plurality of redundant pairs of computer systems includes at least three redundant pairs of computer systems, and the plurality of line replaceable units includes three or more line replaceable units.

Abstract: A method includes performing a file system integrity validation on a host machine having a hypervisor architecture when a file system of a second process is mounted on a file system of a first process. The file system integrity validation occurs independently of booting the host machine.

Abstract: System, method and computer program for initiating a search at a server computer. A data base including a URL of the server computer is stored at a client computer. Information entered by a user into the client computer is received. From the information, a search term and the URL of the server computer are identified. Then, an HTTP search request which includes the URL of the server computer and the search term is generated. Then, the HTTP search request is sent to the server computer. The identifying of the URL of the server computer comprises searching the data base for a character string contained in the information that matches the URL of the server computer. The identifying of the search term comprises identifying a portion of the information appended to the URL of the server. The identifying of the search term also comprises omitting from the portion one or more symbols adjacent to the search term which are inconsistent with a search request using HTTP.

Abstract: An integrated circuit comprises a test interface, an embedded in-circuit emulator, a circuit-under-debugging, and a memory. The embedded in-circuit emulator is used for software debugging via the test interface. The circuit-under-debugging comprises a scan chain dumping states of every delayed flip-flop (DFF) out of the circuit-under-debugging. The memory stores the states from the scan chain and transfers the states to a computer via the test interface.

Abstract: A method for diagnosing problems with protection of a data source and recovery of the same. The method includes diagnosing a copy of data located at the storage location and diagnosing a temporal version of the copy of data. Based on the diagnosis it is determined whether an error or a warning was detected. If either were detected a response is provided with a suggested solution.

Abstract: A method, apparatus, and computer program product for graphically presenting compatible workflow steps to a user through a graphical user interface are disclosed. The method includes graphically displaying a plurality of steps in a workflow. A user's selection for at least one step in a plurality of steps to denote at least one selected step and at least one non-selected step is received. The method further includes determining if a set of one or more output parameters of the selected step is acceptable as an input of the non-selected step. An appearance of the non-selected step is graphically changed if the output parameters are acceptable. The method also includes determining if a set of one or more output parameters of the non-selected step is acceptable as an input of the selected step. An appearance of the non-selected step is graphically changed if the output parameters are acceptable.

Abstract: A system and computer program product for monitoring a data processing system is proposed. The system and computer program product involve the measuring of state parameters of the system. Indicators of the performance of the system are then inferred from the state parameters by applying fuzzy-logic rules. The proposed solution is based on the idea of estimating a trust value, based on the effectiveness of the corrective actions. If the previous corrective actions prove to be effective than the trust value is enhanced and the system is allowed a higher level of autonomy. Otherwise the intervention of an operator might be invoked.

Abstract: A method for diagnosing problems with protection of a data source and recovery of the same. The method includes diagnosing a copy of data located at the storage location and diagnosing a temporal version of the copy of data. Based on the diagnosis it is determined whether an error or a warning was detected. If either were detected a response is provided with a suggested solution.

Abstract: Systems and methods for recovering from software processing errors are provided. The systems and methods provide for the validation of data following the occurrence of a software processing error.

Abstract: A method, system and program product save state data in a multi-processor system. A problem in the multi-processor system is detected and a statesave thread is spawned for each processor in the system. Each statesave thread directs a processor, in parallel with the other processors to attempt to identify a component in the system having a status of “incomplete”, indicating that state data of the component remains to be offloaded. When a component having a status of “incomplete” is identified, the processor executes statesave code to offload state data from the identified component. Upon completion of the state data offload from the identified component, the processor changes the status of the component to “complete”. The foregoing processes are repeated until no components are identified in the system having a status of “incomplete”.

Abstract: A system and method includes receiving an event, for example, from a frame relay network or from a system log. Whether the event designates a virtual circuit fault in at least one of the local network, the service provider network, or the communications link is determined. When the event designates a virtual circuit fault it is distinguished which of the local network, the service provider network, or the communications link is the source of the fault.

Abstract: Systems and methods for monitoring the accuracy of unit status reporting within an application specific integrated circuit device may be used reduce power consumption. Accurate status reporting of an idle state is needed to safely disable a clock signal for a unit in order to reduce the power needed by that unit. A watchdog monitor may be used during functional simulation and synthesized for formal verification, emulation, and functional device testing and debugging. The watchdog monitor may also be configured based on specific characteristics of the unit that it is monitoring.

Abstract: Disclosed are a method and system for detecting errors in a computer system including a processing unit to perform tasks to change items. The method comprises the steps of assigning a task control block to the processing unit, and using the task control block to keep track of items being changed by the processing unit. The method comprises the further steps of at defined times, checking the task control block to identify items being changed by the processing unit, and checking the states of said identified items to determine if those states are correct. The preferred embodiment of the invention detects an error when it arises (where possible), and utilizes an infrastructure that allows simple and periodic consistency checks (for example, at designated code points) that detect the error before it causes follow-on problems.

Abstract: A method and apparatus to write a file to a nonvolatile memory is provided. The method may include writing a file to a nonvolatile memory using at least two headers and at least two file fragments and using only information stored in one header of the at least two headers to determine if the writing of the file to the nonvolatile memory was interrupted by a loss of power. Other embodiments are described and claimed.

Abstract: A method for monitoring a data processing system is proposed. The method involves the measuring of state parameters of the system. Indicators of the performance of the system are then inferred from the state parameters by applying fuzzy-logic rules. The proposed solution is based on the idea of estimating a trust value, based on the effectiveness of the corrective actions. If the previous corrective actions prove to be effective than the trust value is enhanced and the system is allowed a higher level of autonomy. Otherwise the intervention of an operator might be invoked.

Abstract: The present invention aims at avoiding a hung-up in the case where a command is sent from a controller within a printer but there is no response to the command from the unit side within the printer, due to a faulty communication or the like, and also in the case where a noise is introduced in the communication data. In the present invention, based on a command sent to the unit side, a data amount of a response from the unit side to this command is predicted, and also a threshold value of response time is provided (S21), which is the time when from the command is sent until the time when the response is received. After the command is sent (S23) until the threshold value of the response time elapses, the receive data is sequentially stored in the receive buffer up to when the data amount from the unit side reaches the predicted data amount (S28, 32, 34).

Abstract: Disclosed is a method for detecting errors in a computer system including a processing unit to perform tasks to change items. The method comprises the steps of assigning a task control block to the processing unit, and using the task control block to keep track of items being changed by the processing unit. The method comprises the further steps of at defined times, checking the task control block to identify items being changed by the processing unit, and checking the states of said identified items to determine if those states are correct. The preferred embodiment of the invention detects an error when it arises (where possible), and utilizes an infrastructure that allows simple and periodic consistency checks (for example, at designated code points) that detect the error before it causes follow-on problems.

Abstract: Monitoring of the state vector of a test access port (TAP) permits isolation of the root cause of improper transitions of the state vector due to various factors, including electrical noise. The test access port includes TCK, TMS, TDI, and TDO. A circuit for monitoring the state vector includes a TAP controller, a storage circuit, and a sampling circuit. The TAP controller updates the state vector for each transition of TCK. The storage circuit stores a value of the state vector responsive to transitions of TCK while a write enable is enabled. To permit generating the write enable without additional pins and without violating a protocol for the test access port, the write enable may be generated in response to a plurality of transitions of TDI of the test access port during an interval in which TMS and TCK of the test access port have no transitions.

Abstract: Distributed transaction and lock management techniques are disclosed that manage and regulate access to distributed data. A lock manager module is provided for regulating access to resources by applications in a system having a number of nodes each communicatively coupled to a network. The module can be configured to be fault tolerant. In one embodiment, the module uses a totally ordered transport that imposes total ordering protocols on messaging between nodes. The module can exploit the multicast ability of the network (e.g., Ethernet or other network features that enable multicast). The module includes a queue for each resource, the queue identifying the node that owns distributed lock for that resource. Each queue can be replicated across the nodes in a distributed configuration.

Abstract: In an image forming apparatus for forming an image in accordance with control codes stored in a plurality of memory media, when the control codes stored in the plurality of memory media to control the image forming apparatus is rewritten, rewrite execution codes adapted to execute rewrite of the control codes are transferred to predetermined one of the plurality of memory media from an external apparatus, and rewrite of the control codes is performed in accordance with the transferred rewrite execution codes.

Abstract: A system for detecting transmission errors in a data transmission system includes a receiver for receiving a data packet transmitted thereto by a corresponding transmitter and transmitting the data packet to a destination device and an error detection device for receiving a plurality of protocol signals that control the operation of the transmitter and the receiver. The error detection device applies at least one predetermined rule to the protocol signals, wherein a violation of the at least one rule by the protocol signals indicates that an error in the transmission of the packet has occurred, and asserts an error signal when the at least one rule has been violated by the protocol signals. The system further includes a packet filtering device coupled to receive the error signal from the error detection device and the data packet from the receiver, wherein, upon receiving the asserted error signal, the packet filtering device terminates the transmission of the data packet to the destination device.

Abstract: Even if business processing is transaction, a standby-type cluster system copes with double faults in a short time while holding down the standby computer cost to the minimum. An execution server monitoring thread in a standby server periodically monitors an operation state of an execution server. Upon detecting time-out as a result of the monitoring, the thread resets the execution server, stops load balancing to an IP address of the execution server, recovers transaction of the execution server, and returns to monitoring of the operation state. If normality of the execution server is detected as the result of monitoring and an operation state in an execution server management table is “stop,” the thread starts the load balancing to the execution server and returns to the monitoring of the operation state.

Abstract: A DMA device prefetches descriptors into a descriptor prefetch buffer. The size of descriptor prefetch buffer holds an appropriate number of descriptors for a given latency environment. To support a linked list of descriptors, the DMA engine prefetches descriptors based on the assumption that they are sequential in memory and discards any descriptors that are found to violate this assumption. The DMA engine seeks to keep the descriptor prefetch buffer full by requesting multiple descriptors per transaction whenever possible. The bus engine fetches these descriptors from system memory and writes them to the prefetch buffer. The DMA engine may also use an aggressive prefetch where the bus engine requests the maximum number of descriptors that the buffer will support whenever there is any space in the descriptor prefetch buffer. The DMA device discards any remaining descriptors that cannot be stored.

Abstract: A method and system for debug and test using replicated logic is described. A representation of a circuit is compiled. The circuit includes a replicated portion and delay logic to delay inputs into the replicated portion. The circuit may also include trigger logic and clock control logic to enable execution of the replicated portion of the circuit to be paused when a trigger condition occurs. The compiled representation of the circuit may be programmed into a hardware device. A debugger may then be invoked. One or more triggering signals are selected. For each selected triggering signal, one or more states are selected to setup a trigger condition. The hardware device may then be run. The replicated portion of the circuit will be paused when the trigger condition occurs. The states of registers in the replicated portion of the circuit and the sequence of inputs that led to the trigger condition are recorded.

Abstract: A buffer manager for controlling a buffer in a disk drive having a main control processor for performing functions relating to transfer of data between a host and disk media includes a processor for managing caching algorithms with respect to the buffer. A memory in communication with the processor stores instructions executed by the processor in performing the caching algorithms, and a storage unit stores data used by the processor in performing the caching algorithms.

Abstract: A method, apparatus and program storage device for performing fault tolerant code upgrade on a fault tolerant system by determining when functional code reaches a desired state before resuming an upgrade. A concurrent code-load to a plurality of storage controllers of a storage system is initiated. A role transition is detected. The storage system determines when the storage system returns to a desired state. The code-load is resumed when the storage system returns to the desired state.