Data Processing System Error Or Fault Handling Patents (Class 714/100)
-
Patent number: 12184487Abstract: The present invention relates to a serverless computing method and apparatus, and more particularly, to a serverless computing method and apparatus using mutual monitoring between network edges. The serverless computing method according to one embodiment of the present invention comprises monitoring, by an event handler of the first network edge, an event occurring in the second network edge, generating, by an event generating module of the second network edge, an event response signal through filtering on the event in response to the event occurring, transmitting, by an event delivery module of the second network edge, the event response signal to the event handler of the first network edge, and scaling an application, by an auto-scaler, in the first network edge based on the event response signal.Type: GrantFiled: February 24, 2022Date of Patent: December 31, 2024Assignee: FOUNDATION OF SOONGSIL UNIVERSITY-INDUSTRY COOPERATIONInventors: Young Han Kim, Jae Eun Cho
-
Patent number: 12067400Abstract: Processing circuitry has a handler mode and a thread mode. In response to an exception condition, a switch to handler mode is made. In response to an intermodal calling branch instruction specifying a branch target address when the processing circuitry is in the handler mode, an instruction decoder controls the processing circuitry to save a function return address to a function return address storage location; switch a current mode of the processing circuitry to the thread mode; and branch to an instruction identified by the branch target address. This can be useful for deprivileging of exceptions.Type: GrantFiled: November 5, 2020Date of Patent: August 20, 2024Assignee: Arm LimitedInventor: Thomas Christopher Grocutt
-
Patent number: 11683348Abstract: In an approach for bypassing security vulnerable and anomalous devices in a multi-device workflow, a processor monitors behavior and network traffic of a plurality of smart devices within a multi-smart device system. A processor identifies a first smart device of the plurality of smart devices with at least one of a security vulnerability and an anomaly. A processor identifies a multi-smart device workflow that includes the first smart device. A processor identifies a function of the first smart device within the multi-smart device workflow. A processor determines whether an alternative smart device can replace the first smart device within the multi-smart device workflow. Responsive to resolution of the at least one of the security vulnerability and the anomaly, a processor re-establishes the workflow with the first smart device.Type: GrantFiled: July 10, 2020Date of Patent: June 20, 2023Assignee: International Business Machines CorporationInventors: Manish Anand Bhide, Sarbajit K. Rakshit, Madhavi Katari, Seema Nagar, Kuntal Dey
-
Patent number: 11636012Abstract: A method and apparatus for performing node information exchange management of an all flash array (AFA) server are provided. The method may include: utilizing a hardware manager module among multiple program modules running on any node of multiple nodes of the AFA server to control multiple hardware components in a hardware layer of the any node, for establishing a Board Management Controller (BMC) path between the any node and a remote node among the multiple nodes; utilizing at least two communications paths to exchange respective node information of the any node and the remote node, to control a high availability (HA) architecture of the AFA server according to the respective node information of the any node and the remote node, for continuously providing a service to a user of the AFA server; and in response to malfunction of any communications path, utilizing remaining communications path(s) to exchange the node information.Type: GrantFiled: October 29, 2021Date of Patent: April 25, 2023Assignee: Silicon Motion, Inc.Inventor: Zheng-Jia Su
-
Patent number: 11500634Abstract: A computer program stored in a computer readable storage medium is provided. It includes encoded commands, in which when the computer program is executed by one or more processors of a computer system. The computer program allows the one or more processors to perform certain commands for distributing resources of a computing device.Type: GrantFiled: December 23, 2020Date of Patent: November 15, 2022Assignee: SILCROAD SOFT, INC.Inventor: Jeong Il Yoon
-
Patent number: 11379340Abstract: An apparatus for estimating anomaly information includes an input unit configured to input anomaly data detected as anomaly by an anomaly detecting algorithm that outputs an anomaly degree of input data for vectors, using learning of the vectors in a normal state, and an estimate unit configured to search for one or more vectors that decrease the degree of anomaly when added to the anomaly data, taking into account a likelihood, for each dimension, of a given dimension being a cause of the anomaly, and estimate the cause of the anomaly based on the searched vectors whereby it is possible to estimate detailed information on a detected anomaly.Type: GrantFiled: November 9, 2017Date of Patent: July 5, 2022Assignee: NIPPON TELEGRAPH AND TELEPHONE CORPORATIONInventors: Yasuhiro Ikeda, Keisuke Ishibashi, Yusuke Nakano, Keishiro Watanabe, Ryoichi Kawahara
-
Patent number: 11334467Abstract: A computer-implemented method, system and computer program product for representing source code in vector space. The source code is parsed into an abstract syntax tree, which is then traversed to produce a sequence of tokens. Token embeddings may then be constructed for a subset of the sequence of tokens, which are inputted into an encoder artificial neural network (“encoder”) for encoding the token embeddings. A decoder artificial neural network (“decoder”) is initialized with a final internal cell state of the encoder. The decoder is run the same number of steps as the encoding performed by the encoder. After running the decoder and completing the training of the decoder to learn the inputted token embeddings, the final internal cell state of the encoder is used as the code representation vector which may be used to detect errors in the source code.Type: GrantFiled: May 3, 2019Date of Patent: May 17, 2022Assignee: International Business Machines CorporationInventors: David Wehr, Eleanor Pence, Halley Fede, Isabella Yamin, Alexander Sobran, Bo Zhang
-
Patent number: 11307557Abstract: A method for monitoring process instances that are being executed and for eliminating process anomalies in the process instances is provided. In a monitoring step, a sensor, using a sensor definition, monitors a process log with respect to a process anomaly described in the sensor definition, and detects process instances or processes that have the process anomaly described in the sensor definition. In a correction step, for a process instance detected in the monitoring step, the process anomaly is eliminated at the runtime of the process instance.Type: GrantFiled: September 11, 2020Date of Patent: April 19, 2022Assignee: Celonis SEInventors: Alexander Rinke, Martin Klenk
-
Patent number: 11281491Abstract: Methods to execute an orchestration of computing services concurrently, the method including developing a representation of a set of services where each service relates to other services via different types of relationships. Also, applying a set of dependency rules for each type of relationship within the set of services such that the application of the dependency rules creates inter-step dependencies between steps representing state transitions of the set of services and developing the orchestration plan based on the inter-step dependencies that allows for concurrent execution of nondependent steps.Type: GrantFiled: November 21, 2018Date of Patent: March 22, 2022Assignee: Hewlett Packard Enterprise Development LPInventors: Peter Michael Bruun, Jane Koenigsfeldt, Mads Stenhuus
-
Patent number: 11275638Abstract: A system and method that allows debugging data to be stored without slowing down initialization is disclosed. The system includes a processor, a firmware read only memory (ROM), and a first memory device coupled to the firmware ROM. The firmware ROM can be a BIOS ROM. The first memory device is configured to store debug information from the firmware ROM prior to running an operating system on the processor. Having the firmware ROM store the debug information on the first memory device allows debug information associated with the firmware to be easily accessible without needing a debug firmware or a cable to receive outputs of the debug firmware.Type: GrantFiled: March 2, 2021Date of Patent: March 15, 2022Assignee: QUANTA COMPUTER INC.Inventors: Chun-Ping Huang, Kuo-Chun Liao, Chih-Hsiang Hsu
-
Patent number: 11243805Abstract: A technique for job distribution within a grid environment includes receiving jobs at a submission cluster for distribution of the jobs to at least one of a plurality of execution clusters where each execution cluster includes one or more execution hosts. Resource attributes are determined corresponding to each execution host of the execution clusters. Resource requirements are determined for the job and candidate execution clusters are identified for processing the job based on the resource attributes of the execution hosts and the resource requirements of the job. An optimum execution cluster is selected from the candidate execution clusters for allocating the job thereto for execution of the job based on a weighting factor applied to select resources of the respective execution clusters.Type: GrantFiled: March 25, 2019Date of Patent: February 8, 2022Assignee: International Business Machines CorporationInventors: Chong Chen, Fang Liu, Qi Wang, Shutao Yuan
-
Patent number: 11188269Abstract: A storage cluster is provided. The storage cluster includes a plurality of storage nodes coupled together as the storage cluster. The plurality of storage nodes is configured to assign data to two or more logical arrays and the plurality of storage nodes is configured to establish data striping across the plurality of storage nodes for user data of each of the two or more logical arrays.Type: GrantFiled: July 11, 2019Date of Patent: November 30, 2021Assignee: Pure Storage, Inc.Inventors: John Hayes, Par Botes
-
Patent number: 11086371Abstract: An apparatus for heat suppression in an initial setting mode includes, in one embodiment, an execution unit of an information processing device that executes an operation related to an initial setting mode of the information processing device, a power supply that supplies power to one or more heat generating components of the execution unit, and a controller that controls at least the power supplied by the power supply to make an amount of heat generation of the execution unit in the initial setting mode lower than the amount of heat generation of the execution unit in an operating mode after termination of the initial setting mode until fulfillment of a predetermined condition. A method and a computer program product also perform functions of the apparatus.Type: GrantFiled: May 22, 2019Date of Patent: August 10, 2021Assignee: Lenovo (Singapore) PTE. LTD.Inventors: Akinori Uchino, Toyoaki Inada, Yusaku Morishige, Kazuhiro Kosugi, Hajime Yoshizawa, Yuhsaku Sugai, Hiroki Oda
-
Patent number: 10922261Abstract: A memory clock frequency adjusting method suitable for a computer device is provided. The computer device includes a basic input output system (BIOS) and a memory. The memory clock frequency adjusting method includes following steps. A boot process of the computer device is executed, and the memory is operated at a memory clock frequency set by the BIOS. Whether the computer device is successfully booted is determined by the BIOS to decide whether the boot process of the computer device is to be re-executed. A setting of the memory clock frequency is adjusted by the BIOS when the computer device re-executes the boot process to lower the memory clock frequency, so that the memory is operated at the lowered memory clock frequency. In addition, a mainboard and a computer operating system applying the memory clock frequency adjusting method are also provided.Type: GrantFiled: April 10, 2017Date of Patent: February 16, 2021Assignee: GIGA-BYTE TECHNOLOGY CO., LTD.Inventors: Cho-May Chen, Hou-Yuan Lin, Sheng-Liang Kao
-
Patent number: 10901737Abstract: A computer program stored in a computer readable storage medium is provided. It includes encoded commands, in which when the computer program is executed by one or more processors of a computer system. The computer program allows the one or more processors to perform certain commands for distributing resources of a computing device.Type: GrantFiled: November 9, 2017Date of Patent: January 26, 2021Assignee: SILCROAD SOFT, INC.Inventor: Jeong Il Yoon
-
Patent number: 10831578Abstract: A processing system, such as for an automobile, includes multiple processor cores, including an application core and a safety core, and a fault detection circuit in communication with the processor cores. The fault detection circuit includes a progress register for storing progress data of an application executed on the application core. The safety core, which executes a fault detection program, reads the progress data from the progress register, and generates an output based on the progress data and an expected behavior of the application. The safety core writes the output to a status register of the fault detection circuit. The fault detection circuit includes a controller that reads the status register and generates a fault signal when the output indicates there is a fault in the execution of the application. In response, the application core either recovers from the fault or runs in a safe mode.Type: GrantFiled: September 28, 2018Date of Patent: November 10, 2020Assignee: NXP USA, INC.Inventors: Hemant Nautiyal, Jan Chochola, Ashish Kumar Gupta, David Baca
-
Patent number: 10601858Abstract: The present invention relates to methods, network devices, and machine-readable media for an integrated environment for a method of environment security validation through controlled computer network exploitation. A set of parameters is received from an operator over the network. Based on these parameters an attack campaign is performed on the environment. In the course of the campaign, vulnerable hardware and software in the attacked network are identified. In another scenario, vulnerable hardware and software are mitigated until vendors provide official patches.Type: GrantFiled: January 11, 2019Date of Patent: March 24, 2020Assignee: Scythe, Inc.Inventors: Ateeq Sharfuddin, Bryson Bort, Robert W. Winchester-Mauck
-
Patent number: 10595255Abstract: Provided are a wireless communication apparatus, a system and a method that are suitable for establishing steady communication by using a redundant configuration. The wireless communication apparatus includes a plurality of devices that transmit and receive data through a wireless network. The devices each include a control section and a decision section. The decision section in one of the devices designates a first device from among the devices as a first valid device, and designates a second device as a second valid device. The control section in the first device copies to the second device the data and coupling information for transmitting and receiving the data. When the second device is determined to valid, the control section in the second device transmits the copied data from the second device.Type: GrantFiled: April 20, 2018Date of Patent: March 17, 2020Assignee: RENESAS ELECTRONICS CORPORATIONInventor: Makoto Maeda
-
Patent number: 10225276Abstract: The present invention relates to methods, network devices, and machine-readable media for an integrated environment for a method of environment security validation through controlled computer network exploitation. A set of parameters is received from an operator over the network. Based on these parameters an attack campaign is performed on the environment. In the course of the campaign, vulnerable hardware and software in the attacked network are identified. In another scenario, vulnerable hardware and software are mitigated until vendors provide official patches.Type: GrantFiled: January 9, 2018Date of Patent: March 5, 2019Assignee: SCYTHE INC.Inventors: Bryson Bort, Ateeq Sharfuddin, Robert W. Winchester-Mauck, Benjamin L. Dagana, Larry M. White, Christopher M. Balles, Tiffany Williams, Tommy Chin, Sean McConnell
-
Patent number: 10216702Abstract: A machine generates and provides a digital impact matrix including a first matrix and, in some embodiments, a second matrix, the first matrix including a plurality of impacts that various digital technologies have on various organizational processes. In some embodiments, the first matrix includes a plurality of magnitudes of impacts, while the second matrix includes a plurality of business values of impact that the various digital technologies have on the various organizational processes. A user interface is provided to assign impact categorizations to the impacts and of the first matrix and the second matrix, if applicable, and to display a graphical representation of the digital impact matrix.Type: GrantFiled: November 14, 2016Date of Patent: February 26, 2019Assignee: Accenture Global Solutions LimitedInventors: Silke Lehmann, Ankur Saxena
-
Patent number: 10191798Abstract: Certain aspects of the present disclosure relate to selecting a deferral period after detecting an error in a received packet by an apparatus for wireless communications. The apparatus generally includes an interface configured to obtain a frame received over a medium, and a processing system configured to detect an occurrence of an error when processing the frame, determine an intended recipient of the frame based on information included in the frame, and select a deferral period, after detecting the occurrence of the error, during which the apparatus refrains from transmitting on the medium, wherein the selection is based, at least in part, on the determination.Type: GrantFiled: May 4, 2016Date of Patent: January 29, 2019Assignee: QUALCOMM IncorporatedInventor: Alfred Asterjadhi
-
Patent number: 10175748Abstract: A personal computer or other electronic device may be powered by an external power supply and may have a legacy ambient temperature sensor e.g. because a fan whose speed is controlled by a controller, uses as an input, inter alia, ambient air temperature received from the legacy temperature sensor which may be disposed adjacent the fan. A controller may be provided which limits the current based on ambient air temperature reading/s flowing out of the sensor thereby to optimize power consumption relative to conventional “worst-case-assumption based” control of the current, in which current supplied is limited, mindful of a pre-set worst-case temperature assessment, to an un-necessarily low level of current.Type: GrantFiled: January 5, 2017Date of Patent: January 8, 2019Assignee: NUVOTON TECHNOLOGY CORPORATIONInventor: Moshe Alon
-
Patent number: 10133562Abstract: Data is received that characterizes a score model. Thereafter, the score model is normalized by transforming it into a directed acyclic graph. The directed acyclic graph is then transformed into a structured rules language program. The structured rules language program is then transformed into a program using a concurrent, class-based, object-oriented computer programming language (e.g., JAVA, C, COBOL, etc.). Related apparatus, systems, techniques and articles are also described.Type: GrantFiled: October 31, 2016Date of Patent: November 20, 2018Assignee: FAIR ISAAC CORPORATIONInventors: Andrei R. Yershov, Andrew K. Holland
-
Patent number: 9996436Abstract: One or more techniques and/or computing devices are provided for communicating storage controller failures utilizing service processor traps. A first storage controller, of a first storage cluster, has a disaster recovery relationship with a second storage controller of a second storage cluster. The first storage controller comprise a first service processor configured to monitor health of the first storage controller. Responsive to identifying a failure of the first storage controller, the first service processor uses stored communication configuration of a second service processor of the second storage controller to send a service processor trap to the second service processor. In this way, the second service processor initiates a switchover operation by the second storage controller to provide clients with failover access to data previously available through the first storage controller before the failure.Type: GrantFiled: October 22, 2015Date of Patent: June 12, 2018Assignee: NetApp Inc.Inventors: Hrishikesh Keremane, Vijay Singh, David Andrew Allender
-
Patent number: 9843564Abstract: A method and system for securing data in a computer system provides the capability to secure information even when it leaves the boundaries of the organization using a data loss agent integrated with encryption software. A method for securing data in a computer system comprises detecting attempted connection or access to a data destination to which sensitive data may be written, determining an encryption status of the data destination, allowing the connection or access to the data destination when the data destination is encrypted, and taking action to secure the sensitive data when the data destination is not encrypted.Type: GrantFiled: November 17, 2014Date of Patent: December 12, 2017Assignee: McAfee, Inc.Inventors: Elad Zucker, Eran Werner, Mattias Weidhagen
-
Patent number: 9727398Abstract: A first control device includes: a switch device including a first port connected to a second control device among the plurality of control devices via a first channel and a second port connected to the second control device via a second channel and to which a processing device is connected; a detection unit that detects an error in the control devices; a first reset processing unit that performs a port reset of the first port included in the switch device; and a transmitting unit that transmits a reset instruction to the second control device; thereby propagation of an error occurred in a control device can be inhibited.Type: GrantFiled: October 27, 2014Date of Patent: August 8, 2017Assignee: FUJITSU LIMITEDInventor: Takashi Kidamura
-
Patent number: 9558110Abstract: A method of managing a rewritable mass memory subdivided into sectors within which data pages are recorded, and data periodically updated, where data erasure in a sector erases all previously written data therein. The method includes: writing pieces of data in a sector, each piece being associated with a first block containing at least one information for identifying the data piece, writing information data in an administrative block for managing the data of the sector concerned in the sector, each block being written among other data of the sector and being associated with a second block including one information piece and one check information piece, a block including a first part giving general indications and a second part including a counter being incremented at each writing of an administrative block in a new sector, each first block including a check number which is based on the corresponding administrative block counter.Type: GrantFiled: October 16, 2013Date of Patent: January 31, 2017Assignees: CONTINENTAL AUTOMOTIVE FRANCE, CONTINENTAL AUTOMOTIVE GMBHInventors: Nicolas Boursier, Andreas Mehrwald
-
Patent number: 9485168Abstract: An apparatus and method routes data over network links based on a temperature of the network links. When the temperature of a link meets a first threshold a routing mechanism re-routes a portion of the network traffic over a lower temperature link to reduce the likelihood that the link will exceed a second threshold that necessitates that the link be throttled back or disabled. Re-routing data to cooler links allows the system to maintain the lowest possible temperature of the network links to gain optimal performance of the system. In the disclosed example, the network links include interconnect cable connections and backplane connections. A temperature of the network links is determined by monitoring a region of an integrated circuit near a line driver driving the network link.Type: GrantFiled: October 3, 2013Date of Patent: November 1, 2016Assignee: International Business Machines CorporationInventors: Brett J. Reese, Gary R. Ricard, Jaimeson J. Saley
-
Patent number: 9477444Abstract: A control server receives information from detector agents associated with an application program being executed by a processor. The information, which is collected by the detector agents at runtime of the application, includes data with which the control server can generate a representation of the software architecture for the application. The control server compares the generated representation to representations of a set of known acceptable architectures. Based on the results of that comparison, the control server indicates whether the architecture of the application is a valid architecture. Recommendations for modifying the architecture of the application may be made in cases where the architecture is not deemed valid by the control server.Type: GrantFiled: December 30, 2014Date of Patent: October 25, 2016Assignee: CA, Inc.Inventors: Tony Shen, Kevin Liu
-
Patent number: 9459633Abstract: A thermal workload distribution controller receives, for each of multiple thermal controlled areas, at least one current thermal measurement from at least one separate thermostat node. The thermal workload distribution controller selects a particular thermal controlled area from among the multiple thermal controlled areas that is most optimal to receive additional heat based on the at least one current thermal measurement received for each of the thermal controlled areas. The thermal workload distribution controller distributes at least one workload to a server node associated with the particular thermal controlled area, wherein the heat dissipated by the server from executing the workload affects a thermal environment of the particular thermal controlled area.Type: GrantFiled: October 30, 2013Date of Patent: October 4, 2016Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Andrew Geissler, Michael C. Hollinger
-
Patent number: 9438541Abstract: The invention concerns a method for sending information about users assigned to work on tasks, wherein data sets comprising information about users and tasks the users are assigned to are stored in particular on a first server (101), wherein a request for information about a user is received, in particular via a receiver (API) of said first server (101), wherein said request comprises information about a predetermined task, wherein a test is performed, in particular by a processor (111) of said first server (101) to determine a data set comprising information about a user assigned to said predetermined task, wherein a reply is sent, in particular by a sender (API) of said first server (101), depending on the result of said test, wherein said reply comprises information about said user.Type: GrantFiled: March 28, 2012Date of Patent: September 6, 2016Assignee: Alcatel LucentInventor: Roman Sorokin
-
Patent number: 9348714Abstract: One or more techniques and/or systems are provided for load balancing between storage controllers. For example, a first storage controller and a second storage controller may be configured at a first storage site according to a high availability configuration, and may be configured as disaster recovery partners for a third storage controller and a fourth storage controller at a second storage site. If the first storage controller fails, the second storage controller provides failover operation for a first storage device. If a disaster occurs at the second storage site, the second storage controller provides switchover operation for a third storage device and a fourth storage device. Responsive to the first storage controller being restored, the third storage device may be reassigned from the second storage controller to the first storage controller for load balancing at the first storage site during disaster recovery of the second storage site.Type: GrantFiled: March 20, 2014Date of Patent: May 24, 2016Assignee: NetApp Inc.Inventors: Abhishek Jain, Chaitanya Patel, Deepan Natesan Seeralan, Linda Ann Riedle
-
Patent number: 9280411Abstract: A method for operating a controller includes receiving a command associated with at least one operation, determining a CPU channel path based on the received command, determining a unique job identifier based on the received command, and determining a state based on the received command. In addition, the method includes updating at least one data matrix based on the determined state, unique job identifier and CPU channel path and operating the controller based on the updated data matrix.Type: GrantFiled: February 23, 2015Date of Patent: March 8, 2016Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Brian D. Clark, Juan A. Coronado, Beth A. Peterson
-
Patent number: 9262173Abstract: A method and apparatus for detecting lock instructions and lock release instruction, as well as predicting critical sections is herein described. A lock instruction is detected with detection logic, which potentially resides in decode logic. A lock instruction entry associated with the lock instruction is stored/created. Address locations and values to be written to those address location of subsequent potential lock release instruction are compared to the address loaded from by the lock instruction and the value load by the lock instruction. If the addresses and values match, it is determined that the lock release instruction matches the lock instruction. A prediction entry stores a reference to the lock instruction, such as a last instruction pointer (LIP), and an associated value to represent the lock instruction is to be elided upon subsequent detection, if it is determined that the lock release instruction matches the lock instruction.Type: GrantFiled: January 13, 2012Date of Patent: February 16, 2016Assignee: Intel CorporationInventors: Haitham Akkary, Ravi Rajwar, Srikanth T. Srinivasan
-
Patent number: 9229828Abstract: A mechanism is described for achieving high memory reliability, availability, and serviceability (RAS) according to one embodiment of the invention. A method of embodiments of the invention includes detecting a permanent failure of a first memory device of a plurality of memory devices of a first channel of a memory system at a computing system, and eliminating the first failure by merging a first error-correction code (ECC) locator device of the first channel with a second ECC locator device of a second channel, wherein merging is performed at the second channel.Type: GrantFiled: December 8, 2014Date of Patent: January 5, 2016Assignee: Intel CorporationInventors: Dableena Das, Kai Cheng, Jonathan C. Jasper
-
Patent number: 9092215Abstract: A processor 4 is provided which supports a first instruction set specifying 32-bit architectural registers and a second instruction set specifying 64-bit architectural registers. Each of these instruction sets is presented with its own set of architectural registers for use. The first set of registers presented to the first instruction set has a one-to-one mapping to the second set of registers presented to this second instruction set. The registers which are provided in hardware are 64-bit registers. In some embodiments, when executing program instructions of the first instruction set, only the least significant portion of these 64-bit registers are accessed and manipulated with the remaining most significant portion of the registers being left unaltered.Type: GrantFiled: February 22, 2011Date of Patent: July 28, 2015Assignee: ARM LimitedInventors: Richard Roy Grisenthwaite, David James Seal
-
Patent number: 9020779Abstract: A first of a plurality of data lanes of a first of a plurality of processor links is determined to have a weakest of base performance measurements for the plurality of data lanes. A switching data pattern is transmitted via a first set of the remainder processor links and a quiet data pattern is transmitted via a second set of the remainder processor links. If performance of the first data lane increases vis-à-vis the corresponding base performance measurement, the first set of remainder processor links is eliminated from the remainder processor links. If performance of the first data lanes decreases vis-à-vis the corresponding base performance measurement, the second set of remainder processor links is eliminated from the remainder processor links. The above operations are repeatedly executed until an aggressor processor link that is determined to decrease performance of the first of the plurality of data lanes is identified.Type: GrantFiled: October 25, 2011Date of Patent: April 28, 2015Assignee: International Business Machines CorporationInventors: Robert W. Berry, Jr., Anand Haridass, Prasanna Jayaraman
-
Patent number: 9021587Abstract: The subject disclosure is directed towards detecting software vulnerabilities in an isolated computing environment. In order to evaluate each input submission from an external computer, a plurality of tasks are automatically generated for execution on one or more computing units running within the isolated computing environment. Various configurations of the one or more computing units are defined in which each computing unit executes the plurality of tasks. A report is produced comprising results associated with such an execution.Type: GrantFiled: October 27, 2011Date of Patent: April 28, 2015Assignee: Microsoft Technology Licensing, LLCInventors: Nitin Kumar Goel, Kenneth D. Johnson, Matthew Ryan Miller, Navin Narayan Pai, Grzegorz M. Wroblewski, Gregory Justice Riggs
-
Patent number: 8990817Abstract: Various systems and methods for automated error recovery in workflows. For example, one method involves receiving an operation indication. The operation indication indicates an operation that is to be performed using a multi-tier application system that includes first and second applications. The first and second applications are implemented using different tiers of the multi-tier application system. The method involves accessing dependency information that indicates first data dependencies between the first and the second applications. The method further involves determining outcome of execution of the operation, where the determining is based on the dependency information but does not include executing the operation.Type: GrantFiled: September 6, 2012Date of Patent: March 24, 2015Assignee: Symantec CorporationInventors: Debasish Garai, Sumeet S. Kembhavi
-
Patent number: 8977729Abstract: Various system and method embodiments are disclosed that include using a first node to receive messages including error information from a plurality of client computers via a computer network. Recommendations for resolving errors associated with the error information are made available to the client computers via the computer network.Type: GrantFiled: March 15, 2006Date of Patent: March 10, 2015Assignee: Hewlett-Packard Development Company, L.P.Inventors: Joshua Hawkins, William Brothers, Phil A. Flocken, Jay Shaughnessy, Travis Scott Tripp
-
Patent number: 8972422Abstract: A method for managing log messages in a system includes identifying a log message having a data value, filtering a first data value from a historical log record for a first interval, predicting whether any particular system events should occur when the first data value is filtered from a received log record and identifying the corresponding system events, initiating a second interval while filtering the first data value from a received log record, determining whether any non-predicted system events have occurred, and removing the filter for the first data value responsive to determining that a non-predicted system event has occurred.Type: GrantFiled: November 25, 2013Date of Patent: March 3, 2015Assignee: International Business Machines CorporationInventors: Eli M. Dow, Erin M. Farr, Douglas M. Zobre
-
Patent number: 8966503Abstract: The method includes monitoring a plurality of information handling systems. The method further includes receiving an anomalous event with respect to at least one information handling system of the plurality of information handling systems. In addition, the method includes performing, via at least one correlation handler, at least one correlation algorithm on the anomalous event. Further, the method includes, responsive to the performing, creating, via the correlation handler, at least one composite event. Additionally, the method includes sending the at least one composite event to an event handler. The method also includes issuing, via the event handler, an alert for the at least one composite event.Type: GrantFiled: March 15, 2013Date of Patent: February 24, 2015Assignee: Dell Software Inc.Inventors: Kelly Noel Dyer, David McAleer, Omair-Inam Abdul-Matin
-
Patent number: 8958429Abstract: In some embodiments, an apparatus includes a gateway device configured to be operatively coupled to a Fiber Channel switch by a first data port and a second data port. The gateway device is configured to designate the first data port as a primary data port and the second data port as a secondary data port. The gateway device is configured to associate a set of virtual ports with the first data port and not the second data port when in the first configuration. The gateway device is configured to associate the set of virtual ports with the second data port when in the second configuration. The gateway device moves from the first configuration to the second configuration when an error associated with the first data port is detected.Type: GrantFiled: December 22, 2010Date of Patent: February 17, 2015Assignee: Juniper Networks, Inc.Inventors: Amit Shukla, Suresh Boddapati
-
Patent number: 8942337Abstract: The accuracy of data processing operations in implantable medical devices is improved through reductions in errors associated with data acquisition, reading, and transmission. In one embodiment, two or more circuit modules of the device are operated at different clock speeds and a voting scheme is utilized to obtain a valid data value from one of the modules. The disclosure describes methods, devices and systems that utilize the voting schemes to eliminate errors induced by race conditions in obtaining the valid data values by obtaining a plurality of data samples during operation of the circuit modules at the different clock speeds and selecting from among the data samples the valid data value.Type: GrantFiled: April 25, 2012Date of Patent: January 27, 2015Assignee: Medtronic, Inc.Inventor: Robert A. Corey
-
Patent number: 8938409Abstract: A method analyzes a quality control strategy. A quality control rule can define quality control events and specifying a control limit for determining whether a quality control event passes or fails. The quality control rule and a number of patient samples tested between quality control events can be received. A first expected number of correctible errors when a quality control event fails can be computed based on the quality control rule and the number of patient samples tested between quality control events. A second expected number of final errors that are not correctible when a quality control event fails can be computed based on the quality control rule and the number of patient samples tested between quality control events. An assessment of the quality control rule can include the first expected number of correctible errors and the second expected number of final errors as separate values.Type: GrantFiled: April 4, 2014Date of Patent: January 20, 2015Assignee: Bio-Rad Laboratories, Inc.Inventors: Curtis Alan Parvin, John C. Yundt-Pacheco
-
Patent number: 8930326Abstract: According to one embodiment of the present invention, a system analyzes data in response to detecting occurrence of an event, and includes a computer system including at least one processor. The system maps fields between the data and a fingerprint definition identifying relevant fields of the data to produce a fingerprint for the data. The data is deleted after occurrence of the event. The produced fingerprint is stored in a data repository, and retrieved in response to detection of the event occurrence after the data has been deleted. The system analyzes the retrieved fingerprint to evaluate an impact of the event on corresponding deleted data. Embodiments of the present invention further include a method and computer program product for analyzing data in response to detecting occurrence of an event in substantially the same manner described above.Type: GrantFiled: February 27, 2012Date of Patent: January 6, 2015Assignee: International Business Machines CorporationInventors: Kristen E. Cochrane, Ivan M. Milman, Martin Oberhofer, Donald A. Padilla
-
Patent number: 8930325Abstract: According to one embodiment of the present invention, a system analyzes data in response to detecting occurrence of an event, and includes a computer system including at least one processor. The system maps fields between the data and a fingerprint definition identifying relevant fields of the data to produce a fingerprint for the data. The data is deleted after occurrence of the event. The produced fingerprint is stored in a data repository, and retrieved in response to detection of the event occurrence after the data has been deleted. The system analyzes the retrieved fingerprint to evaluate an impact of the event on corresponding deleted data. Embodiments of the present invention further include a method and computer program product for analyzing data in response to detecting occurrence of an event in substantially the same manner described above.Type: GrantFiled: February 15, 2012Date of Patent: January 6, 2015Assignee: International Business Machines CorporationInventors: Kristen E. Cochrane, Ivan M. Milman, Martin Oberhofer, Donald A. Padilla
-
Patent number: 8924333Abstract: An approach is provided for detecting an anomaly in a processing environment. The approach includes using a processor to obtain a series of values collected within a processing interval of the processor in the processing environment. The processor normalizes this first series of values to obtain a first series of normalized values. A second series of normalized values is generated by applying a predictive filter to the first series of normalized values. A comparison score is generated from the normalized values by comparing the first series of normalized values and the second series of normalized values. The approach then determines whether the comparison score represents an anomaly relative to at least one other comparison score derived from values collected within the processing interval.Type: GrantFiled: July 26, 2012Date of Patent: December 30, 2014Assignee: International Business Machines CorporationInventor: Alain E. Biem
-
Patent number: 8918371Abstract: Various of the disclosed embodiments provide systems and methods to compensate for certain event log errors. For example, when a system fails to record the occurrence of several events (a file closing, a file modification, a network socket opening, etc.) the disclosed embodiments may identify the discrepancy and provide a synthesized event sequence suitable to fulfill the purposes of the event log. In this manner, for example, a client may still be accurately billed for their use of a licensed software or system, even if their usage was punctuated with occasional failures to record their activity.Type: GrantFiled: May 27, 2014Date of Patent: December 23, 2014Assignee: Flexera Software LLCInventors: Alexander Prikhodko, David Znidarsic
-
Patent number: 8918677Abstract: A report generator of a storage area network management application includes a data validation mechanism that validates data related to managed resources operating in a storage area network. The data validation mechanism obtains first and second data sets concerning first and second characteristics of a resource operating in the storage area network and applies at least one data validation test using data sets to detect inconsistencies in data in the first and second data sets associated with the resource operating in the storage area network. Values can be compared in different columns of the same or different reports to detect report integrity errors or data mining errors. The report generator provides a storage area network management report based on data of the first data set and the second data set that accounts for inconsistencies in data associated with the resource as detected by the at least one data validation test.Type: GrantFiled: September 30, 2004Date of Patent: December 23, 2014Assignee: EMC CorporationInventors: Serge Marokhovsky, Christopher A. Chaulk, Yongmei Xu