With Power Supply Status Monitoring Patents (Class 714/22)
  • Patent number: 10481807
    Abstract: Example implementations relate to generating statuses for data images. In example implementations, an event, in response to which a save operation is initiated on a memory module, may be identified. A data image may be generated during the save operation. A status may be generated for the generated data mage. The status may include an event portion indicative of the identified event, and a completion portion indicative of whether the save operation was completed.
    Type: Grant
    Filed: December 22, 2014
    Date of Patent: November 19, 2019
    Assignee: Hewlett Packard Enterprise Development LP
    Inventors: Melvin K. Benedict, Lidia Warnes
  • Patent number: 10389247
    Abstract: A power conversion device according to one or more embodiments may include: a microcomputer; and an output circuit controlled by the microcomputer, including an output unit that converts an input power into a predetermined power and outputs the predetermined power, an internal power source that supplies a power source to the microcomputer, a driver that drives the output unit by a signal from the microcomputer, and a microcomputer stop transition unit that, when an operation of the power conversion device is stopped, outputs a microcomputer stop signal to the microcomputer and causes an operation of the microcomputer to transition to a stop state. In one or more embodiments, after the microcomputer stop transition unit causes the operation of the microcomputer to transition to a stop state, the microcomputer or the output circuit may stop an output of the internal power source.
    Type: Grant
    Filed: March 26, 2018
    Date of Patent: August 20, 2019
    Assignee: SANKEN ELECTRIC CO., LTD.
    Inventors: Junichi Takada, Mitsutomo Yoshinaga, Toshihiro Nakano, Koki Imai, Osamu Ohtake
  • Patent number: 10386264
    Abstract: A structural health monitoring module including a sensor attached to a surface of a structural member configured to convert a strain on the structural member to electric energy, a gate operationally connected to the sensor and configured to control distribution of the energy, an energy storage device operationally connected to the gate and configured to receive the energy from the sensor, a data collection device configured to receive the energy from the sensor and at least one of process and record data related to the received energy, and a data transmission device configured to wirelessly transmit data from the data collection device to an external receiver. The gate is configured to direct a portion of the energy to the storage device in a storage state and configured to direct a portion of the energy to the data collection device when in load monitoring or interrogation states.
    Type: Grant
    Filed: November 24, 2015
    Date of Patent: August 20, 2019
    Assignee: SIKORSKY AIRCRAFT CORPORATION
    Inventors: Fanping Sun, Zaffir A. Chaudhry, Avinash Sarlashkar
  • Patent number: 10353594
    Abstract: An electronic control unit for a vehicle including a nonvolatile memory capable of erasing and writing data electrically and two buffers to acquire, by communication, divided data obtained by dividing a program by predetermined size. Then, in parallel with using the two buffers alternately to receive divided data, the electronic control unit for a vehicle uses one buffer that is not used to receive divided data to write the received divided data into the nonvolatile memory.
    Type: Grant
    Filed: September 14, 2012
    Date of Patent: July 16, 2019
    Assignee: Hitachi Automotive Systems, Ltd.
    Inventors: Yusuke Abe, Koji Yuasa, Toshihisa Arai
  • Patent number: 10353375
    Abstract: A machine tool controller includes: a voltage detection unit which detects a voltage value of an input power supply; a time measurement unit which measures an occurrence time and a duration time when a voltage drop state occurs with respect to the voltage value; an abnormality determination unit which determines whether a low voltage abnormality or a power failure occurs with respect to the input power supply based on the voltage value and the duration time of the voltage drop state; a machining management unit which acquires a machining condition command and machining information of the machine tool; and a storage unit which stores the voltage value detected by the voltage detection unit, the occurrence time of the voltage drop state measured by the time measurement unit, and the machining information when the abnormality determination unit determines that the low voltage abnormality occurs with respect to the input power supply.
    Type: Grant
    Filed: June 15, 2017
    Date of Patent: July 16, 2019
    Assignee: FANUC CORPORATION
    Inventor: Shunpei Tanaka
  • Patent number: 10254353
    Abstract: A brown-out detection circuit having a time sequence control function comprises: a voltage divider (110), a reference voltage source (120), a comparator (130) and a time sequence control module (140); wherein one terminal of the voltage divider (110) is connected to an external power supply, the other terminal of the voltage divider (110) is connected to a positive input of the comparator (130), the reference voltage source (120) is connected to an inverted input of the comparator (130), the time sequence control module (140) is connected to an output of the comparator (130), an output of the time sequence control module (140) serves as an output of the brown-out detection circuit; when a duration of a power supply voltage lower than a reference voltage is not shorter than a preset time, the time sequence control module (140) controls the output of the brown-out detection circuit to be inverted from a high level to a low level.
    Type: Grant
    Filed: June 30, 2015
    Date of Patent: April 9, 2019
    Assignee: CSMC TECHNOLOGIES FABI CO., LTD.
    Inventors: Youhui Li, Xiaoli Xu
  • Patent number: 10203888
    Abstract: Technologies for performing a data copy operation on a data storage device include storing a copy token in a power-fail-safe data structure that identifies the source address and destination address of the data copy operation, updating an address table to indicate that the source and destination addresses are involved in the data copy operation, and notifying a host requesting that data copy operation that the data copy operation has been completed prior to performing the data copy operation. The host may subsequently perform other tasks while the data storage device completes the data copy operation. During the data copy operation, data access requests to the source or destination addresses are blocked based on the address table. Additionally, should a power failure event occur, the power-fail-safe data structure is saved to non-volatile data storage so that the copy operation may be completed upon the next power-on event of the data storage device.
    Type: Grant
    Filed: December 18, 2015
    Date of Patent: February 12, 2019
    Assignee: Intel Corporation
    Inventors: Sanjeev N. Trika, Anand S. Ramalingam
  • Patent number: 10126960
    Abstract: Techniques for providing data protection in an integrated circuit are provided. A method according to these techniques includes maintaining an anti-replay counter value in a volatile memory of the integrated circuit, the anti-replay counter value being associated with data stored in an off-chip, non-volatile memory in which the integrated circuit is configured to store the data, monitoring an external power source, and writing the anti-replay counter value to a programmable read-only memory of the integrated circuit responsive to a loss of power to the integrated circuit from the external power source.
    Type: Grant
    Filed: June 13, 2016
    Date of Patent: November 13, 2018
    Assignee: QUALCOMM Incorporated
    Inventors: Olivier Jean Benoit, Vincent Pierre Le Roy
  • Patent number: 10025536
    Abstract: A memory system and method for simplifying scheduling on a flash interface module and reducing latencies in a multi-die environment are provided. In one embodiment, a memory die is provided comprising a memory array, an interface, at least one register, and circuitry. The circuitry is configured to receive, via the interface, a pause command from a controller in communication with the memory die; and in response to receiving the pause command: pause a data transfer between the memory die and the controller; and while the data transfer is paused and until a resume command is received, maintain state(s) of the at least one register irrespective of inputs received via the interface that would otherwise change the state(s) of the at least one register. Other embodiments are provided.
    Type: Grant
    Filed: February 10, 2016
    Date of Patent: July 17, 2018
    Assignee: SanDisk Technologies LLC
    Inventors: Abhijeet Manohar, Hua-Ling Cynthia Hsu, Daniel E. Tuers
  • Patent number: 10019329
    Abstract: A method for providing backup power to power loads. The method includes a computer processor identifying an indication of a power failure to a computing system. The method further includes identifying a first active power load that is imposed on the computing system by one or more computing devices in the computing system. The method further includes responding to the power failure by activating a first IPU that is connected to the first active power load, identifying a power duration threshold for the first active power load, and determining whether a duration of power stored in the first IPU is less than the identified power duration. The method further includes responding to the determination that the duration of power stored in the first IPU is less than the identified power duration threshold of the first active power load by initiating a shutdown protocol for the first active power load.
    Type: Grant
    Filed: May 5, 2016
    Date of Patent: July 10, 2018
    Assignee: International Business Machines Corporation
    Inventors: Peter W. Kelly, Shankar K M, Mahendra Krishna Mavilla Venkata, Kiruthikalakshmi Periasamy
  • Patent number: 9939867
    Abstract: An apparatus includes a plurality of components and a plurality of component controllers. Each of the plurality of component controllers is associated with at least one component of the plurality of components. Each component controller is configured to compute a local power budget for the at least one component based, at least in part, on the power differential and the proportion of the total power consumption corresponding to the at least one component. A service processor is configured to determine failure associated with at least one component controller of the plurality of component controllers or the at least one component associated with the at least one component controller. The service processor is configured to in response to a reset threshold not being exceeded, reset the at least one component controller without interrupting operations of any components of the at least one component that have not failed.
    Type: Grant
    Filed: June 29, 2015
    Date of Patent: April 10, 2018
    Assignee: International Business Machines Corporation
    Inventors: Malcolm S. Allen-Ware, Martha Ann Broyles, Glenn Rueban Miles, Todd Jon Rosedahl, Guillermo Jesus Silva, Gregory Scott Still
  • Patent number: 9935563
    Abstract: An apparatus for installation within a tire for a vehicle includes a flexible arm and a power generating element coupled to the flexible arm for generating electrical energy. One end of the flexible arm is coupled to a rim of the tire. The opposing end of the flexible arm is configured to be in contact with the inside tread surface of the tire. The flexible arm is capable of deformation in response to a variability of distance between the rim and the inside tread surface during rolling movement of the tire, and the power generating element generates the electrical energy in response to deformation of the flexible arm. The apparatus may be combined with a tire pressure sensor module as a system so as to provide electrical energy for powering the tire pressure sensor module.
    Type: Grant
    Filed: August 5, 2015
    Date of Patent: April 3, 2018
    Assignee: NXP USA, Inc.
    Inventors: John J. Tatarchuk, Matthew W. Muddiman
  • Patent number: 9927856
    Abstract: Component power consumption is collected from each of a plurality of controllers of a node having a plurality of components. The component power consumption is provided to each of the plurality of controllers. A power differential is determined as a difference between a power cap for an apparatus and a total power consumption for the apparatus based, at least in part, on the component power consumption. A proportion of the total power consumption corresponding to the at least one component associated with the at least one component controller is determined. A local power budget is computed for the at least one component based, at least in part, on the power differential and the proportion of the total power consumption corresponding to the at least one component. A failure associated with the at least one component controller or the at least one component is determined.
    Type: Grant
    Filed: August 24, 2015
    Date of Patent: March 27, 2018
    Assignee: International Business Machines Corporation
    Inventors: Malcolm S. Allen-Ware, Martha Ann Broyles, Glenn Rueban Miles, Todd Jon Rosedahl, Guillermo Jesus Silva, Gregory Scott Still
  • Patent number: 9921896
    Abstract: A memory apparatus and methods are provided for preventing read errors on weak pages in a non-volatile memory system. In one example, a method includes identifying a weak page in a non-volatile memory device along a word line, wherein the weak page is partially written with at least some data; buffering data associated with the weak page to a weak page buffer that is coupled in communication with the non-volatile memory device; determining that an amount of data in the weak page buffer has reached a predetermined data level; and writing the data from the weak page buffer into the weak page along the word line in the non-volatile memory device.
    Type: Grant
    Filed: February 10, 2014
    Date of Patent: March 20, 2018
    Assignee: Virident Systems, LLC
    Inventors: Ashwin Narasimha, Vibhor Patale, Sandeep Sharma, Ajith Kumar Battaje
  • Patent number: 9866369
    Abstract: A beacon includes an infrared emitter configured to emit beacon signals; an infrared-link emitter configured to emit infrared-link signals having a wavelength different from that of the beacon signals; an infrared-link detector configured to detect infrared-link signals; a memory configured to store a delay time; a clock configured to generate a clock cycle signal; and a microcontroller configured to, in response to receiving an infrared-link signal including a signaling code and clock synchronization data from an external beacon: adjust the clock to be synchronized with a clock of the external beacon; store the signaling code in the memory; and when the clock cycle signal generated by the clock indicates that it is a starting time of a clock cycle period, control the infrared emitter to emit a beacon signal including the signaling code with the delay time relative to the starting time of the clock cycle period.
    Type: Grant
    Filed: August 18, 2016
    Date of Patent: January 9, 2018
    Assignee: Cejay Engineering, LLC
    Inventors: Derek Haynes, Guido Albert Lemke, Mark Haynes
  • Patent number: 9851767
    Abstract: Multiple processor systems are provided. A first processor is configured to monitor the state of at least one other processor by comparing received signals. When the first processor determines that another processor needs to be reset, the first processor provides a reset signal to a reset pin of the processor that needs to be reset. The first processor may reset itself after providing the reset signal.
    Type: Grant
    Filed: October 2, 2015
    Date of Patent: December 26, 2017
    Assignee: NIKE, Inc.
    Inventors: James Bielman, Kate Cummings, Edward Stephen Lowe, Jr.
  • Patent number: 9818337
    Abstract: The current disclosure provides an LED display control circuit. The control circuit has a device configured to separate a first PWM data into LSB data and MSB data. The control circuit also comprises a LSB circuit coupled to a plurality of LED channels. The LSB circuit is configured to supply LSB data to each of the plurality of LED channels.
    Type: Grant
    Filed: July 24, 2014
    Date of Patent: November 14, 2017
    Assignee: SCT TECHNOLOGY, LTD.
    Inventors: Eric Li, Shang-Kuan Tang, Wenjie Yang, Yutao Chen, Tianqi Qiu, Jun Tian, Hui Li
  • Patent number: 9778861
    Abstract: A method for controlling flash memory is described. The method includes selecting a new forward error correction (FEC) parameter set that provides more redundancy than a current FEC parameter set. The method also includes coding source information bits, using the new FEC parameter set, during write operations to a first corrupted page in the flash memory. The method further includes mapping the first corrupted page and at least one additional corrupted page in the flash memory to a single logical page with an expected page size.
    Type: Grant
    Filed: October 14, 2015
    Date of Patent: October 3, 2017
    Assignee: QUALCOMM Incorporated
    Inventor: Yinian Mao
  • Patent number: 9740276
    Abstract: There are provided n (n is an integer greater than or equal to 2) physical layer control units which communicate with another apparatus connected to a device itself and control a physical layer, a logical layer control unit which controls a logical layer in communication with the other apparatus, and a control unit which controls the logical layer control unit from a power-supply ON state to a standby state in accordance with a standby instruction for the device itself, wherein one physical layer control unit of the n physical layer control units generates a clock using a connected resonator and the other physical layer control units receive the clock generated by the physical layer control unit to which the resonator is connected.
    Type: Grant
    Filed: February 12, 2013
    Date of Patent: August 22, 2017
    Assignee: NEC DISPLAY SOLUTIONS, LTD.
    Inventor: Kenji Yamamoto
  • Patent number: 9720475
    Abstract: An information processing system includes a receiving unit that receives user operation; a setting unit that holds association information in which pieces of necessity information each indicating necessity of a shutdown process indicating a process required for stopping power supply to a corresponding device are associated with a plurality of devices, respectively; a first instruction unit that instructs a target device for which the power supply is to be stopped to perform the shutdown process when the receiving unit receives operation to stop the power supply and the target device requires the shutdown process based on the association information; and a second instruction unit that instructs a power supply control device that controls execution or stop of the power supply to the target device to stop the power supply to the target device when the shutdown process of the target device is completed.
    Type: Grant
    Filed: August 25, 2014
    Date of Patent: August 1, 2017
    Assignee: RICOH COMPANY, LTD.
    Inventor: Keisuke Iwasa
  • Patent number: 9660993
    Abstract: Particular embodiments may receive and log information related to one or more events occurring on one or more client computing devices associated with a user. An event may comprise a restriction of a user action on a social-networking system, the restriction comprising the social-networking system blocking the user from performing the user action. An event may comprise a login issue associated with logging in to the social-networking system. An event may comprise a system or device error. System errors may comprise events originating from a third-party system. For each event, an indication of the event and at least one user-activatable reference may be provided for display to the user. A control action may then be determined for the event in response to a user selection of the user-activatable reference. An interface may provide third parties with a view of a user's events as well as functionality to effect control actions.
    Type: Grant
    Filed: October 25, 2012
    Date of Patent: May 23, 2017
    Assignee: Facebook, Inc.
    Inventors: Jacob Andrew Brill, Daniel Gregory Muriello, Andrew Bartholomew
  • Patent number: 9606951
    Abstract: An interface controller, coupling a device main body of an external electronic device to a host, is disclosed, which transmits a termination-on signal to the host prior to a mechanically stable state of a device main body of the external electronic device. When the device main body has not reached the mechanically stable state yet, the interface controller responds to the host with default link information in a delayed manner. The default link information is contained in the interface controller. When the device main body reaches the mechanically stable state, the interface controller transmits specific link information retrieved from the device main body to the host.
    Type: Grant
    Filed: January 10, 2014
    Date of Patent: March 28, 2017
    Assignee: VIA TECHNOLOGIES, INC.
    Inventor: Chia-Ying Kuo
  • Patent number: 9588565
    Abstract: Example embodiments of the present invention relate to a method, an apparatus, and a computer program product for providing secondary power to allow shutdown of a device during a power loss. The method includes monitoring an input power attribute for a data storage device. Upon detection of an anomaly in the input power attribute for the data storage device indicative of a power loss, the method includes providing secondary power to the data storage device for temporary operation of the device to power down.
    Type: Grant
    Filed: June 28, 2013
    Date of Patent: March 7, 2017
    Assignee: EMC IP Holding Company LLC
    Inventors: Jason A. Harland, Joseph E. Fenton, Adrianus Djohan, Paul F. Provost
  • Patent number: 9575686
    Abstract: The present invention is directed to computer storage systems and methods thereof. More specifically, embodiments of the present invention provide an isolated storage control system that includes both a non-volatile memory and a volatile memory. The non-volatile memory comprises a data area and a metadata area. In power failure or similar situations, content of the volatile memory is copied to the data area of the non-volatile memory, and various system parameters are stored at the metadata area. When the system restores its operation, the information at the metadata area is processed, and the content stored at the data area of the non-volatile memory is copied to the volatile memory. There are other embodiments as well.
    Type: Grant
    Filed: April 25, 2016
    Date of Patent: February 21, 2017
    Assignee: RAMBUS INC.
    Inventors: Shih-ho Wu, Christopher Haywood
  • Patent number: 9544647
    Abstract: An advertisement system includes an advertising manager that receives a content-event indicator, which indicates playback of an advertisement for viewing on a first display screen at a media-playback device or indicates playback of recorded content that includes advertisements. The advertising manager can determine an optimal time offset as a duration of time before or after playback of an advertisement to the start of an event that is associated with the advertisement for viewing on a second display screen at a mobile device. For recorded content, an optimization schedule is determined that replaces and time-shifts advertisements during playback of the recorded content. The advertising manager can also determine a fulfillment criterion for a product or service based on latency constraints to indicate a duration of time within which fulfillment of the product or service is expected when offered as a second advertisement corresponding to a first advertisement.
    Type: Grant
    Filed: November 21, 2012
    Date of Patent: January 10, 2017
    Assignee: Google Technology Holdings LLC
    Inventors: Nitya Narasimhan, Venugopal Vasudevan, Jehan Wickramasuriya, Joseph F. Wodka
  • Patent number: 9507827
    Abstract: In one embodiment, a data structure comprises: a primary index comprising one or more position-block references; and one or more position blocks sequentially following the primary index, wherein: each one of the position-block references corresponds to one of the position blocks; and each one of the position blocks comprises: a secondary index comprising one or more position-data references; and one or more sets of positions sequentially following the secondary index, wherein each one of the position-data references corresponds to of one of the sets of positions in the position block. In one embodiment, an instance of the data structure is stored in a computer-readable memory and accessible by an application executed by a process.
    Type: Grant
    Filed: June 30, 2011
    Date of Patent: November 29, 2016
    Assignee: EXCALIBUR IP, LLC
    Inventor: Tomi Poutanen
  • Patent number: 9448896
    Abstract: Torn write mitigation circuitry determines if a write operation to memory is in progress at or about a time of power loss. In response to the write operation being in progress at or about the time of the power loss, the torn write mitigation circuitry causes torn write data and metadata to be stored to a non-volatile cache. The torn write data comprise data left in a degraded or uncorrectable state as a result of the loss of power. The metadata describe the torn write data.
    Type: Grant
    Filed: August 7, 2013
    Date of Patent: September 20, 2016
    Assignee: SEAGATE TECHNOLOGY LLC
    Inventors: Mark Allen Gaertner, Jon Trantham, Vidya Krishnamurthy, Steve Faulhaber, Yong Yang
  • Patent number: 9429630
    Abstract: A BIST circuit is provided for testing the status of power supplies in an integrated circuit in multiple power modes including multiple circuit blocks. The BIST circuit includes a finite state machine (FSM), power monitors and a comparator. The FSM sequentially enables at least two power mode states in a predetermined order. In each power mode state, the FSM outputs power mode signals to enable the power supplies used in the corresponding power mode. Each power monitor is connected to a power input node of one of the circuit blocks, and outputs a monitor signal indicative of the voltage at the corresponding power input node when the corresponding power supply is enabled. The comparator compares each monitor signal with a corresponding reference signal and generates a set of power supply status signals.
    Type: Grant
    Filed: September 23, 2014
    Date of Patent: August 30, 2016
    Assignee: Freescale Semiconductor, Inc.
    Inventors: Yong Zhu, Shayan Zhang
  • Patent number: 9424127
    Abstract: Aspects of charger detection and optimization prior to host control are described herein. In various embodiments, a condition of whether reverse current is present on a system bus is detected. When the condition for reverse current is present, reverse current is sunk by one or more of various reverse current sink circuits. By relying upon one or more of the reverse current sink circuits, for safety, to address or mitigate the condition for reverse current, a detector may be able to identify or distinguish among several different types of charger or charging ports coupled to a system bus allowing a charger to be selected optimally. Further, an indicator of the type of charger or charging port coupled to the system bus is communicated over a single pin interface, for backwards compatibility with circuits capable of identifying between only two different types of chargers.
    Type: Grant
    Filed: July 25, 2013
    Date of Patent: August 23, 2016
    Assignee: BROADCOM CORPORATION
    Inventors: Walid Nabhane, Mark D Rutherford, Narayan Prasad Ramachandran, David Chang, Yi Ting Chen, Chenmin Zhang, Ajmal A. Godil
  • Patent number: 9402568
    Abstract: A device monitors sensor data generated by movement of a wearer and determines whether the data indicates a fall. The device may include accelerometers, barometer(s), and sensors that detect, light, sound, temperature, magnetic and electric fields, strain-force on the device, and other environmental conditions. A processor determines whether the data meets a first criterion for a parameter (i.e., exceeding an acceleration or barometric pressure maximum threshold). The first criterion corresponds to a first set of known-fall event data sets. If the first criterion is met, the processor generates a full indication. If the data does not meet the first criterion, the processor compares the data to a second criterion for the same, or different, parameter. If the second parameter is met, further processing confirms a fall determination by comparing the data to other criteria corresponding to known-fall event data sets that differ from the first set.
    Type: Grant
    Filed: August 29, 2012
    Date of Patent: August 2, 2016
    Assignee: Verizon Telematics Inc.
    Inventor: James R. Barfield
  • Patent number: 9384078
    Abstract: A method for diagnosing a mechanism of untimely cut-offs of the power supply to a motor vehicle computer (1) which is programmed to execute a startup routine when woken up and a shutdown routine before being put into sleep mode, includes, at the time of each shutdown routine, generating and storing in storage elements a marker representing a completed execution of the shutdown routine, and at the time of each startup routine, checking for the presence of a marker, and if the marker is present, reinitializing the storage elements of the marker, and if the marker is absent, generating a data element representing a power supply fault.
    Type: Grant
    Filed: July 19, 2013
    Date of Patent: July 5, 2016
    Assignees: CONTINENTAL AUTOMOTIVE FRANCE, CONTINENTAL AUTOMOTIVE GMBH
    Inventor: Stephane Eloy
  • Patent number: 9372519
    Abstract: According to one embodiment, a method for dynamically sharing power grids of a device includes providing power from a first power supply to a first power grid in a first component of the device. The method also includes providing power from a second power supply to a second power grid in a second component of the device and dynamically changing, by a controller, a state of a first switch that controls a sharing of power between the first power grid and the second power grid during a runtime of the device.
    Type: Grant
    Filed: March 6, 2013
    Date of Patent: June 21, 2016
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Pradip Bose, Alper Buyuktosunoglu, Hans M. Jacobson
  • Patent number: 9348705
    Abstract: The present invention is directed to computer storage systems and methods thereof. More specifically, embodiments of the present invention provide an isolated storage control system that includes both a non-volatile memory and a volatile memory. The non-volatile memory comprises a data area and a metadata area. In power failure or similar situations, content of the volatile memory is copied to the data area of the non-volatile memory, and various system parameters are stored at the metadata area. When the system restores its operation, the information at the metadata area is processed, and the content stored at the data area of the non-volatile memory is copied to the volatile memory. There are other embodiments as well.
    Type: Grant
    Filed: June 26, 2014
    Date of Patent: May 24, 2016
    Assignee: INPHI CORPORATION
    Inventors: Shih-Ho Wu, Christopher Haywood
  • Patent number: 9336089
    Abstract: A processing apparatus includes a first memory, a second memory, a capacitor, and a processor coupled to the first memory and the second memory. The processor is configured to cause power feeding from the capacitor, and execute a first processing to cause the first memory to hold data, after the power feeding is caused from the capacitor, cause a battery to start power feeding in at least one of a case where the power feeding from an external power source is not started after being halted and an output voltage of the capacitor has fallen below a first value, and a case where the power feeding from the external power source is not started after being halted and a first time period has elapsed, and execute a second processing to write the data from the first memory into the second memory during the power feeding from the battery.
    Type: Grant
    Filed: April 10, 2014
    Date of Patent: May 10, 2016
    Assignee: FUJITSU LIMITED
    Inventors: Kentarou Yuasa, Takanori Ishii
  • Patent number: 9335809
    Abstract: Apparatus and method for operating a device in a low power mode. In accordance with some embodiments, the apparatus comprises a memory and a system on chip (SOC) integrated circuit. The SOC has a first region with a processing core and a second region electrically isolated from the first region as an always on domain power island with a power control block. In response to a sleep command, the processing core transfers system data to the memory and the power control block enters a low power mode in which no electrical power is supplied to the first region. In response to a wake up command, power is restored to the first region and the processing core performs a reinitialization operation responsive to status information communicated by the power control block indicative of a state of the system during the low power mode.
    Type: Grant
    Filed: March 15, 2013
    Date of Patent: May 10, 2016
    Assignee: Seagate Technology LLC
    Inventor: Scott Thomas Younger
  • Patent number: 9304562
    Abstract: A server rack system including a plurality of power supply units, a monitoring circuit, a rack management controller (RMC), and a plurality of server nodes is provided. The monitoring circuit is for monitoring the power supply units. The RMC is for monitoring the power supply units. When the monitoring circuit and/or the RMC finds that at least one of the power supply units failed to output a normal voltage, an operation status of the server nodes is lowered or at least one of the server nodes is forcibly shut down.
    Type: Grant
    Filed: August 10, 2012
    Date of Patent: April 5, 2016
    Assignee: Quanta Computer Inc.
    Inventors: Maw-Zan Jau, Wei-Yi Chu, Ting-Chen Ko, Li-Ching Chi, Wei-Kai Chao
  • Patent number: 9305662
    Abstract: An identification technique for physically damaged blocks of a flash memory of a data storage device. In the data storage device, a controller coupled to the flash memory writes data into the flash memory with at least one time stamp corresponding to the data. The time stamp is taken into consideration by the controller to identify the physically damaged blocks of the flash memory, and thereby it is prevented from erroneously identifying a physically undamaged block as bad. Thus, the flash memory is prevented from being erroneously regarded as a write protected memory. The lifespan of the flash memory is effectively prolonged.
    Type: Grant
    Filed: June 27, 2014
    Date of Patent: April 5, 2016
    Assignee: VIA TECHNOLOGIES, INC.
    Inventors: Chin-Yin Tsai, Yi-Lin Lai
  • Patent number: 9298234
    Abstract: According to one embodiment, a method for dynamically sharing power grids of a device includes providing power from a first power supply to a first power grid in a first component of the device. The method also includes providing power from a second power supply to a second power grid in a second component of the device and dynamically changing, by a controller, a state of a first switch that controls a sharing of power between the first power grid and the second power grid during a runtime of the device.
    Type: Grant
    Filed: November 27, 2012
    Date of Patent: March 29, 2016
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Pradip Bose, Alper Buyuktosunoglu, Hans M. Jacobson
  • Patent number: 9292076
    Abstract: Fast recalibration circuitry for input/output (IO) compensation finite state machine power-down exit is described. The fast recalibration circuitry includes a finite state machine having a volatile memory to store an IO compensation setting and a power supply coupled to the volatile memory to provide power to the volatile memory. The fast recalibration circuitry includes a persistent memory coupled to the volatile memory and one or more circuits, coupled to the volatile memory and the persistent memory, to identify an event to enter a power-down mode, wherein the power-down mode comprises the power supply removing power from the volatile memory and transfer the IO compensation setting in the volatile memory to the persistent memory prior to the power supply removing the power from the volatile memory.
    Type: Grant
    Filed: September 16, 2013
    Date of Patent: March 22, 2016
    Assignee: Intel Corporation
    Inventors: Todd W. Mellinger, Nicholas J. Denier
  • Patent number: 9251047
    Abstract: Approaches for automatically backing up data from volatile memory to persistent storage in the event of a power outage, blackout or other such failure are described. The approaches can be implemented on a computing device that includes a motherboard, central processing unit (CPU) a main power source, volatile memory (e.g., random access memory (RAM)), an alternate power source and circuitry (e.g., a specialized application-specific integrated circuit (ASIC)) for performing the backup of volatile memory to a persistent storage device. In the event of a power failure of the main power source, the alternate power source is configured to supply power to the specialized ASIC for backing up the data in the volatile memory. For example, when power failure is detected, the ASIC can read the data from the DIMM socket using power supplied from the alternate power source and write that data to a persistent storage device.
    Type: Grant
    Filed: May 13, 2013
    Date of Patent: February 2, 2016
    Assignee: Amazon Technologies, Inc.
    Inventors: Samuel James McKelvie, Michael David Marr
  • Patent number: 9190107
    Abstract: An information recording device includes a recording medium in which renewal data, which is a target of a data refresh operation, is recorded, a reading module that reads the renewal data recorded in the recording medium, a renewal module that performs updating of a value indicating a state of the data refresh operation, a generation module that generates parity data based on the value and the read renewal data, and a recording module that records the renewal data after recording the generated parity data.
    Type: Grant
    Filed: February 27, 2013
    Date of Patent: November 17, 2015
    Assignee: Kabushiki Kaisha Toshiba
    Inventor: Osamu Yoshida
  • Patent number: 9189057
    Abstract: An apparatus, method, and program product for optimizing core performance and power in a multi-core processor. The apparatus includes a multi-core processor coupled to a clock source providing a clock frequency to one or more cores, an independent power supply coupled to each core for providing a supply voltage to each core and a Phase-Locked Loop (PLL) circuit coupled to each core for dynamically adjusting the clock frequency provided to each core. The apparatus further includes a controller coupled to each core and being configured to collect performance data and power consumption data measured for each core and to adjust, using the PLL circuit, a supply voltage provided to a core, such that, the operational core frequency of the core is greater than a specification core frequency preset for the core and, such that, core performance and power consumption is optimized.
    Type: Grant
    Filed: September 30, 2013
    Date of Patent: November 17, 2015
    Assignee: International Business Machines Corporation
    Inventors: Daeik Kim, Jonghae Kim, Moon J. Kim, James R. Moulic
  • Patent number: 9182796
    Abstract: When the first time has elapsed after the operator operates a power switch to stop power supply, an image processing apparatus forcibly stops power supply. When stopping power supply, the image processing apparatus executes hibernation processing to retract, in a secondary storage device, the stored content of a main memory used as a work area by a CPU. When the hibernation processing will be completed within a target time necessary to complete the hibernation processing and end processing of the image processing apparatus before the first time elapses, the image processing apparatus executes the end processing of the image processing apparatus and stops power supply after completing the hibernation processing; otherwise, the image processing apparatus interrupts the hibernation processing, executes the end processing of the image processing apparatus, and stops power supply.
    Type: Grant
    Filed: November 26, 2012
    Date of Patent: November 10, 2015
    Assignee: CANON KABUSHIKI KAISHA
    Inventor: Kenji Hara
  • Patent number: 9170621
    Abstract: A power supply device is provided. The power supply device provides a maintenance voltage at an output terminal to a system chip of a system and includes a first battery, a capacitor, a charging circuit, and a monitoring circuit. The first battery provides a battery voltage. The capacitor stores a capacitor voltage. The charging circuit is coupled to the capacitor. The monitoring circuit detects whether the battery voltage is less than a first threshold and whether the capacitor voltage is larger than a second threshold and generates a control signal according to the determination result. When the monitoring circuit detects that the battery voltage is less than the first threshold and the capacitor voltage is not larger than the second threshold, the monitoring circuit asserts the control signal to control the charging circuit to charge the capacitor.
    Type: Grant
    Filed: February 8, 2012
    Date of Patent: October 27, 2015
    Assignee: WISTRON CORP.
    Inventor: Po-Chuan Chen
  • Patent number: 9129067
    Abstract: In a position detector for detecting a position of a detection body, a signal processing circuit processes a signal outputted from a magnetic field detection element. A first storage circuit stores the signal outputted from the magnetic field detection element and outputs a signal to an external device through an output circuit in a normal operation mode. A second storage circuit stores an output value of the first storage circuit. When a malfunction determination circuit determines an instantaneous power interruption mode, a signal route changing circuit prevents a signal transmission between the first storage circuit and the second storage circuit and a signal transmission between the first storage circuit and the output circuit, prevents the second storage circuit from updating data for a certain period of time, and permits the second storage circuit in which updating is prevented to output a signal to the output circuit.
    Type: Grant
    Filed: November 21, 2012
    Date of Patent: September 8, 2015
    Assignee: DENSO CORPORATION
    Inventors: Takamitsu Kubota, Tohru Shimizu, Tetsuya Hara, Yoshiyuki Kono
  • Patent number: 9086463
    Abstract: A power supply apparatus includes a secondary battery and a timer unit for measuring a time required to charge the secondary battery from a first State Of Charge (SOC) to a second SOC, or a time required to discharge the second battery from the second SOC to the first SOC. The power supply apparatus further includes a determination unit for determining a degraded state of the secondary battery based on results of the measurement by the timer unit.
    Type: Grant
    Filed: October 20, 2010
    Date of Patent: July 21, 2015
    Assignee: PANASONIC INTELLECTUAL PROPERTY MANAGEMENT CO., LTD.
    Inventor: Hideki Tamura
  • Patent number: 9082472
    Abstract: Battery backup devices and methods of performing a backup operation using the same are provided. A battery backup device can include a partial battery power controller configured to shut off power to components to be backed up one by one as data backup is completed on each device. The battery backup devices and methods provided can efficiently utilize battery power such that power consumption and charging time can be reduced.
    Type: Grant
    Filed: November 15, 2012
    Date of Patent: July 14, 2015
    Assignee: TAEJIN INFO TECH CO., LTD.
    Inventor: Hyukjong Ahn
  • Patent number: 9075546
    Abstract: Power supply device and an image forming apparatus having the power supply device are provided. The power supply device includes an input unit to input alternating current (AC) power, a converter to convert the input AC power to direct current (DC) power having a preset level and to output the DC power, and a sensor to be connected to the input unit in parallel and to sense whether the AC power has been input. The sensor includes a transformer to receive the AC power and to output a sensing signal having a level reduced more than a level of the AC power, and a resistor unit connected to the transformer in series so that a current of the AC power input into the transformer is lower than or equal to a preset current.
    Type: Grant
    Filed: November 26, 2012
    Date of Patent: July 7, 2015
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventor: An-sik Jeong
  • Publication number: 20150149825
    Abstract: The various embodiments described herein include systems, methods and/or devices used to enable power fail latching based on monitoring multiple power supply voltages in a storage device. In one aspect, the method includes: (1) determining whether a first power supply voltage provided to the storage device is out of range for a first time period, (2) determining whether a second power supply voltage provided to the storage device is out of range for a second time period, and (3) in accordance with a determination that at least one of the first power supply voltage is out of range for the first time period and the second power supply voltage is out of range for the second time period, latching a power fail condition.
    Type: Application
    Filed: December 19, 2013
    Publication date: May 28, 2015
    Applicant: SanDisk Enterprise IP LLC
    Inventors: Gregg S. Lucas, Kenneth B. Delpapa, Robert W. Ellis
  • Patent number: 9043642
    Abstract: Disclosed is a power isolation and backup system. When a power fail condition is detected, temporary storage is flushed to an SDRAM. After the flush, interfaces are halted, and power is removed from most of the chip except the SDRAM subsystem. The SDRAM subsystem copies data from an SDRAM to a flash memory. On the way, the data may be encrypted, and/or a data integrity signature calculated. To restore data, the SDRAM subsystem copies data from the flash memory to the SDRAM. On the way, the data being restored may be decrypted, and/or a data integrity signature checked.
    Type: Grant
    Filed: April 8, 2011
    Date of Patent: May 26, 2015
    Assignee: Avago Technologies General IP Singapore) Pte Ltd
    Inventors: Peter B. Chon, James Yu, David M. Olson, Timothy E. Hoglund, Gary J. Piccirillo