Skew Detection Correction Patents (Class 714/700)
  • Patent number: 10827333
    Abstract: A power saving wire-free earpiece has a Bluetooth transceiver and a Bluetooth Low Energy (BLE) transceiver. A stream of audio from a remote source is separated into a local audio stream and a stream sent to the BLE transceiver for a remote earpiece. The earpiece is operative in a first and second mode, the first mode enabling the BT transceiver and BLE transceiver, the second mode enabling only the BLE transceiver for receiving remote streams of data. The first and second mode alternate so that the local and remote earpiece have substantially uniform current requirements.
    Type: Grant
    Filed: June 14, 2019
    Date of Patent: November 3, 2020
    Assignee: Silicon Laboratories Inc.
    Inventor: Partha Sarathy Murali
  • Patent number: 10749663
    Abstract: The disclosed systems, structures, and methods are directed to a two wire-based clock multiplication unit (CMU), employing a first phase lock loop (PLL) configured to generate a first high-speed clock frequency f1 encoded in differential mode, a second PLL configured to generate a second high-speed clock frequency f2 encoded in common mode, and a summer configured to combine the differential mode encoding the first high-speed clock frequency f1 and the common mode encoding the second high-speed clock frequency f2 and transmit the combined differential and common mode high-speed clock frequencies on a two wire-based conductor bus. In addition, systems, structures, and methods directed to a two wire-based clock recovery module and a two wire-based clock recovery module have also been disclosed.
    Type: Grant
    Filed: September 10, 2019
    Date of Patent: August 18, 2020
    Assignee: HUAWEI TECHNOLOGIES CO., LTD.
    Inventors: Marc-Andre Lacroix, MohammadMahdi Mohsenpour
  • Patent number: 10718812
    Abstract: Techniques and mechanisms to exchange test, debug or trace (TDT) information via a general purpose input/output (I/O) interface. In an embodiment, an I/O interface of a device is coupled to an external TDT unit, wherein the I/O interface is compatible with an interconnect standard that supports communication of data other than any test information, debug information or trace information. One or more circuit components reside on the device or are otherwise coupled to the external TDT unit via the I/O interface. Information exchanged via the I/O interface is generated by, or results in, the performance of one or more TDT operations to evaluate the one or more circuit components. In another embodiment, the glue logic of the device interfaces the I/O interface with a test access point that is coupled between the one or more circuit components and the I/O interface.
    Type: Grant
    Filed: August 20, 2018
    Date of Patent: July 21, 2020
    Assignee: Intel IP Corporation
    Inventors: Rolf H. Kuehnis, Sankaran M. Menon, Patrik Eder
  • Patent number: 10686583
    Abstract: Generating, during a first and second signaling interval, an aggregated data signal by forming a linear combination of wire signals received in parallel from wires of a multi-wire bus, wherein at least some of the wire signals undergo a signal level transition during the first and second signaling interval; measuring a signal skew characteristic of the aggregated data signal; and, generating wire-specific skew offset metrics, each wire-specific skew offset metric based on the signal skew characteristic.
    Type: Grant
    Filed: July 4, 2017
    Date of Patent: June 16, 2020
    Assignee: KANDOU LABS, S.A.
    Inventors: Roger Ulrich, Armin Tajalli, Ali Hormati, Richard Simpson
  • Patent number: 10631248
    Abstract: Changes in operating conditions, like voltage or temperature, can cause the frequency of an internal clock signal to change and negatively affect device operation. In one embodiment, a method for controlling internal clock frequency of a device includes counting a number of clock cycles of the internal clock signal relative to a current period of a system clock signal to determine a current mid-cycle count of clock cycles, wherein the internal clock signal is based on a first clock signal of a plurality of clock signals produced in the device, each having a different frequency. When the current mid-cycle count is differs from a calibrated mid-cycle count by more than a tolerable amount, a second clock signal of the plurality of clock signals is selected as the internal clock signal.
    Type: Grant
    Filed: May 30, 2017
    Date of Patent: April 21, 2020
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Anand Seshadri, Hugh P McAdams
  • Patent number: 10554444
    Abstract: A method for operating a bus system in which a message of the bus system is received and its validity is ascertained, characterized in that, when it has been ascertained that the message is “not valid”, a defend message is transmitted to a designated recipient of the message, the defend message being configured so that the designated recipient is instructed by way of the defend message to initiate defensive measures against the message.
    Type: Grant
    Filed: July 7, 2017
    Date of Patent: February 4, 2020
    Assignee: Robert Bosch GmbH
    Inventors: Antonio La Marca, Joachim Steinmetz, Liem Dang, Marco Neumann, Benjamin Herrmann, Michael Beuten
  • Patent number: 10536165
    Abstract: In certain aspects, a serial-to-parallel converter includes multiple cascaded stages configured to convert a serial data stream into multiple parallel data signals, wherein each of the stages includes one or more demultiplexers. The serial-to-parallel converter also includes demultiplexer control circuits, wherein each of the demultiplexer control circuits is coupled to the one or more demultiplexers of a respective one of the stages, and a pattern detector coupled to the demultiplexer control circuits.
    Type: Grant
    Filed: February 20, 2019
    Date of Patent: January 14, 2020
    Assignee: QUALCOMM Incorporated
    Inventors: Anand Gaurav, Bo Sun
  • Patent number: 10469199
    Abstract: A test instrument or host device can apply inverse transmitter and receiver functions to data transmitted or received by an electrical and optical transponder. The inverse transmitter and receiver functions are applied to counteract internal signal conversion processes of the transponder. Forward error correction and test pattern analysis may be performed on signals received from the transponder after the inverse receiver function is applied to the received signals.
    Type: Grant
    Filed: September 9, 2016
    Date of Patent: November 5, 2019
    Assignee: VIAVI SOLUTIONS INC.
    Inventor: Andrew Neal
  • Patent number: 10440446
    Abstract: The invention relates to a method for generating haptic coefficients associated with an audiovisual document. Initially, data is extracted from an audio and/or video track and is used to calculate at least one first group of haptic coefficients from an autoregressive model applied to the read data. These haptic coefficients are designed to program a filter supplying at the output the control parameters for controlling at least one haptic actuator. Then, a “haptic” sequence of the audiovisual document is determined and calculated haptic parameters are associated with the determined sequence. In this manner, the haptic parameters enabling the control of one or more actuators are easily calculated and easily reproducible. Advantageously, the data used for the calculation is extracted from the selected sequence.
    Type: Grant
    Filed: November 21, 2014
    Date of Patent: October 8, 2019
    Assignee: INTERDIGITAL CE PATENT HOLDINGS
    Inventors: Julien Fleureau, Fabien Danieau, Philippe Guillotel
  • Patent number: 10425161
    Abstract: Enabling Low Frequency Periodic Signalling over an optical link with a circuit arrangement and method for controlling a light-emitting component, including: monitoring a differential input for the presence of an electrical idle state by an IDLE detector; triggering a time delay block by the IDLE detector when the electrical idle state at the differential input is interrupted or resumed; detecting whether the differential input is driven by a Low Frequency Periodic Signalling or by a Super Speed/Enhanced Super Speed signalling by a signal type detector; making a decision whether the signalling is to be transmitted by a decision circuit; an input stage connected to the decision circuit; and driving the light-emitting component by an output stage.
    Type: Grant
    Filed: September 30, 2016
    Date of Patent: September 24, 2019
    Assignee: Silicon Line GmbH
    Inventors: Martin Groepl, Holger Hoeltke
  • Patent number: 10381929
    Abstract: A power-delivery system may comprise a load device and a direct-current converter configured to deliver current to the load device when the direct-current converter is in an on state. The power-deliver system may comprise a voltage-measurement system configured to measure, at a beginning of each measurement cycle in a cyclic measurement pattern, a voltage at the load device. The power-deliver system may comprise a power controller configure to receive, at the beginning of each measurement cycle, the measurement of the voltage, and to perform, at the beginning of a control cycle in a cyclic control pattern, a voltage-control decision in response to a change in the measurement of the voltage being below a voltage-change threshold. The voltage-control decision may comprise whether to switch the state of the first direct-current converter. The cyclic control pattern may operate at a first frequency, and the measurement pattern may operate at a second frequency.
    Type: Grant
    Filed: August 24, 2018
    Date of Patent: August 13, 2019
    Assignee: International Business Machines Corporation
    Inventors: Andrew Ferencz, Todd E. Takken, Paul W. Coteus, Xin Zhang
  • Patent number: 10353610
    Abstract: There are disclosed techniques for use in configuring a data storage system. The techniques disclose defining a first workload including a first storage capacity requirement, a first IOPS requirement and a first skew value describing an expected workload profile. The techniques also disclose determining a percentage of the storage capacity requirement to be allocated from a storage tier based on a policy as well as allocating an amount of storage capacity from the storage tier in accordance with the percentage of the first storage capacity requirement. The techniques also disclose utilizing the first skew value to map the percentage of the first storage capacity requirement to a corresponding IOPS percentage to be handled by the storage tier. Further, the techniques disclose determining a first distribution of IOPS to the allocated storage capacity based on the IOPS percentage and the first IOPS requirement.
    Type: Grant
    Filed: March 16, 2017
    Date of Patent: July 16, 2019
    Assignee: EMC IP Holding Company LLC
    Inventors: Muzhar S. Khokhar, Shyam Reddy
  • Patent number: 10284414
    Abstract: This invention relates to methods and systems for estimating skew based on, for example, the IEEE 1588 Precision Time Protocol (PTP). These methods and systems can allow the clock skew between a master clock (server) and slave clock (client) exchanging PTP messages over a packet network to be estimated more rapidly than conventional estimation techniques and thereby improve the convergence of standard estimation algorithms. In one embodiment, the skew estimation is derived from a set of timestamps from a message exchange between the master and slave using a non-linear least square-fitting algorithm. An example of the fitting algorithm is the Levenberg-Marquardt algorithm.
    Type: Grant
    Filed: June 10, 2016
    Date of Patent: May 7, 2019
    Assignees: Khalifa University of Scence, Technology and Research, British Telecommunications PLC, Emirates Telecommunications Corporation
    Inventors: Zdenek Chaloupka, Ivan Boyd
  • Patent number: 10243764
    Abstract: A method of and device for generation and transmission of a first data message over a wireless channel and for a device-to-device enabled cellular communication device arranged to operate with a cellular radio access network. A transmitter identification, ID, of the cellular communication device in the first data message is included The entire first data message, including at least data associated with the transmitter ID is scrambled with a scrambling sequence associated with a synchronization source identity. The first data message is transmitted over the wireless channel. A corresponding method of and device for receiving and decoding one or more data messages over a wireless channel and for a device-to-device enabled cellular communication device arranged to operate with a cellular radio access network. A first synchronization source identity is determined. A received first data message with a scrambling sequence associated with the first synchronization source identity is descrambled.
    Type: Grant
    Filed: October 29, 2014
    Date of Patent: March 26, 2019
    Assignee: Telefonaktiebolaget LM Ericsson (Publ)
    Inventors: Bengt Lindoff, Fredrik Gunnarsson, Stefano Sorrentino
  • Patent number: 10241719
    Abstract: A computer-implemented method, computer program product and system for dynamic granularity of a data storage by identifying tiers of data including units of data with a unit heat index, corresponding to an activity level metric and identifying a tier heat index for each of the tiers of data corresponding to an average of the unit heat index for the units of data within the tiers of data. Furthermore determining a granularity index based on a size of the units of data; calculating a pairing index by comparing the unit heat indexes from the corresponding tiers of data and calculating an efficiency index by comparing the unit heat indexes indicating a percentage of the of units of data within a first tier of data with a higher unit heat index than all of the units of data within a another tier of data with a lower tier heat index.
    Type: Grant
    Filed: June 27, 2016
    Date of Patent: March 26, 2019
    Assignee: International Business Machines Corporation
    Inventor: Xue Qiang Zhou
  • Patent number: 10209307
    Abstract: A multiple-level driver circuit, such as for providing several different signals to a device under test (DUT) in an automated test system, can include multiple diode bridge circuits. In an example, a first diode bridge circuit is configured to receive a multiple-valued input voltage signal, having at least two different DC voltage signal levels, at an input node and, in response, to selectively provide a corresponding multiple-valued output voltage signal at an output node. The first diode bridge circuit can operate in a conducting and non-commutated state when it is used to selectively provide the multiple-valued output voltage signal at the output node.
    Type: Grant
    Filed: May 23, 2016
    Date of Patent: February 19, 2019
    Assignee: Analog Devices, Inc.
    Inventor: Christopher C. McQuilkin
  • Patent number: 10132653
    Abstract: Some embodiments of the invention include a capacitive linear encoder for determining positions comprising a scale and a read head for capacitively scanning the scale, wherein scale and read head are movable relative to one another. The scale has at least one, preferably capacitive, position reference marker. On the basis of the position references provided by the capacitive position reference marker, the positions are locatable in absolute terms and verifiable.
    Type: Grant
    Filed: December 3, 2015
    Date of Patent: November 20, 2018
    Assignee: HEXAGON TECHNOLOGY CENTER GMBH
    Inventors: Marcel Rohner, Ingo Bednarek, Rainer Wohlgenannt, Lukas Baumann
  • Patent number: 10095360
    Abstract: A communication device, including: a touch sensor configured to detect a touch or an approach of an input object by detecting a change in capacitance; and a near field communicator configured to perform near field communication with an information processing terminal present in a communication area in which near field communication is possible, the information processing terminal being capable of performing the near field communication, wherein a distance within which the touch or the approach of the input object is detectable by the touch sensor is shorter than a distance within which the near field communication by the near field communicator with the information processing terminal is possible.
    Type: Grant
    Filed: March 27, 2014
    Date of Patent: October 9, 2018
    Assignee: BROTHER KOGYO KABUSHIKI KAISHA
    Inventors: Koji Akagi, Masaaki Wakizaka, Shoji Sato, Akikazu Murata
  • Patent number: 10054467
    Abstract: Some embodiments of the invention include an absolute capacitive rotary encoder comprising a first disk, which is rotatable relative a second disk, and a first sensor ring and a second sensor ring. The first and the second sensor ring each have a multiplicity of first coupling electrodes and second coupling electrodes capacitively coupling to one another. The first coupling electrodes of a respective sensor ring have different coupling signal phases. The first sensor ring and the second sensor ring are matched to one another in such a way that an angle is determinable absolutely.
    Type: Grant
    Filed: December 3, 2015
    Date of Patent: August 21, 2018
    Assignee: HEXAGON TECHNOLOGY CENTER GMBH
    Inventors: Marcel Rohner, Ingo Bednarek, Lukas Baumann, Rainer Wohlgenannt
  • Patent number: 9964597
    Abstract: Methods and apparatus for self test of safety logic in safety critical devices is provided in which the safety logic includes comparator logic coupled to a circuit under test (CUT) in a safety critical device and the self test logic is configured to test the comparator logic. The self test logic may be implemented as a single cycle parallel bit inversion approach, a multi-cycle serial bit inversion approach, or a single cycle test pattern injection approach.
    Type: Grant
    Filed: September 1, 2016
    Date of Patent: May 8, 2018
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Sundarrajan Rangachari, Saket Jalan
  • Patent number: 9921912
    Abstract: A technique for managing spare disk drives in a data storage system includes transferring segments of data from disk drives of an operating RAID group to spare regions on a set of spare disk drives to create unused space in the disk drives of the RAID group, thus using the spare regions to overprovision storage in the RAID group. Upon a failure of one of the disk drives in the RAID group, data of the failing disk drive are rebuilt based on the segments of data as well as on data from still-functioning disk drives in the RAID group. Thus, the spare disk drives act not only to overprovision storage for the RAID group prior to disk drive failure, but also to fulfill their role as spares in the event of a disk drive failure.
    Type: Grant
    Filed: September 30, 2015
    Date of Patent: March 20, 2018
    Assignee: EMC IP Holding Company LLC
    Inventors: Vamsi Vankamamidi, Ryan Gadsby, Thomas E. Linnell, David W. Harvey, Daniel Cummins, Steven Morley
  • Patent number: 9903891
    Abstract: The present invention includes a detecting capacitor of which the capacitance is changed depending on pressure; a fixed capacitor having reference capacitance; an initial voltage application part that applies an initial voltage having a predetermined frequency to the detecting capacitor and the fixed capacitor; a first operational amplifier that outputs an output voltage based on a partial voltage applied to at least the detecting capacitor; a reference voltage generation part that generates a reference voltage that serves as a reference for a change in the output voltage of the first operational amplifier and has the same frequency as that of the initial voltage; a second operational amplifier that outputs an output voltage based on the difference between the output voltage of the first operational amplifier and the reference voltage; and a pressure operation part that operates a pressure from the amplitude of the output voltage of the second operational amplifier.
    Type: Grant
    Filed: November 27, 2015
    Date of Patent: February 27, 2018
    Assignee: HORIBA STEC, CO., LTD.
    Inventors: Sotaro Kishida, Ryota Nakayama
  • Patent number: 9883256
    Abstract: A transmission system, a receiver and a method for satellite signal transmission, wherein the satellite signals includes respective data streams consisting of a sequence of data packets. The method includes: subdividing the data packets of the data stream, through a splitter, into a first and at least one second data pseudo-streams; modulating the first and at least one second data pseudo-streams through a first and at least one second modulators, respectively; transmitting the modulated data pseudo-streams through respective transmission channels (Ch#1 . . . Ch#N), wherein, in order to generate the data pseudo-streams, the splitter will: select each data packet of the data stream; interrogate the modulators in a sequential manner in order to identify that modulator which, among the modulators, is available to accept the data packet, and send the latter to it; send a null data packet to the remaining modulators.
    Type: Grant
    Filed: September 2, 2014
    Date of Patent: January 30, 2018
    Assignee: RAI Radiotelevisione Italiana S.P.A.
    Inventors: Alberto Morello, Vittoria Mignone, Bruno Sacco
  • Patent number: 9804939
    Abstract: A technique for repairing a RAID (Redundant Array of Independent Disks) group in a data storage system following a failure of a disk drive in the RAID group includes identifying regions of the failed disk drive that supported unallocated storage extents and writing predetermined data to corresponding regions of the spare disk drive. Any reading of other disk drives in the RAID group may thus be limited only to those regions of the failed disk drive that supported allocated storage extents.
    Type: Grant
    Filed: September 30, 2015
    Date of Patent: October 31, 2017
    Assignee: EMC IP Holding Company LLC
    Inventors: Jean-Pierre Bono, Philippe Armangau
  • Patent number: 9806743
    Abstract: A method for decoding a codeword transmitted over a channel demodulates data received over the channel to produce an initial estimate of belief messages for bits of the codeword and decodes the codeword using a belief propagation (BP) decoding that iteratively passes the belief messages between a set of variable nodes representing the bits of the codeword and a set of check nodes representing parity-check constraints on the bits of the codeword until a termination condition is met. The BP decoding selects a look-up table based on a probability of the belief messages and maps, using the look-up table, values of at least two incoming belief messages to values of at least one outgoing belief message that forms an incoming belief message in a subsequent iteration of the BP decoding.
    Type: Grant
    Filed: November 16, 2015
    Date of Patent: October 31, 2017
    Assignee: Mitsubishi Electric Research Laboratories, Inc.
    Inventors: Toshiaki Koike-Akino, David Millar
  • Patent number: 9772649
    Abstract: In accordance with an embodiment of the invention, higher-speed outgoing data paths are used to transmit oversampled data signals, and corresponding slower-speed return data paths are used to receive return data signals. A channel-bonding control circuit measures the skew between the returned data signals and generates bit-slip and/or word-slip control signals to compensate for the skew. Transmission bit-slip (or, alternatively, clock-slip) circuits slip integer numbers of bits based on the bit-slip control signals. Bypass registers (or, alternatively, FIFO write or read enable signals) may be used to slip a whole word when the integer number of bits to slip is greater or equal to the parallel width of a lane. Various other aspects, features, and embodiments are also disclosed.
    Type: Grant
    Filed: May 28, 2015
    Date of Patent: September 26, 2017
    Assignee: Altera Corporation
    Inventor: David W. Mendel
  • Patent number: 9640278
    Abstract: An apparatus includes an output driver circuit and a trimming circuit. The output driver circuit may be configured to (i) receive an input signal and a first control signal and (ii) generate an output signal. The output signal may be a delayed version of the input signal. A length of delay between the input signal and the output signal is determined in response to the first control signal. The trimming circuit may be configured to generate the first control signal in response to a second control signal. The trimming circuit is generally enabled to vary a value of the first control signal to minimize a phase difference between the output signal and an output clock signal.
    Type: Grant
    Filed: December 10, 2015
    Date of Patent: May 2, 2017
    Assignee: INTEGRATED DEVICE TECHNOLOGY, INC.
    Inventor: Xiaoming Xi
  • Patent number: 9588178
    Abstract: The present disclosure describes a novel method and apparatus of using the JTAG TAP's TMS and TCK terminals as a general purpose serial Input/Output (I/O) bus. According to the present disclosure, the TAP's TMS terminal is used as a clock signal and the TCK terminal is used as a bidirectional data signal to allow serial communication to occur between; (1) an IC and an external controller, (2) between a first and second IC, or (3) between a first and second core circuit within an IC.
    Type: Grant
    Filed: March 21, 2016
    Date of Patent: March 7, 2017
    Assignee: Texas Instruments Incorporated
    Inventor: Lee D. Whetsel
  • Patent number: 9582634
    Abstract: A method of optimizing timing performance of an IC design is provided. The IC design is expressed as a graph that includes a plurality of paths. Each path includes a plurality of nodes that represent IC components including clocked elements and computational elements. The method optimizes the timing performance of the IC design by retiming a set of paths. The retiming includes skewing clock signals to a set of clocked elements by more than a clock period without changing the position of any clocked element relative to the position of the computational elements in the set of paths. The method performs simulation on the optimized IC design and provides the result of the simulation as a clock skew scheduling of the IC design instead of retiming of the IC design.
    Type: Grant
    Filed: December 24, 2014
    Date of Patent: February 28, 2017
    Assignee: Altera Corporation
    Inventors: Steven Teig, Andrew Caldwell
  • Patent number: 9563191
    Abstract: A method and system for autonomously monitoring, evaluating, storing and testing tools and other units operated at a rig-site. The system may include a storage facility communicatively coupled to one or more tools, status flags identifying the health and operational status of the tools, and a computer for performing a self-check for determining the operational status for the one or more tools. The system may further include a remotely positioned computer system in communication with the operational status of the tools, and a user terminal in communication with the computer system.
    Type: Grant
    Filed: August 8, 2011
    Date of Patent: February 7, 2017
    Assignee: Halliburton Energy Services, Inc.
    Inventor: Ronald Johannes Dirksen
  • Patent number: 9529962
    Abstract: The present disclosure relates to a computer-implemented method for use with an electronic design. Embodiments include identifying, using one or more processors, a plurality of sibling nets associated with the electronic design and determining if the plurality of sibling nets have a same input slew rate. If the plurality of sibling nets do not have a same input slew rate, embodiments also include determining a delay calculation (DC) for each of the plurality of sibling nets. If the plurality of sibling nets do have a same input slew rate, embodiments further include sharing a stored DC with the plurality of sibling nets.
    Type: Grant
    Filed: June 5, 2015
    Date of Patent: December 27, 2016
    Assignee: Cadence Design Systems, Inc.
    Inventors: Amit Dhuria, Pradeep Yadav, Manuj Verma, Naresh Kumar, Prashant Sethia
  • Patent number: 9502003
    Abstract: A digital image is obtained from a camera in a smartphone and is processed by a processor on the smartphone to modify a part but not all of the pixels in a frame of the digital image, which is a digital video image, which is modified by image processing in accordance with a modification mask and reversible modification instructions, and is transmitted to a second smartphone with a display screen to display the modified image. Image processing data are transmitted to the second smartphone to enable restoring the original digital video image from the partially reversibly modified image and to be displayed in unmodified form on the display screen.
    Type: Grant
    Filed: July 31, 2015
    Date of Patent: November 22, 2016
    Assignee: Spatial Cam LLC
    Inventor: Peter Lablans
  • Patent number: 9485039
    Abstract: Techniques for calibrating interleaved analog-to-digital converter (ADC) arrays are presented. A transceiver comprises an ADC component comprising an array of interleaved sub-ADCs, and an auxiliary path associated with an auxiliary sub-ADC used to facilitate calibrating a sampling array by comparing the auxiliary path signal to signals of the sub-ADCs in the array. A calibration component employs a phase-interpolator and analog delay lines to adjust the auxiliary sub-ADC to enable the auxiliary sub-ADC to be lined up to any one of the sampling instants of the sampling array. The calibration component compares the auxiliary signal to sub-ADC signals, determines path differences between the sub-ADC paths based on the comparison results, and calibrates the sub-ADCs and sub-ADC paths to reduce the path differences to mitigate distortion in a digital stream produced from combining the digital substreams produced by the sub-ADCs in the array.
    Type: Grant
    Filed: June 11, 2015
    Date of Patent: November 1, 2016
    Assignee: APPLIED MICRO CIRCUITS CORPORATION
    Inventors: Moshe Malkin, Tarun Gupta
  • Patent number: 9442136
    Abstract: Disclosed is an improved real-time oscilloscope (“IRTO”) for generating a fast worst-case real-time eye diagram from an input signal. The IRTO may include signal conditioning circuitry, a digitizer, an acquisition memory, a clock and data recovery (“CDR”) module, a worst-case real-time eye diagram rendering (“WRTER”) module, and a display.
    Type: Grant
    Filed: September 1, 2013
    Date of Patent: September 13, 2016
    Assignee: Keysight Technologies, Inc.
    Inventor: Christopher P. Duff
  • Patent number: 9395744
    Abstract: Techniques for de-skewing transmitted data are described herein. In one example, a method can include detecting, via a processor, a number of data lanes that transmit data. The method can also include designating, via the processor, a number of buffers to store the data transmitted through each data lane, wherein the number of buffers is less than the number of data lanes. Additionally, the method can include detecting, via the processor, an alignment marker for each data lane. Furthermore, the method can include storing, via the processor, the transmitted data received from the data lanes in the buffers, and de-skewing, via the processor, the transmitted data when the alignment marker for each data lane has been detected.
    Type: Grant
    Filed: January 24, 2014
    Date of Patent: July 19, 2016
    Assignee: International Business Machines Corporation
    Inventor: Yiftach Benjamini
  • Patent number: 9372626
    Abstract: Parallel storage system testing is provided. An input/output (I/O) pattern is received. One or more sets of jobs are determined, based, at least in part, on the I/O pattern. Each of the one or more sets of jobs identifies one or more jobs. Each job identifies one or more I/O operations. Each set of jobs of the one or more sets of jobs is assigned to a processing node of one or more processing nodes. The one or more sets of jobs are executed concurrently.
    Type: Grant
    Filed: June 12, 2014
    Date of Patent: June 21, 2016
    Assignee: LENOVO ENTERPRISE SOLUTIONS (SINGAPORE) PTE. LTG.
    Inventor: Madhav Ponamgi
  • Patent number: 9344209
    Abstract: Discrete time compensation mechanisms include a channel component configured for determining which channel of a plurality of channels to process time slots of sampled data that are time stamped in a discrete time and processing the time slots of the sampled data to the plurality of channels. A common channel clock component is configured for time stamping the time slots of the sampled data in the discrete time domain that is faster than a non-discrete reference time stamp of continuous data from which the time slots are sampled from and for processing the sampled data through the plurality of channels faster than the continuous data is being received. Compensations for one or more gaps are generated based on a set of predetermined criteria and a corrected time stamp is applied to the sampled data for processing among different processing channels.
    Type: Grant
    Filed: September 3, 2013
    Date of Patent: May 17, 2016
    Assignee: APPLIED MICRO CIRCUITS CORPORATION
    Inventors: Stacy Nichols, Sameer Gandhi, Burt Christian
  • Patent number: 9324455
    Abstract: A method of measuring skew between signals from an asynchronous integrated flash memory controller (IFC) includes connecting input/output (I/O) pins of the IFC to cycle based test equipment (ATE). The ATE applies a pattern of test signals as input drive to the IFC. Relative to the test cycle, the earliest delay time at which output signals from all of the I/O pins first correspond with expected results, and the latest delay time at which the output signals still correspond with the expected results are measured. The difference between the latest and the earliest delay times is compared with a limit value and a comparison report is generated.
    Type: Grant
    Filed: May 27, 2014
    Date of Patent: April 26, 2016
    Assignee: FREESCALE SEMICONDUCTOR, INC.
    Inventors: Vishal Vadhavania, Deepak Jindal, Anuruddh Sachan
  • Patent number: 9304531
    Abstract: Disclosed are various embodiments providing processing circuitry that generates an output for each clock cycle of a clock signal using a logic block, the logic block being powered by a supply voltage. The processing circuitry detects whether the output has stabilized at a point in time before the end of a clock cycle of the clock signal, the point in time being based at least upon a delay line. In response to detecting whether the output has stabilized at a point in time, the processing circuitry dynamically adjusts at least one of the supply voltage or the frequency of the clock signal.
    Type: Grant
    Filed: November 27, 2012
    Date of Patent: April 5, 2016
    Assignee: BROADCOM CORPORATION
    Inventors: David Money Harris, Kwok Ping Hui
  • Patent number: 9279857
    Abstract: A semiconductor device-under-test (DUT) may be tested by an automated test system that processes test programs specifying a number of edges per tester cycle that may be greater than the number of edges the tester is capable of generating. The test system may include circuitry that reduces the number of edges in each cycle of a test program based on data specifying operation of the tester in that cycle and/or a prior cycle. Such a reduction simplifies the circuitry required to implement an edge generator by reducing the total number of timing verniers per channel. Nonetheless, flexibility in programming the test system is retained.
    Type: Grant
    Filed: November 19, 2013
    Date of Patent: March 8, 2016
    Assignee: Teradyne, Inc.
    Inventors: Howard Lin, Corbin L. Champion, Jan Paul Anthonie van der Wagt, Ronald A. Sartschev
  • Patent number: 9263151
    Abstract: A memory interface enables AC characterization under test conditions without requiring the use of Automated Test Equipment (ATE) and functional patterns. The memory controller may be configured to generate output patterns through the test interface and create a loopback path for input specification testing using an external stressed-eye random number generator and checker. As a result, the memory interface may be evaluated for electrical and timing specifications under a relatively simple test setup and test procedure through the test interface (JTAG), as opposed to a complex processor program that sets up a similar memory access pattern on Automated Test Equipment (ATE).
    Type: Grant
    Filed: February 15, 2012
    Date of Patent: February 16, 2016
    Assignee: Cavium, Inc.
    Inventors: Thucydides Xanthopoulos, David Lin
  • Patent number: 9225507
    Abstract: Provided is a method and apparatus for aligning a first local oscillator (LO) clock generated by a controllable LO clock generator in a first radio frequency (RF) path with a second LO clock in a second RF path. The apparatus includes a synchronization channel configured to exchange a synchronization clock between the first and second RF paths, a phase detector configured to measure a phase alignment between the first and second LO clocks, and a loop filter configured to drive the controllable LO clock generators using the phase alignment. Also provided is a time to digital converter. The time to digital converter includes a D flip-flop for sampling first and second input clocks with a third clock, and a counter configured to synchronously increment the resulting samples and create a digital proportional value representing the delay between the first and second clocks.
    Type: Grant
    Filed: June 4, 2013
    Date of Patent: December 29, 2015
    Assignee: PMC-Sierra US, Inc.
    Inventors: William Michael Lye, Dragos Cartina
  • Patent number: 9071262
    Abstract: Techniques for calibration of high-speed interleaved analog-to-digital converter (ADC) arrays are presented. A transceiver comprises an ADC component that comprises an array of sub-ADCs that can be interleaved to facilitate high-speed data communications. The ADC component processes signals received from a remote transmitter to facilitate recovering the received data. The transceiver can comprise a calibration component that determines transfer characteristics of the communication channel or medium between the transceiver and the remote transmitter, and the transfer characteristics of the remote transmitter to each of the sub-ADCs of the array, based on the recovered data.
    Type: Grant
    Filed: January 24, 2014
    Date of Patent: June 30, 2015
    Assignee: Applied Micro Circuits Corporation
    Inventor: Moshe Malkin
  • Patent number: 9053025
    Abstract: A processor is described comprising: instruction failure logic to perform a plurality of operations in response to a detected instruction execution failure, the instruction failure logic to be used for instructions which have complex failure modes and which are expected to have a failure frequency above a threshold, wherein the operations include: detecting an instruction execution failure and determining a reason for the failure; storing failure data in a destination register to indicate the failure and to specify details associated with the failure; and allowing application program code to read the failure data and responsively take one or more actions responsive to the failure, wherein the instruction failure logic performs its operations without invocation of an exception handler or switching to a low level domain on a system which employs hierarchical protection domains.
    Type: Grant
    Filed: December 28, 2012
    Date of Patent: June 9, 2015
    Assignee: Intel Corporation
    Inventors: Oren Ben-Kiki, Ilan Pardo, Robert Valentine
  • Patent number: 8971355
    Abstract: An information processing apparatus is provided which includes a transmission unit for transmitting a query request for querying another device for a count value held by such other device, a reception unit for receiving a return of the count value from such other device, a correction unit for performing, at a predetermined period, correction processing for synchronizing sampling frequency with such other device based on the received count value, and a reproduction unit for reproducing content in synchronization with such other device based on the sampling frequency. The correction unit corrects by taking into account a Round Trip Time between the transmission of the query request and the reception of the return and residual difference occurred at a previous correction time.
    Type: Grant
    Filed: June 3, 2010
    Date of Patent: March 3, 2015
    Assignee: Sony Corporation
    Inventor: Seiji Ohbi
  • Publication number: 20150046760
    Abstract: A memory module may have a redrive circuit having a plurality of redrive paths, a memory device, and a deskew circuit. The deskew circuit may be separate from the plurality of redrive paths. The deskew circuit may be coupled between the plurality of redrive paths and the memory device to selectively deskew data received in the redrive circuit.
    Type: Application
    Filed: June 16, 2014
    Publication date: February 12, 2015
    Inventor: Pete D. Vogt
  • Patent number: RE47252
    Abstract: A communication system includes master host unit, hybrid expansion unit, and remote antenna unit. Master host unit communicates analog signals with service provider interfaces. Master host unit and hybrid expansion unit communicate N-bit words of digitized spectrum over communication link. Hybrid expansion unit converts between N-bit words and analog spectrum. Hybrid expansion unit and remote antenna unit communicate analog spectrum over analog communication medium. Remote antenna unit transmits and receives wireless signals over air interfaces. Master host unit includes master clock distribution unit that generates digital master reference clock signal. Master host unit communicates digital master reference clock signal over communication link. Hybrid expansion unit receives digital master reference clock signal from master host unit over communication link and generates analog reference clock signal based on digital master reference clock signal.
    Type: Grant
    Filed: September 16, 2016
    Date of Patent: February 19, 2019
    Assignee: CommScope Technologies LLC
    Inventors: Lance K. Uyehara, Larry G. Fischer, David Hart, Dean Zavadsky
  • Patent number: RE47393
    Abstract: A communication system includes master host unit, hybrid expansion unit, and remote antenna unit. Master host unit communicates analog signals with service provider interfaces. Master host unit and hybrid expansion unit communicate N-bit words of digitized spectrum over communication link. Hybrid expansion unit converts between N-bit words and analog spectrum. Hybrid expansion unit and remote antenna unit communicate analog spectrum over analog communication medium. Remote antenna unit transmits and receives wireless signals over air interfaces. Master host unit includes master clock distribution unit that generates digital master reference clock signal. Master host unit communicates digital master reference clock signal over communication link. Hybrid expansion unit receives digital master reference clock signal from master host unit over communication link and generates analog reference clock signal based on digital master reference clock signal.
    Type: Grant
    Filed: September 16, 2016
    Date of Patent: May 14, 2019
    Assignee: CommScope Technologies LLC
    Inventors: Lance K. Uyehara, Larry G. Fischer, David Hart, Dean Zavadsky
  • Patent number: RE48342
    Abstract: A communication system includes master host unit, hybrid expansion unit, and remote antenna unit. Master host unit communicates analog signals with service provider interfaces. Master host unit and hybrid expansion unit communicate N-bit words of digitized spectrum over communication link. Hybrid expansion unit converts between N-bit words and analog spectrum. Hybrid expansion unit and remote antenna unit communicate analog spectrum over analog communication medium. Remote antenna unit transmits and receives wireless signals over air interfaces. Master host unit includes master clock distribution unit that generates digital master reference clock signal. Master host unit communicates digital master reference clock signal over communication link. Hybrid expansion unit receives digital master reference clock signal from master host unit over communication link and generates analog reference clock signal based on digital master reference clock signal.
    Type: Grant
    Filed: February 15, 2019
    Date of Patent: December 1, 2020
    Assignee: CommScope Technologies LLC
    Inventors: Lance K. Uyehara, Larry G. Fischer, David Hart, Dean Zavadsky
  • Patent number: RE48351
    Abstract: A communication system includes master host unit, hybrid expansion unit, and remote antenna unit. Master host unit communicates analog signals with service provider interfaces. Master host unit and hybrid expansion unit communicate N-bit words of digitized spectrum over communication link. Hybrid expansion unit converts between N-bit words and analog spectrum. Hybrid expansion unit and remote antenna unit communicate analog spectrum over analog communication medium. Remote antenna unit transmits and receives wireless signals over air interfaces. Master host unit includes master clock distribution unit that generates digital master reference clock signal. Master host unit communicates digital master reference clock signal over communication link. Hybrid expansion unit receives digital master reference clock signal from master host unit over communication link and generates analog reference clock signal based on digital master reference clock signal.
    Type: Grant
    Filed: September 16, 2016
    Date of Patent: December 8, 2020
    Assignee: CommScope Technologies LLC
    Inventors: Lance K. Uyehara, Larry G. Fischer, David Hart, Dean Zavadsky