Abstract: Techniques and mechanisms for determining an amount of skew between two clock signals. In an embodiment, detector circuitry receives a first signal and a signal which indicate (respectively) a NAND combination of clock signals, and a NOR combination of the clock signals. The detector circuitry evaluates a first length of time that the first signal indicates a respective first logic state, and a second length of time that the second signal indicates a respective second logic state. The skew is calculated based on a difference between the first length of time and the second length of time. In another embodiment, one of the first signal or the second signal is generated with a combinatorial logic gate, a transistor of which is relatively large, as compared to another transistor which is to operate based on one of the first signal, the second signal, or the clock signals.

Abstract: In order to provide a receiver capable of accurately determining a phase difference of I/Q signals, a receiver includes a section detector configured to detect a section between a rising and a falling of a phase based on the rising and the falling of the phase represented by I/Q signals generated based on an advertisement packet transmitted from a transmitter, and a section setting unit configured to identify, within the section between the rising and the falling of the phase, a period in which a first variation amount of the phase is equal to or less than a first predetermined amount, and use the identified period as a section for detecting the phase of the I/Q signals. The section detector detects the rising when a first phase is smaller than a last phase among a plurality of phases acquired by sampling the phases.

Abstract: Techniques for encoding additional data in a memory without requiring an increase to the physical storage capacity of the memory device are described. Additional data can be encoded with error correction code symbols without having to physically store the additional data in memory, while retaining the number of error correction code bits used by the memory. When data is read from memory without the additional data, erasure decoding can be performed to recover the additional data. When errors are encountered in the data read from memory, the errors can be treated as erasures for different predictions of the error locations to determine if the errors can be corrected.

Abstract: A probe device includes a first receiving terminal configured to receive a multi-level signal having M levels, where M is a natural number greater than 2; a second receiving terminal configured to receive a reference signal; a receiving buffer including a first input terminal connected to the first receiving terminal, a second input terminal connected to the second receiving terminal, and an output terminal configured to output the multi-level signal based on signals received from the first and second input terminals; and a resistor circuit comprising a plurality of resistors connected to the first and second receiving terminals and determining a magnitude of a termination resistance of the first and second receiving terminals.

Abstract: A device includes a receiver to receive one or more training sequences during a training of a link, where the link connects two devices. The device may include agent logic to determine, from the one or more training sequences, a number of extension devices on the link between the two devices, and determine that the number of extension devices exceeds a threshold number. The device may include a transmitter to send a plurality of clock compensation ordered sets on the link based on determining that the number of extension devices exceeds a threshold number.

Abstract: The present disclosure relates to a data transmission method, device, system, and display device. The method includes encoding clock training data to obtain two sets of encoded data corresponding to the clock training data and complementary to each other, sending a specified set of encoded data in the two sets of encoded data to a receiving end when positive and negative pins of the transmitting end and the receiving end are correspondingly connected, sending other set of coded data in the two sets of coded data than the specified set of encoded data to the receiving end when the positive and negative pins of the transmitting end and the receiving end are reversely connected. The receiving end may be configured to perform clock training according to the received encoded data.

Abstract: A test instrument or host device can apply inverse transmitter and receiver functions to data transmitted or received by an electrical and optical transponder. The inverse transmitter and receiver functions are applied to counteract internal signal conversion processes of the transponder. Forward error correction and test pattern analysis may be performed on signals received from the transponder after the inverse receiver function is applied to the received signals.

Abstract: Crosstalk amelioration systems and methods in a radio frequency front end (RFFE) communication system provide a host or master of an RFFE bus to monitor a weakly-driven data line in the RFFE bus while a clock line is actively providing a clock signal for trigger events at one or more slaves on the RFFE bus. If the host detects noise on the data line that looks like a sequence start condition (SSC) signal, the host further signals on the data line to negate the impact of the false SSC signal and thus avoid misinterpretation by the slaves.

Abstract: A probe is connectable to a test instrument for measuring signals of a DUT, where the probe includes a probe head that includes multiple leads configured to connect to signal probe points of the DUT, and a sensor connected between two of the leads; at least one probe output configured to connect to the test instrument; a current detection circuit configured to detect current of the DUT through the sensor, and to provide a detected current signal; a voltage detection circuit configured to detect voltage of the DUT between the sensor and ground, and to provide a detected voltage signal; a combiner configured to combine the detected current signal and the detected voltage signal, and to provide a power signal indicating power of the DUT; and switches configured to selectively output at least one of the detected current signal, the detected voltage signal, and the power signal.

Abstract: A system and method for measuring or calibrating a delay through a circuit path within an integrated circuit is disclosed. In some embodiments, a delay locked loop (DLL) circuit is provided. An arbiter circuit in the DLL compares timing of a clock signal and a delayed version of the clock signal that has passed through the circuit path. The percentage of the clock signal with feature that arrives before the corresponding feature of the delayed clock can be an indication of the delay timing through the path relative to a period of the clock signal and used as feedback in the DLL.

Abstract: In certain embodiments, a method includes repeatedly transmitting, by a first device, first data to a second device within a first time unit set. The first data is determined based on a first redundancy version and to-be-transmitted system bits. The first time unit set includes K time units, K?3, and K is an integer. The method further includes when a first condition is met, stopping, by the first device, transmitting the first data in the Mth time unit, where 2?M?K, and M is an integer.

Abstract: A power saving wire-free earpiece has a Bluetooth transceiver and a Bluetooth Low Energy (BLE) transceiver. A stream of audio from a remote source is separated into a local audio stream and a stream sent to the BLE transceiver for a remote earpiece. The earpiece is operative in a first and second mode, the first mode enabling the BT transceiver and BLE transceiver, the second mode enabling only the BLE transceiver for receiving remote streams of data. The first and second mode alternate so that the local and remote earpiece have substantially uniform current requirements.

Abstract: The disclosed systems, structures, and methods are directed to a two wire-based clock multiplication unit (CMU), employing a first phase lock loop (PLL) configured to generate a first high-speed clock frequency f1 encoded in differential mode, a second PLL configured to generate a second high-speed clock frequency f2 encoded in common mode, and a summer configured to combine the differential mode encoding the first high-speed clock frequency f1 and the common mode encoding the second high-speed clock frequency f2 and transmit the combined differential and common mode high-speed clock frequencies on a two wire-based conductor bus. In addition, systems, structures, and methods directed to a two wire-based clock recovery module and a two wire-based clock recovery module have also been disclosed.

Abstract: Techniques and mechanisms to exchange test, debug or trace (TDT) information via a general purpose input/output (I/O) interface. In an embodiment, an I/O interface of a device is coupled to an external TDT unit, wherein the I/O interface is compatible with an interconnect standard that supports communication of data other than any test information, debug information or trace information. One or more circuit components reside on the device or are otherwise coupled to the external TDT unit via the I/O interface. Information exchanged via the I/O interface is generated by, or results in, the performance of one or more TDT operations to evaluate the one or more circuit components. In another embodiment, the glue logic of the device interfaces the I/O interface with a test access point that is coupled between the one or more circuit components and the I/O interface.

Abstract: Generating, during a first and second signaling interval, an aggregated data signal by forming a linear combination of wire signals received in parallel from wires of a multi-wire bus, wherein at least some of the wire signals undergo a signal level transition during the first and second signaling interval; measuring a signal skew characteristic of the aggregated data signal; and, generating wire-specific skew offset metrics, each wire-specific skew offset metric based on the signal skew characteristic.

Abstract: Changes in operating conditions, like voltage or temperature, can cause the frequency of an internal clock signal to change and negatively affect device operation. In one embodiment, a method for controlling internal clock frequency of a device includes counting a number of clock cycles of the internal clock signal relative to a current period of a system clock signal to determine a current mid-cycle count of clock cycles, wherein the internal clock signal is based on a first clock signal of a plurality of clock signals produced in the device, each having a different frequency. When the current mid-cycle count is differs from a calibrated mid-cycle count by more than a tolerable amount, a second clock signal of the plurality of clock signals is selected as the internal clock signal.

Abstract: A method for operating a bus system in which a message of the bus system is received and its validity is ascertained, characterized in that, when it has been ascertained that the message is “not valid”, a defend message is transmitted to a designated recipient of the message, the defend message being configured so that the designated recipient is instructed by way of the defend message to initiate defensive measures against the message.

Abstract: In certain aspects, a serial-to-parallel converter includes multiple cascaded stages configured to convert a serial data stream into multiple parallel data signals, wherein each of the stages includes one or more demultiplexers. The serial-to-parallel converter also includes demultiplexer control circuits, wherein each of the demultiplexer control circuits is coupled to the one or more demultiplexers of a respective one of the stages, and a pattern detector coupled to the demultiplexer control circuits.

Abstract: A test instrument or host device can apply inverse transmitter and receiver functions to data transmitted or received by an electrical and optical transponder. The inverse transmitter and receiver functions are applied to counteract internal signal conversion processes of the transponder. Forward error correction and test pattern analysis may be performed on signals received from the transponder after the inverse receiver function is applied to the received signals.

Abstract: The invention relates to a method for generating haptic coefficients associated with an audiovisual document. Initially, data is extracted from an audio and/or video track and is used to calculate at least one first group of haptic coefficients from an autoregressive model applied to the read data. These haptic coefficients are designed to program a filter supplying at the output the control parameters for controlling at least one haptic actuator. Then, a “haptic” sequence of the audiovisual document is determined and calculated haptic parameters are associated with the determined sequence. In this manner, the haptic parameters enabling the control of one or more actuators are easily calculated and easily reproducible. Advantageously, the data used for the calculation is extracted from the selected sequence.

Abstract: Enabling Low Frequency Periodic Signalling over an optical link with a circuit arrangement and method for controlling a light-emitting component, including: monitoring a differential input for the presence of an electrical idle state by an IDLE detector; triggering a time delay block by the IDLE detector when the electrical idle state at the differential input is interrupted or resumed; detecting whether the differential input is driven by a Low Frequency Periodic Signalling or by a Super Speed/Enhanced Super Speed signalling by a signal type detector; making a decision whether the signalling is to be transmitted by a decision circuit; an input stage connected to the decision circuit; and driving the light-emitting component by an output stage.

Abstract: A power-delivery system may comprise a load device and a direct-current converter configured to deliver current to the load device when the direct-current converter is in an on state. The power-deliver system may comprise a voltage-measurement system configured to measure, at a beginning of each measurement cycle in a cyclic measurement pattern, a voltage at the load device. The power-deliver system may comprise a power controller configure to receive, at the beginning of each measurement cycle, the measurement of the voltage, and to perform, at the beginning of a control cycle in a cyclic control pattern, a voltage-control decision in response to a change in the measurement of the voltage being below a voltage-change threshold. The voltage-control decision may comprise whether to switch the state of the first direct-current converter. The cyclic control pattern may operate at a first frequency, and the measurement pattern may operate at a second frequency.

Abstract: There are disclosed techniques for use in configuring a data storage system. The techniques disclose defining a first workload including a first storage capacity requirement, a first IOPS requirement and a first skew value describing an expected workload profile. The techniques also disclose determining a percentage of the storage capacity requirement to be allocated from a storage tier based on a policy as well as allocating an amount of storage capacity from the storage tier in accordance with the percentage of the first storage capacity requirement. The techniques also disclose utilizing the first skew value to map the percentage of the first storage capacity requirement to a corresponding IOPS percentage to be handled by the storage tier. Further, the techniques disclose determining a first distribution of IOPS to the allocated storage capacity based on the IOPS percentage and the first IOPS requirement.

Abstract: This invention relates to methods and systems for estimating skew based on, for example, the IEEE 1588 Precision Time Protocol (PTP). These methods and systems can allow the clock skew between a master clock (server) and slave clock (client) exchanging PTP messages over a packet network to be estimated more rapidly than conventional estimation techniques and thereby improve the convergence of standard estimation algorithms. In one embodiment, the skew estimation is derived from a set of timestamps from a message exchange between the master and slave using a non-linear least square-fitting algorithm. An example of the fitting algorithm is the Levenberg-Marquardt algorithm.

Abstract: A method of and device for generation and transmission of a first data message over a wireless channel and for a device-to-device enabled cellular communication device arranged to operate with a cellular radio access network. A transmitter identification, ID, of the cellular communication device in the first data message is included The entire first data message, including at least data associated with the transmitter ID is scrambled with a scrambling sequence associated with a synchronization source identity. The first data message is transmitted over the wireless channel. A corresponding method of and device for receiving and decoding one or more data messages over a wireless channel and for a device-to-device enabled cellular communication device arranged to operate with a cellular radio access network. A first synchronization source identity is determined. A received first data message with a scrambling sequence associated with the first synchronization source identity is descrambled.

Abstract: A computer-implemented method, computer program product and system for dynamic granularity of a data storage by identifying tiers of data including units of data with a unit heat index, corresponding to an activity level metric and identifying a tier heat index for each of the tiers of data corresponding to an average of the unit heat index for the units of data within the tiers of data. Furthermore determining a granularity index based on a size of the units of data; calculating a pairing index by comparing the unit heat indexes from the corresponding tiers of data and calculating an efficiency index by comparing the unit heat indexes indicating a percentage of the of units of data within a first tier of data with a higher unit heat index than all of the units of data within a another tier of data with a lower tier heat index.

Abstract: A multiple-level driver circuit, such as for providing several different signals to a device under test (DUT) in an automated test system, can include multiple diode bridge circuits. In an example, a first diode bridge circuit is configured to receive a multiple-valued input voltage signal, having at least two different DC voltage signal levels, at an input node and, in response, to selectively provide a corresponding multiple-valued output voltage signal at an output node. The first diode bridge circuit can operate in a conducting and non-commutated state when it is used to selectively provide the multiple-valued output voltage signal at the output node.

Abstract: Some embodiments of the invention include a capacitive linear encoder for determining positions comprising a scale and a read head for capacitively scanning the scale, wherein scale and read head are movable relative to one another. The scale has at least one, preferably capacitive, position reference marker. On the basis of the position references provided by the capacitive position reference marker, the positions are locatable in absolute terms and verifiable.

Abstract: A communication device, including: a touch sensor configured to detect a touch or an approach of an input object by detecting a change in capacitance; and a near field communicator configured to perform near field communication with an information processing terminal present in a communication area in which near field communication is possible, the information processing terminal being capable of performing the near field communication, wherein a distance within which the touch or the approach of the input object is detectable by the touch sensor is shorter than a distance within which the near field communication by the near field communicator with the information processing terminal is possible.

Abstract: Some embodiments of the invention include an absolute capacitive rotary encoder comprising a first disk, which is rotatable relative a second disk, and a first sensor ring and a second sensor ring. The first and the second sensor ring each have a multiplicity of first coupling electrodes and second coupling electrodes capacitively coupling to one another. The first coupling electrodes of a respective sensor ring have different coupling signal phases. The first sensor ring and the second sensor ring are matched to one another in such a way that an angle is determinable absolutely.

Abstract: Methods and apparatus for self test of safety logic in safety critical devices is provided in which the safety logic includes comparator logic coupled to a circuit under test (CUT) in a safety critical device and the self test logic is configured to test the comparator logic. The self test logic may be implemented as a single cycle parallel bit inversion approach, a multi-cycle serial bit inversion approach, or a single cycle test pattern injection approach.

Abstract: A technique for managing spare disk drives in a data storage system includes transferring segments of data from disk drives of an operating RAID group to spare regions on a set of spare disk drives to create unused space in the disk drives of the RAID group, thus using the spare regions to overprovision storage in the RAID group. Upon a failure of one of the disk drives in the RAID group, data of the failing disk drive are rebuilt based on the segments of data as well as on data from still-functioning disk drives in the RAID group. Thus, the spare disk drives act not only to overprovision storage for the RAID group prior to disk drive failure, but also to fulfill their role as spares in the event of a disk drive failure.

Abstract: The present invention includes a detecting capacitor of which the capacitance is changed depending on pressure; a fixed capacitor having reference capacitance; an initial voltage application part that applies an initial voltage having a predetermined frequency to the detecting capacitor and the fixed capacitor; a first operational amplifier that outputs an output voltage based on a partial voltage applied to at least the detecting capacitor; a reference voltage generation part that generates a reference voltage that serves as a reference for a change in the output voltage of the first operational amplifier and has the same frequency as that of the initial voltage; a second operational amplifier that outputs an output voltage based on the difference between the output voltage of the first operational amplifier and the reference voltage; and a pressure operation part that operates a pressure from the amplitude of the output voltage of the second operational amplifier.

Abstract: A transmission system, a receiver and a method for satellite signal transmission, wherein the satellite signals includes respective data streams consisting of a sequence of data packets. The method includes: subdividing the data packets of the data stream, through a splitter, into a first and at least one second data pseudo-streams; modulating the first and at least one second data pseudo-streams through a first and at least one second modulators, respectively; transmitting the modulated data pseudo-streams through respective transmission channels (Ch#1 . . . Ch#N), wherein, in order to generate the data pseudo-streams, the splitter will: select each data packet of the data stream; interrogate the modulators in a sequential manner in order to identify that modulator which, among the modulators, is available to accept the data packet, and send the latter to it; send a null data packet to the remaining modulators.

Abstract: A method for decoding a codeword transmitted over a channel demodulates data received over the channel to produce an initial estimate of belief messages for bits of the codeword and decodes the codeword using a belief propagation (BP) decoding that iteratively passes the belief messages between a set of variable nodes representing the bits of the codeword and a set of check nodes representing parity-check constraints on the bits of the codeword until a termination condition is met. The BP decoding selects a look-up table based on a probability of the belief messages and maps, using the look-up table, values of at least two incoming belief messages to values of at least one outgoing belief message that forms an incoming belief message in a subsequent iteration of the BP decoding.

Abstract: A technique for repairing a RAID (Redundant Array of Independent Disks) group in a data storage system following a failure of a disk drive in the RAID group includes identifying regions of the failed disk drive that supported unallocated storage extents and writing predetermined data to corresponding regions of the spare disk drive. Any reading of other disk drives in the RAID group may thus be limited only to those regions of the failed disk drive that supported allocated storage extents.

Abstract: In accordance with an embodiment of the invention, higher-speed outgoing data paths are used to transmit oversampled data signals, and corresponding slower-speed return data paths are used to receive return data signals. A channel-bonding control circuit measures the skew between the returned data signals and generates bit-slip and/or word-slip control signals to compensate for the skew. Transmission bit-slip (or, alternatively, clock-slip) circuits slip integer numbers of bits based on the bit-slip control signals. Bypass registers (or, alternatively, FIFO write or read enable signals) may be used to slip a whole word when the integer number of bits to slip is greater or equal to the parallel width of a lane. Various other aspects, features, and embodiments are also disclosed.

Abstract: An apparatus includes an output driver circuit and a trimming circuit. The output driver circuit may be configured to (i) receive an input signal and a first control signal and (ii) generate an output signal. The output signal may be a delayed version of the input signal. A length of delay between the input signal and the output signal is determined in response to the first control signal. The trimming circuit may be configured to generate the first control signal in response to a second control signal. The trimming circuit is generally enabled to vary a value of the first control signal to minimize a phase difference between the output signal and an output clock signal.

Abstract: The present disclosure describes a novel method and apparatus of using the JTAG TAP's TMS and TCK terminals as a general purpose serial Input/Output (I/O) bus. According to the present disclosure, the TAP's TMS terminal is used as a clock signal and the TCK terminal is used as a bidirectional data signal to allow serial communication to occur between; (1) an IC and an external controller, (2) between a first and second IC, or (3) between a first and second core circuit within an IC.

Abstract: A method of optimizing timing performance of an IC design is provided. The IC design is expressed as a graph that includes a plurality of paths. Each path includes a plurality of nodes that represent IC components including clocked elements and computational elements. The method optimizes the timing performance of the IC design by retiming a set of paths. The retiming includes skewing clock signals to a set of clocked elements by more than a clock period without changing the position of any clocked element relative to the position of the computational elements in the set of paths. The method performs simulation on the optimized IC design and provides the result of the simulation as a clock skew scheduling of the IC design instead of retiming of the IC design.

Abstract: A method and system for autonomously monitoring, evaluating, storing and testing tools and other units operated at a rig-site. The system may include a storage facility communicatively coupled to one or more tools, status flags identifying the health and operational status of the tools, and a computer for performing a self-check for determining the operational status for the one or more tools. The system may further include a remotely positioned computer system in communication with the operational status of the tools, and a user terminal in communication with the computer system.

Abstract: The present disclosure relates to a computer-implemented method for use with an electronic design. Embodiments include identifying, using one or more processors, a plurality of sibling nets associated with the electronic design and determining if the plurality of sibling nets have a same input slew rate. If the plurality of sibling nets do not have a same input slew rate, embodiments also include determining a delay calculation (DC) for each of the plurality of sibling nets. If the plurality of sibling nets do have a same input slew rate, embodiments further include sharing a stored DC with the plurality of sibling nets.

Abstract: A digital image is obtained from a camera in a smartphone and is processed by a processor on the smartphone to modify a part but not all of the pixels in a frame of the digital image, which is a digital video image, which is modified by image processing in accordance with a modification mask and reversible modification instructions, and is transmitted to a second smartphone with a display screen to display the modified image. Image processing data are transmitted to the second smartphone to enable restoring the original digital video image from the partially reversibly modified image and to be displayed in unmodified form on the display screen.

Abstract: Techniques for calibrating interleaved analog-to-digital converter (ADC) arrays are presented. A transceiver comprises an ADC component comprising an array of interleaved sub-ADCs, and an auxiliary path associated with an auxiliary sub-ADC used to facilitate calibrating a sampling array by comparing the auxiliary path signal to signals of the sub-ADCs in the array. A calibration component employs a phase-interpolator and analog delay lines to adjust the auxiliary sub-ADC to enable the auxiliary sub-ADC to be lined up to any one of the sampling instants of the sampling array. The calibration component compares the auxiliary signal to sub-ADC signals, determines path differences between the sub-ADC paths based on the comparison results, and calibrates the sub-ADCs and sub-ADC paths to reduce the path differences to mitigate distortion in a digital stream produced from combining the digital substreams produced by the sub-ADCs in the array.

Abstract: Disclosed is an improved real-time oscilloscope (“IRTO”) for generating a fast worst-case real-time eye diagram from an input signal. The IRTO may include signal conditioning circuitry, a digitizer, an acquisition memory, a clock and data recovery (“CDR”) module, a worst-case real-time eye diagram rendering (“WRTER”) module, and a display.

Abstract: Techniques for de-skewing transmitted data are described herein. In one example, a method can include detecting, via a processor, a number of data lanes that transmit data. The method can also include designating, via the processor, a number of buffers to store the data transmitted through each data lane, wherein the number of buffers is less than the number of data lanes. Additionally, the method can include detecting, via the processor, an alignment marker for each data lane. Furthermore, the method can include storing, via the processor, the transmitted data received from the data lanes in the buffers, and de-skewing, via the processor, the transmitted data when the alignment marker for each data lane has been detected.

Abstract: A communication system includes master host unit, hybrid expansion unit, and remote antenna unit. Master host unit communicates analog signals with service provider interfaces. Master host unit and hybrid expansion unit communicate N-bit words of digitized spectrum over communication link. Hybrid expansion unit converts between N-bit words and analog spectrum. Hybrid expansion unit and remote antenna unit communicate analog spectrum over analog communication medium. Remote antenna unit transmits and receives wireless signals over air interfaces. Master host unit includes master clock distribution unit that generates digital master reference clock signal. Master host unit communicates digital master reference clock signal over communication link. Hybrid expansion unit receives digital master reference clock signal from master host unit over communication link and generates analog reference clock signal based on digital master reference clock signal.

Abstract: A communication system includes master host unit, hybrid expansion unit, and remote antenna unit. Master host unit communicates analog signals with service provider interfaces. Master host unit and hybrid expansion unit communicate N-bit words of digitized spectrum over communication link. Hybrid expansion unit converts between N-bit words and analog spectrum. Hybrid expansion unit and remote antenna unit communicate analog spectrum over analog communication medium. Remote antenna unit transmits and receives wireless signals over air interfaces. Master host unit includes master clock distribution unit that generates digital master reference clock signal. Master host unit communicates digital master reference clock signal over communication link. Hybrid expansion unit receives digital master reference clock signal from master host unit over communication link and generates analog reference clock signal based on digital master reference clock signal.

Abstract: A communication system includes master host unit, hybrid expansion unit, and remote antenna unit. Master host unit communicates analog signals with service provider interfaces. Master host unit and hybrid expansion unit communicate N-bit words of digitized spectrum over communication link. Hybrid expansion unit converts between N-bit words and analog spectrum. Hybrid expansion unit and remote antenna unit communicate analog spectrum over analog communication medium. Remote antenna unit transmits and receives wireless signals over air interfaces. Master host unit includes master clock distribution unit that generates digital master reference clock signal. Master host unit communicates digital master reference clock signal over communication link. Hybrid expansion unit receives digital master reference clock signal from master host unit over communication link and generates analog reference clock signal based on digital master reference clock signal.

Abstract: A communication system includes master host unit, hybrid expansion unit, and remote antenna unit. Master host unit communicates analog signals with service provider interfaces. Master host unit and hybrid expansion unit communicate N-bit words of digitized spectrum over communication link. Hybrid expansion unit converts between N-bit words and analog spectrum. Hybrid expansion unit and remote antenna unit communicate analog spectrum over analog communication medium. Remote antenna unit transmits and receives wireless signals over air interfaces. Master host unit includes master clock distribution unit that generates digital master reference clock signal. Master host unit communicates digital master reference clock signal over communication link. Hybrid expansion unit receives digital master reference clock signal from master host unit over communication link and generates analog reference clock signal based on digital master reference clock signal.