Abstract: A data transmission circuit, method and memory device are provided. A comparison circuit is configured to compare global data with bus data to output a comparison result on whether the number of different bits between the global data and the bus data exceeds a preset threshold; a correction circuit is configured to check and/or correct the global data to generate corrected data; a first data conversion circuit is configured to invert the corrected data and transmit the inverted corrected data to the data bus when exceeding the preset threshold, and transmit the corrected data to the data bus when not exceeding the preset threshold, and the first data conversion circuit is further configured to output a mark signal; and a recovery circuit is configured to transmit data or inverted data on the data bus to a serial-parallel conversion circuit according to a value of the mark signal.

Abstract: Various aspects of the present disclosure generally relate to wireless communication. In some aspects, a user equipment (UE) may receive, in a downlink control information, a bit map identifying a plurality of feedback indicators for a plurality of uplink transmissions, wherein the plurality of feedback indicators includes more than one acknowledgment and/or negative acknowledgment; and retransmit one or more of the plurality of uplink transmissions based at least in part on receiving the bit map identifying the plurality of feedback indicators. Numerous other aspects are provided.

Abstract: A receiver adapted to receive a modulated signal including useful and interfering signals and to detect information bits carried thereon. The modulated signal comprises signal components each one associated with a respective modulation subcarrier and including respective useful and interfering signal components.

Abstract: A peripheral component interconnect express (PCIe) device error reporting optimization method includes acquiring advanced error reporting data of a PCIe device, executing a removal detection process of the PCIe device for detecting if the PCIe device is plugged into a connector, transmitting error log data of the PCIe device to a baseboard management controller and an advanced configuration and power interface according to the advanced error reporting data if the PCIe device is plugged into the connector, and filtering the error log data of the PCIe device so that filtered error log data is received by the baseboard management controller and the advanced configuration and power interface if the PCIe device and the connector are electrically disconnected.

Abstract: A data transmission circuit, a data transmission method, and a storage apparatus are provided. The data transmission circuit includes a check circuit, a comparison circuit, and a data conversion circuit. The check circuit is configured to generate check code data according to first data on a first data line, and combine the first data and the check code data into second data. The comparison circuit is configured to receive the second data and third data on the second data line, and compare the second data with the third data to output a comparison result indicating whether number of different bits between the second data and the third data exceeds a preset threshold. The data conversion circuit is configured to invert the second data and transmit the inverted second data to the second data line when the comparison result is indicative of exceeding the preset threshold.

Abstract: An apparatus for preventing physical intrusion on a data bus includes a data bus state sensor coupled to the data bus for monitoring a state of the data bus, a power circuit for generating multiple voltages supplied to functional circuitry in the apparatus, and a variable override circuit. The variable override circuit receives one or more voltages from the power circuit and selectively gates the voltages onto the data bus as a function of one or more control signals. A controller coupled to the variable override circuit, the power circuit and the state sensor receives state information from the state sensor and generates the control signals in response to detection of physical intrusion on the data bus. The controller controls a voltage level of at least one of the voltages generated by the power circuit for overriding the data bus when physical intrusion is detected on the data bus.

Abstract: Embodiments of methods, apparatuses, devices and/or systems for manipulating hierarchical sets of data are disclosed.

Abstract: A method and apparatus for processing a ciphertext based on homomorphic encryption. The method includes determining an approximate polynomial corresponding to a modulus reduction for bootstrapping a ciphertext based on samples extracted from the modulus reduction, and bootstrapping the ciphertext based on the approximate polynomial.

Abstract: A method for enabling and disabling Port Error detection and customizing corresponding error count threshold values. The method allows for adjustment of signal error verification thresholds before a connected port signals a loss of connection due to corrupted characters detected during normal operation and initialization on an IEEE-1394 serial bus. Also, the method customizes the limits for a Loss of Synchronization transition and reduces the probability for Bus Resets. Further, the method provides for a more stable bus operation, which is critical for usage in tight-looped and low-latency control systems.

Abstract: A data capturing device and a data calculation system and method are provided. The data capturing device transmits sensing data to a computing device, and receives a machine learning model and a library corresponding to a current scene from the computing device. The data capturing device runs the machine learning model to capture feature data from the sensing data, runs the library to convert a requirement into a service task, and then transmits the feature data and the service task.

Abstract: An image forming apparatus includes an operation device that is connected to the image forming apparatus and receives an operation to the image forming apparatus; a processing unit that performs a predetermined processing by a first application in the image forming apparatus or the operation device; an error detecting unit that detects the error in the processing by the first application; a control unit that starts up a second application to resolve the error upon the error is detected; a transmission unit that transmits error data formed based on the contents of the error from the first application to the second application; and a display unit that displays the operation screen of the second application based on the error data.

Abstract: A method includes storing a superset of data on a data storage medium along with a corresponding superset superparity. The superset of data includes multiple sets of data, and the corresponding superset superparity is calculated based on all of the multiple sets of data. The method also includes updating at least one subset of the superset of data. The subset has a subset superparity. The superset superparity is updated with the subset superparity, and the subset superparity and a location of the subset within the superset are employed to carry out error correction operations.

Abstract: A method for transmitting data, which is performed by a user equipment (UE), includes receiving, through a first carrier, an uplink (UL) grant for a second carrier, and transmitting UL data through the second carrier according to the UL grant, wherein a UL-DL configuration of the first carrier and a UL-DL configuration of the second carrier are different from each other, and wherein the UL grant includes a time domain resource assignment indicating a starting time for transmitting the UL data.

Abstract: The present disclosure relates to a pre-5th-generation (5G) or 5G communication system to be provided for supporting higher data rates beyond 4th-generation (4G) communication system such as a long term evolution (LTE). A method of a receiving apparatus in a communication system supporting a low density parity check (LDPC) code is provided. The method includes deactivating variable nodes of which absolute values of log likelihood ratio (LLR) values are greater than or equal to a first threshold value; changing LLR values of variable nodes of which absolute values of LLR values are less than a second threshold value among variable nodes other than the deactivated variable nodes to a preset value, and detecting LLR values of check nodes based on LLR values of the variable nodes other than the deactivated variable nodes.

Abstract: Methods for communicating are disclosed. A method includes obtaining at least one input communication symbol selected from a set of communication symbols, converting the at least one input communication symbol into at least one transmittable waveform using at least one defined spiral waveform function, and transmitting the at least one transmittable waveform over a communication channel. Example spiral waveform functions include spline-based piecewise functions and Archimedes spiral functions.

Abstract: A video device having data lanes and a method of operating the video device includes obtaining a stream of debug data in response to a test operation, framing the stream of debug data independent of establishing a video blanking period, and transmitting the framed stream of debug data across one or more data lanes of the video link for operation between a video source device and a video sink device. The method also includes generating a stream of video data related to the test operation, framing the stream of video data to establish a video blanking period, and transmitting the framed stream of debug data concurrently with the framed stream of video data across the one or more data lanes of the video link.

Abstract: There is provided a system for managing maintenance of a plurality of resources. The system may comprise a computerized maintenance management system configured to track maintenance activities of users across at least two clients. The system may also extract data representing performance or other trends. The system may also enable users to upload information, extract an information set from the uploaded information, generate one or more messages based on the information set, and transmit the messages to clients.

Abstract: A method for execution by a dispersed storage and task (DST) execution unit operates to receive a slice retrieval request from a requester that includes a slice name of one or slices to be retrieved; determine an access policy to apply to the slice retrieval request; determine a timestamp; and determine, based on the timestamp, when the one or more slices are available for retrieval. When the one or more slices are available for retrieval, the method operates further to determine when the one or more slices are currently available to the requester; retrieves the one or more slices from memory and sends the one or more slices to the requester, when the one or more slices are currently available to the requester.

Abstract: An apparatus includes a memory die including a group of storage elements and one or more unallocated redundant columns. A number of the unallocated redundant columns is based on a number of one or more bad columns of the memory die. The apparatus further includes a controller coupled to the memory. The controller is configured to receive data and redundancy information associated with the data from the memory. The data includes a first bit, and the redundancy information includes a second bit. The redundancy information is sensed from the one or more unallocated redundant columns and has a size that is based on the number of one or more bad columns. The controller is further configured to determine a value of the first bit based on one or more parity check conditions associated with the second bit.

Abstract: Methods for communicating are disclosed. A method includes obtaining at least one input communication symbol selected from a set of communication symbols, converting the at least one input communication symbol into at least one transmittable waveform using at least one defined spiral waveform function, and transmitting the at least one transmittable waveform over a communication channel. Example spiral waveform functions include spline-based piecewise functions and Archimedes spiral functions.

Abstract: A programmable logic controller includes a device that stores therein data, an authentication-information storage unit that stores therein authentication information, an authentication function unit that performs a user authentication based on the authentication information, and an encryption filter that has a plurality of encryption patterns. When writing of data to the device is requested, the authentication function unit performs the user authentication. When the user authentication is successful, the encryption filter performs the encryption processing to the data with the encryption pattern set in advance by the user to write the data to the device, and when the user authentication fails, the encryption filter performs the encryption processing to the data with one of the encryption patterns that is different from the encryption pattern set in advance by the user to write the data to the device.

Abstract: Systems and methods are provided to automatically analyze performance of an automatic memory management system. One example embodiment involves automatically gathering, using at least one processor of the server, garbage collection information associated with the garbage collection process and storing the garbage collection information in a garbage collection output file of a file system. The garbage collection output file may be analyzed to identify a plurality of flags associated with a performance of the server system that does not meet one or more performance thresholds. In certain embodiments, a first flag of the plurality of flags is associated with a first portion of the garbage collection information, and a second flag of the plurality of flags is associated with a second portion of the garbage collection information that is different from the first portion of the garbage collection information.

Abstract: In embodiments of a serializing transmitter, the serializing transmitter includes N multiplexing drive units, each configured to generate a series of output pulses derived from input data signals and multi-phase clock signals, and each multiplexing drive unit including a pulse-controlled push-pull output driver having first and second inputs and an output. Each multiplexing driver unit further includes a first M:1 pulse-generating multiplexer having an output coupled to the first input of the pulse-controlled push-pull output driver, and a second M:1 pulse-generating multiplexer having an output coupled to the second input of the pulse-controlled push-pull output driver, wherein each of the first and second M:1 pulse-generating multiplexers has four or fewer clock inputs.

Abstract: A data reception apparatus obtains an integrated number of bits by integrating the numbers of bits of a bit string, obtains an integrated number of samples by integrating the number of samples obtained by oversampling each bit, obtains an approximated line that indicates correspondence between the integrated number of bits and the integrated number of samples, determines, based on the approximated line, a bit length of a bit string corresponding to a segment in which identical values continue in oversampling data after the integrated number of samples. Even when a receive-side clock source has a degree of clock frequency error against a transmit-side clock source, how many samples one bit of the bit string corresponds to is obtained with an accuracy higher than a period of oversampling (inverse of the number of samples).

Abstract: An integrated circuit includes a plurality of receivers, each having a clock and data recovery circuit. A first local clock recovery circuit in a first receiver can be caused to produce a test clock which simulates a condition to be tested, and while a second receiver in the plurality of receivers that includes a second local clock recovery circuit is caused to use the test clock in place of the reference clock while receiving a test data sequence at its input. The clock and data recovery circuits in the receivers can include clock control loops responsive to loop control signals to modify the selected reference clock to generate the local clock in response to selective one of (i) a corresponding data signal for normal operation or during a test, and (ii) a test signal applied to the clock control loop in which case the test clock is produced.

Abstract: An edge interval measuring block measures a first same-edge interval. A bit number detector detects the number of bits in the first same-edge interval based on reference bit length information and detects a first number of bits in a same-value interval between consecutive bits of the same value by subtracting the number of bits in the known bit stream from the number of bits in the first same-edge interval. The edge interval measuring block then measures a second same-edge interval. The bit number detector detects the number of bits in the second same-edge interval based on the reference bit length information and detects a second number of bits in a bit stream of consecutive bits of the same value opposite to the value in the same-value interval by subtracting the first number of bits from the number of bits in the second same-edge interval.

Abstract: A method and device are provided for transmitting a digital signal intended for a network having at least four nodes including two transmitters, a relay and a receiver separated from one another by non-orthogonal links, except between the relay and the destination, between which the link is orthogonal, implementing a spatially distributed network code. The method includes: encoding, in each transmitter, supplying a code word for every block of K bits of information; transmitting, in the transmitters, the code word during ?N transmission intervals, ??[0,1]; jointly, iteratively detecting/decoding, in the relay, in order to separate interfering streams from the transmitters and to determine, for each stream, a vector representing the K bits of information associated with the code word; jointly encoding, in the relay, the two vectors in order to determine redundancy information, and scheduling the relays to transmit the redundancy information during the (1??)N following transmission intervals.

Abstract: The accuracy of data processing operations in implantable medical devices is improved through reductions in errors associated with data acquisition, reading, and transmission. In one embodiment, two or more circuit modules of the device are operated at different clock speeds and a voting scheme is utilized to obtain a valid data value from one of the modules. The disclosure describes methods, devices and systems that utilize the voting schemes to eliminate errors induced by race conditions in obtaining the valid data values by obtaining a plurality of data samples during operation of the circuit modules at the different clock speeds and selecting from among the data samples the valid data value.

Abstract: Disclosed is a method for transmitting control information on uplink multi-antenna transmission from a base station and the method includes: transmitting DCI that schedules uplink transmission of a first data block and a second data block through a PDCCH; receiving the first and second data blocks scheduled by the DCI; transmitting information indicating ACK or NACK for the received first and second data blocks, respectively, by using a first PHICH for the first data block and a second PHICH resource for the second data block; receiving a retransmission for a negative-acknowledged data block; and transmitting information indicating ACK or NACK of the retransmission of the negative-acknowledged data block by using the first PHICH resource when the number of negative-acknowledged data blocks is not identical to the number of data blocks that the PDCCH indicates.

Abstract: An apparatus is provided, for performing a direct memory access (DMA) operation between a host memory in a first server and a network adapter. The apparatus includes a host frame parser and a protocol engine. The host frame parser is configured to receive data corresponding to the DMA operation from a host interface, and is configured to insert markers on-the-fly into the data at a prescribed interval and to provide marked data for transmission to a second server over a network fabric. The protocol engine is coupled to the host frame parser. The protocol engine is configured to direct the host frame parser to insert the markers, and is configured to specify a first marker value and an offset value, whereby the host frame parser is enabled to locate and insert a first marker into the data.

Abstract: Disclosed is a data transmission method in a wireless network capable of improving transmission performance on a wireless network by transmitting data, on which ACK is piggybacked, using the ACK transmission opportunity having high priority. The data transmission method includes acquiring a wireless channel by a STA to transmit a first data to the AP, transmitting the first data by the STA acquired the wireless channel to the AP through the wireless channel, analyzing by the AP whether there are second data intended to any one of the plurality of STAs, and, if there are the second data to transmit, transmitting the second data, on which an ACK is piggybacked, to the intended STA from the AP using ACK transmission opportunity having higher priority than that of data transmission.

Abstract: One aspect of the present invention concerns the management of processing resource allocations for a Turbo receiver, where such resources are consumed from a finite resource budget within a defined processing time interval. The contemplated Turbo receiver attempts to allocate more processing resources to those demodulation and/or Turbo decoding tasks that make more valuable contributions with respect to the ultimate goal of successfully decoding all data streams that are of interest in a received signal. The advantageous management approach allows the Turbo receiver to obtain better results for a given consumption of processing resources, and further permits the Turbo receiver to quit upon either achieving a successful outcome within a defined processing time interval or exhausting the budgeted resources.

Abstract: A memory system connected to another apparatus via a data crossbar, has a first memory, a second memory that forms a dual configuration together with the first memory, a first memory controller that transmits or receives data to be written into the first memory or data read out from the first memory to or from the other apparatus, a second memory controller that transmits or receives data to be written into the second memory or data read out from the second memory to or from the other apparatus, and a system controller that instructs the first memory controller and the second memory controller to read out, from the first memory and the second memory, data requested to be read out by the other apparatus if the system controller detects that any one of the first data crossbar and the second data crossbar being not capable of transmitting or receiving data.

Abstract: Disclosed is a display device including a first storage unit having driving data for driving a display panel and a first check SUM data on the driving data stored therein, a second storage unit for retrieving the driving data and the first check SUM data from the first storage unit and storing the driving data and the check SUM data in response to the instruction of a ROM interface, and a data error detection/correction unit generating a second check SUM data with reference to the driving data stored in the second storage unit.

Abstract: A method, control module and system of a vehicle including at least a first and a second control computer each containing a number of local Digital Control Modules and at least one Actuator Control Module wherein the Actuator Control Module of each control computer is operatively connected to all local Digital Control Modules of the same control computer, wherein the Actuator Control Module of each control computer is further operatively connected to all Digital Control Modules of the electrical system in a manner that enables each Actuator Control Module of the system to receive internal data of each Digital Control Module of the electrical system.

Abstract: Provided are a method and apparatus of performing a HARQ in a multiple carrier system. A receiver determines the size of a soft buffer to be used in an effective HARQ process on the basis of the maximum number of effective HARQ processes over a plurality of component carriers and stores the received transport block in the soft buffer. The present invention enables the performance of a HARQ in an efficient manner by using multiple carriers in the event the size of the soft buffer is limited.

Abstract: Failing bus lane detection using syndrome analysis, including a method for receiving a plurality of syndromes of an error detection code, the error detection code associated with a plurality of frames that have been transmitted on a bus that includes a plurality of lanes and is protected by the error detection code. The method includes performing for each of the lanes in each of the syndromes: decoding the syndrome under an assumption that the lane is a failing lane, the decoding outputting a decode result; determining if the decode result is a valid decode; and voting for the lane in response to determining that the decode result is a valid decode. A failing lane is then identified in response to the voting, with the failing lane being characterized by having more votes than at least one other lane on the bus.

Abstract: A receiver of a wireless communication system and method thereof include antennas configured to receive data, wherein the data comprises a preamble, a header, and a payload. The receiver also includes a synchronizer configured to perform time synchronization of the data received through corresponding paths of each antenna using corresponding preambles of the data. The receiver includes a header detector configured to detect a header from the data of each of the paths. A surviving path selector in the receiver is configured to select a signal of a surviving path from among the paths based on the header or the preamble. The receiver also includes combiner configured to combine the signal existing in the surviving path to demodulate the payload.

Abstract: A method of securing bus architecture from a Trojan attack. A restricted address access detector generates an unauthorized access detection signal when a master ID signal is within a restricted range. The unauthorized access detection signal disables the requested slave select signal, and the address decoder instead outputs a default slave select signal. A counter determines the duration of a lock signal from a master, and a comparator activates a malicious bus lock signal if the lock signal duration exceeds a threshold. The master mask register forcibly gates the lock signal upon receipt of the malicious bus lock signal. If the duration of a wait request from a slave exceeds a maximum duration register value, a comparator activates a malicious wait detection signal to disable the wait request signal. The method might include storing identifying information about the malicious master and storing a slave ID corresponding to the malicious slave.

Abstract: A method includes accepting an input code word, which was produced by encoding data with an Error Correction Code (ECC), for decoding by a hardware-implemented ECC decoder. The input code word is pre-processed to produce a pre-processed code word, such that a first number of bit transitions that occur in the hardware-implemented ECC decoder while decoding the pre-processed code word is smaller than a second number of the bit transitions that would occur in the ECC decoder in decoding the input code word. The pre-processed code word is decoded using the ECC decoder, and the data is recovered from the decoded pre-processed code word.

Abstract: Methods and apparatus enable ATSC-M/H mobile devices to conserve power by entering a high power state at a slot reception start time that is after the start of an ATSC M/H slot and entering a low power state at a slot reception stop time before the end of the ATSC M/H slot. Data lost due to the device being in a low power state during the time between the start time of the ATSC M/H slot and the activation time and during the time between the deactivation time and the end of the ATSC M/H slot are recovered using error correction processing. The slot receive and slot reception stop times may be based on the received signal quality. The receiver circuitry may also be deactivated when the entire payload has been received and skip reception of remaining slots.

Abstract: A pulse response for a receiver, as an array PR, is found from the receiver's symbol stream. For a continuous stream of arbitrary data, a value of the array PR[k] can be determined from the signal levels of the symbols received. The stream of received data is input to a FIFO. Between the first and last locations of the FIFO is the symbol referred to herein as Dn. Symbols located in the FIFO before Dn are referred to as Dn?x. Symbols located in the FIFO after Dn are referred to as Dn+x. Dn differs from the other FIFO symbols in that its signal level can be measured with an adjustable error slicer. The ISI effect of any Dn?k upon Dn can be measured, and thus any PR[k] measured, by measuring the average signal level of Dn when only certain types of data streams occur in the FIFO.

Abstract: Systems and methods are disclosed for detecting temporary high level impairments, such as noise or interference, for example, in a communications channel, and subsequently, mitigating the deleterious effects of the dynamic impairments. In one embodiment, the method not only performs dynamic characterization of channel fidelity against impairments, but also uses this dynamic characterization of the channel fidelity to adapt the receiver processing and to affect an improvement in the performance of the receiver. For example, in this embodiment, the method increases the accuracy of the estimation of the transmitted information, or similarly, increases the probability of making the correct estimates of the transmitted information, even in the presence of temporary severe levels of impairment. The channel fidelity history may also be stored and catalogued for use in, for example, future optimization of the transmit waveform.

Abstract: Various embodiments of the present invention provide systems and methods for data processing. For example, a method for data processing is disclosed that includes receiving a codeword that has at least a first circulant with a plurality of data bits and a first circulant parity bit, a second circulant with a plurality of data bits and a second circulant parity bit, and one or more codeword parity bits. The methods further include decoding the codeword using the one or more codeword parity bits to access the first circulant and the second circulant, performing a first circulant parity check on the first circulant, and performing a second circulant parity check on the second circulant.

Abstract: In a magnetic data processing device, an input part sequentially receives magnetic data output from a magnetic sensor. A storage part stores a plurality of the magnetic data as a data set of statistical population. An index derivation part derives a distribution index of the data set of the statistical population. A reliability determination part determines whether or not reliability of the data set of the statistical population is acceptable based on the distribution index and a decision criterion. A decision criterion setting part increases strictness of the decision criterion when the reliability determination part determines that the reliability of the data set of the statistical population is acceptable, and decreases the strictness of the decision criterion when the reliability determination part determines that the reliability of the data set of the statistical population is unacceptable.

Abstract: Provided is a test apparatus that tests a device under test, comprising a test unit that sends and receives signals to and from the device under test; and a control apparatus that controls the test unit. The control apparatus includes a first buffer and a second buffer that buffer access requests to the test unit; a data output section that buffers, in the first buffer, access requests to be sent from the control apparatus to the test unit and, when an error occurs, buffers the access requests in the second buffer instead of the first buffer; and a transmitting section that sequentially transmits the access requests in the first buffer to the test unit and, when an error occurs, sequentially transmits the access requests in the second buffer to the test unit.

Abstract: A communication system that performs encoding and decoding for communication includes a transmitting apparatus and a receiving apparatus. The transmitting apparatus includes a turbo encoding unit including a first encoding unit that encodes an input signal and generates a first parity bit by bit-based encoding and n (n=1, 2, 3, . . . ) second encoding units that encode the input signal and generate second parity bits by bit-based encoding, and a symbol mapping unit that maps an output from the turbo encoding unit to a symbol by bit-based mapping operation and modulates the output. And the receiving apparatus includes a demodulating unit that demodulates a transmission signal, and a turbo decoding unit that performs turbo decoding on the demodulated signal by bit-based decoding.

Abstract: A data protecting method for a portable memory storage apparatus is provided. The method includes determining whether a mode signal is at a data protecting mode, and performing a file hiding procedure to change a file allocation table if the mode signal is at the data protecting mode, wherein a host system coupled to the portable memory storage device is allowed to only access a portion of logical addresses of the portable memory storage apparatus according to the changed file allocation table and files stored in the portable memory storage apparatus before the file hiding procedure are written into another portion of the logical addresses. Additionally, the method still includes performing a file showing procedure to change the file allocation table if the mode signal is not at the data protecting mode, wherein the host system may access all the logical addresses according to the changed file allocation table.

Abstract: A method of handling a stuck bit in a directory of a cache memory, by defining multiple binary encodings to indicate a defective cache state, detecting an error in a tag stored in a member of the directory (wherein the tag at least includes an address field, a state field and an error-correction field), determining that the error is associated with a stuck bit of the directory member, and writing new state information to the directory member which is selected from one of the binary encodings based on a field location of the stuck bit within the directory member. The multiple binary encodings may include a first binary encoding when the stuck bit is in the address field, a second binary encoding when the stuck bit is in the state field, and a third binary encoding when the stuck bit is in the error-correction field. The new state information may also further be selected based on the value of the stuck bit, e.g.

Abstract: A computer system of this invention includes: plural servers; a L7 switch that assigns a processing request from a client terminal to one of the servers; and a session management server that holds and manages handover data that includes handover identification information, which is at least either client terminal identification information or user identification information, and that is data necessary for continuously carrying out the business processing the server carried out.