Abstract: A device comprises a processor arranged to automatically execute boot code upon start-up or reset. The boot code comprises a code authentication procedure to verify whether additional code is authenticated for execution on the processor. A separate security unit comprises a private unlock key and cryptography logic configured to use the private unlock key to sign a portion of data, thereby generating a signed unlock file for supply to a storage location. The processor is arranged to access the unlock file from the storage location, making it available without requiring connection to the security unit. The boot code further comprises an unlocking authentication procedure configured to check for the unlock file in the storage location, and if available to verify whether the unlock file is authenticated for use on the processor based on its signature, so as to de-restrict the boot authentication procedure on condition of verifying the unlock file.

Abstract: An unequal error protection scheme for borehole telemetry. The scheme, when applied to imaging applications, assigns more protection for the more significant bits and less protection for less significant bits. When applied to communication using channels of different quality, more protection is provided for channels of poor quality.

Abstract: Systems, methods, apparatus, devices and computer program products enhance uplink inter-cell interference cancellation with HARQ retransmissions. The decoding of a data packet depends on whether the interfering packet was decoded. Since the interfering packet is itself transmitted using a HARQ process, the transmission by the victim UT can be accomplished to take this situation into account. The latency of the victim UT can be varied based on the need for energy efficient transmission. In accordance with one specific aspect, if the receiver can decode multiple packets simultaneously, high data rates can be achieved using packet pipelining.

Abstract: An error correction method for correcting an first ECC code from a storage unit, comprising: (a) marking at least a first part of the first ECC code according to a correction result generated by correcting error of the first ECC code, to generate a first error correction reference information; and (b) marking at least a second part of the first ECC code according to the first error correction reference information to generate a second error correction reference information.

Abstract: Memory apparatus and methods utilizing multiple bit lanes may redirect one or more signals on the bit lanes. A memory agent may include a redrive circuit having a plurality of bit lanes, a memory device or interface, and a fail-over circuit coupled between the plurality of bit lanes and the memory device or interface.

Abstract: Memory apparatus and methods utilizing multiple bit lanes may redirect one or more signals on the bit lanes. A memory agent may include a redrive circuit having a plurality of bit lanes, a memory device or interface, and a fail-over circuit coupled between the plurality of bit lanes and the memory device or interface.

Abstract: Redundant acknowledgment between agents performing a loopback test over bidirectional communications bus is described. In one example, in a processor including a communications agent coupled to a bidirectional communications bus, the communications agent initiates loopback communications to a second agent, sends a packet including a redundant acknowledgment sequence to the second agent, receives the packet including the redundant acknowledgement sequence looped back from the second agent, determines whether the received redundant acknowledgment sequence is valid, sends a test sequence to the second agent, receives the test sequence looped back, and if the received redundant acknowledgment sequence is determined to be valid, then checks the received test sequence.

Abstract: A system and method for verifying the receive path of an input/output device such as a network interface circuit. The device's operation with various different input sources (e.g., networks) and output sources (e.g., hosts, host buses) is modeled in a verification layer that employs multiple queues to simulate receipt of packets, calculation of destination addresses and storage of the packet data by the device. Call backs are employed to signal completion of events related to storage of packet data by the device and modeling of data processing within the verification layer. Processing of tokens within the verification layer to mimic the device's processing of corresponding packets is performed according to a dynamic DMA policy modeled on the device's policy. The policy is dynamic and can be updated or replaced during verification without interrupting the verification process.

Abstract: A transmission method includes generating a control information signal relating to control information of a data signal. A transmission frame is formed by repeating and discretely arranging the same control information signal. The data signal and the control information signal are transmitted using the transmission frame.

Abstract: An information processing device having two processing units capable of operating in synchronization with each other, includes: a common unit capable of outputting an identical signal to the two processing units; detection units that are respectively provided for the processing units and each detects errors occurred in corresponding processing unit respectively; a comparison unit that compares outputs from the two processing units; and a control unit that controls signals from the processing units to the common unit, based on a detection result of the detection units and a comparison result of the comparison unit, and determines, if errors of an identical type are simultaneously detected by the detection units, that the errors are due to an error of the common unit.

Abstract: A method, device, and system are disclosed. In one embodiment method includes determining a left edge and right edge of a valid data eye for a memory. The method continues by periodically checking the left and right edges for movement during operation of the memory. If movement is detected, the method retrains the valid data eye with an updated left edge and right edge.

Abstract: A test circuit can use a simple test pattern data without customization for each substrate and considerably reduce a test preparation process. A connection test circuit is generated by receiving the input of the data of the connection relation indicating the devices mutually line-connected among a plurality of devices, the number of connection lines corresponding to the respective connection relations, and the device outputting a test result, sequentially searching for a connection destination device from the output terminal of an output device, and embedding a test circuit module in a test route.

Abstract: A memory hub device with test logic is configured to communicate with memory devices via multiple hub device ports, and is also configured to communicate on one or more busses in an upstream and downstream direction. The test logic includes a built-in self test apparatus providing logic to simultaneously and independently test the memory devices interfaced to one or more of the hub device ports using read and write data patterns. The test logic also includes configuration registers to hold fault and diagnostic information, and to initiate one or more tests. The memory hub device can further include command collision detection logic, a trace array, buffer transmit mode logic, trigger logic, clock adjustment logic, transparent mode logic, and a configured command sequencer, as well as additional features.

Abstract: Systems, controllers and methods are disclosed, such as an initialization system including a controller that receives patterns of read data coupled from a memory device through a plurality of read data lanes. The controller is operable to detect any lane-to-lane skew in the patterns of read data received through the read data lanes. The controller then adjusts the manner in which the read data received through the read data lanes during normal operation are divided into frames. The controller can also couple patterns of command/address bits to the memory device through a plurality of command/address lanes. The memory device can send the received command/address bits back to the controller through the read data lanes. The controller is operable to detect any lane-to-lane skew in the patterns of command/address bits received through the read data lanes to adjust the manner in which the command/address bits coupled through the command/address lanes during normal operation are divided into frames.

Abstract: Memory apparatus and methods utilizing multiple bit lanes may redirect one or more signals on the bit lanes. A memory agent may include a redrive circuit having a plurality of bit lanes, a memory device or interface, and a fail-over circuit coupled between the plurality of bit lanes and the memory device or interface.

Abstract: Redundant acknowledgment between agents performing a loopback test over bidirectional communications bus is described. In one example the acknowledgment is performed by initiating loopback communications from a first agent to a second agent, sending a packet including a redundant acknowledgment sequence from the first agent to the second agent, receiving the packet including the redundant acknowledgement sequence looped back from the second agent at the first agent, sending a test sequence from the first agent to the second agent, and receiving the test sequence looped back from the first agent.

Abstract: In a high-speed serial link, an eye finder diagnostic circuit has improved performance by being on-chip with the existing capture latch(es) of a receive equalizer. The eye finder circuit employs an additional capture latch with its input tied to the same input node as the existing capture latch(es) of a receive equalizer. The additional capture latch has a clock input and reference voltage input. The clock input is adjusted through a phase interpolator (or variable delay line) while the reference voltage input is adjusted by a voltage generator. A digital post processing circuit then compares the output of the additional capture latch with the output of the other existing capture latch(es), in order to determine the receive eye opening. The horizontal eye opening is measured by changing the phase of the additional capture latch through the phase interpolator, while the vertical eye opening is measured by changing the reference voltage of the voltage generator of the additional capture latch.

Abstract: An apparatus and associated methodology are provided to generate system test libraries for solution testing involving heterogeneous devices from different vendors. A unified user interface employs received information to execute the tests based on provided device and network topology libraries, generating the system library to perform the required end-to-end system testing. The unified user interface and the library generation mechanism provide a layer of abstraction avoiding complexities of the system configuration commands native to disparate devices.

Abstract: A serial point to point link that communicatively couples an integrated circuit (IC) device to another IC device is initialized by transferring a training sequence of symbols over the link. Registers of the IC device are programmed, to set a symbol data pattern and configure a lane transmitter for the link. A start bit in a register of the IC device is programmed, to request that the link be placed in a measurement mode. In this mode, the IC device instructs the other IC device to enter a loopback mode for the link. The IC device transmits a sequence of test symbols over the link and evaluates a loopback version of the sequence for errors. The sequence of test symbols have a data pattern, and are transmitted, as configured by the registers. Other embodiments are also described and claimed.

Abstract: A method for testing an integrated circuit having an array of resistivity changing cells, wherein the method includes selecting a plurality of cells, setting the state of each selected cell to a defined state, measuring a resistance value being dependent on the resistances of the selected cells, comparing the resistance value with a resistance target value, and classifying the integrated circuit in dependence on the result of the comparison.

Abstract: A method and apparatus provide a receiver with an architecture to regulate a bit error rate of the receiver using an offset based on detecting false transitions in received data. In an embodiment, such false transitions in data may be determined in a bang-bang detector.

Abstract: A loopback test to test a communication link for a layered interface where in a master agent programs the electrical parameters for the slave agent, such as, the offset, timing, and current compensation with a loopback control register. The slave and master agent to support an entry into the loopback test based on detection of a header within a packet. The slave and master agent to support exit out of the loopback test based on whether the loop count is finite.

Abstract: A method for selecting members in a hierarchy includes determining a sequence of one or more actions associated with a member selection tree. The actions collectively selecting one or more members from a hierarchy of members. The hierarchy of members is associated with a particular dimension of an organization of data. The method further includes recording the sequence of actions in a member selection script. In addition, the method includes executing the member selection script to select one or more members after the hierarchy of members has been modified.

Abstract: File management method having first and second processing modes for storing file type information for discrimination between first and second processing modes in recording medium as file management information associated with file for file management. In first processing mode, when data in the form of file is written on a recording medium and a write error occurs, replacement processing to another write area is performed to write the data in another area. In second processing mode, when write error occurs, the replacement processing to other write area is not performed to write the data. Method includes reading file type information associated with a file to be processed from recording medium, converting the file type from file type indicative of first processing mode to file type indicative of second processing mode, and writing the file type after conversion in recording medium as file management information associated with the file to be processed.

Abstract: Communications equipment can be tested using a test pattern that is modified compared to, and more exploitive than, a standard test pattern. Test patterns can be employed that have lengthened or shortened consecutive identical digit (CID) portions, or that have lengthened or shortened pseudo random bit sequence (PRBS) portions. In some cases, PRBS polynomials are not re-seeded after each CID. Further, different order polynomials can be employed for different applications. Exemplary applications can include test equipment and built-in self-test capability for integrated circuits.

Abstract: The communication system includes two communication channels for communication of protection and control information between two protective relays on a power line portion of an electric power system. A switch provided at the receiving relay connects one communication channel and provides a connecting link between the communication channel and the receiving relay. The transmitted data is applied on both communication channels and processed substantially identically. When the one communication channel is indicated to be faulty, the switch in the receiving relay is operated to connect the second communication channel, thereby substantially preventing delay in the receipt of the data from the transmitting relay.

Abstract: This invention relates to the measurement of the accuracy of a communication channel. The invention provides a method and apparatus for determining channel degradation information for a communications channel, in which a known data sequence is generated within a transmitter; a coded data sequence based on the known data sequence is transmitted using the transmission channel; said known data sequence is generated within the receiver; and the known data sequence generated within the receiver is compared with a decoded data sequence based on data received via the channel to provide said channel degradation information; wherein a source encoder in the transmitter has the ability to generate a predetermined output data sequence in response to a predetermined input data sequence; the known data sequence is generated within the transmitter and within the receiver in dependence upon the predetermined output data sequence; and the decoded data sequence is measured prior to source decoding in the receiver.

Abstract: A method for overriding interference in a reproduced audio signal which is derived from a digital signal, the reproduced audio signal being attenuated as a function of data error statistics of the digital signal, which is distinguished by the fact that a substitute signal is superimposed on the attenuated audio signal as a function of the data error statistics of the digital signal. The method advantageously ensures that, even in the case of very noisy digital input signals, a signal is acoustically reproduced at any time, so that the volume set on an appropriately equipped radio receiver is able to be anticipated realistically for the user at any time. This avoids deceiving the user about the volume of the reproduction that is actually set, which in the case of a very noisy received signal, as a result of the interruption of an audio reproduction, is no longer determinable according to the related art.

Abstract: A method for providing packet loss recovery in a data packet-based network used for real-time multimedia communications. In accordance with a first illustrative embodiment of the present invention, the information payload associated with a given data packet k is identically copied and appended to data packet k+w (i.e., the information payload is repeated with a delay of w transmitted packets). More generally, the present invention provides a method of coding a sequence of data packets representing a contiguous stream of information, with each data packet comprising, a set of payload information representative of a segment of the stream of information corresponding thereto.

Abstract: A method for testing a signal path for mark ratio tolerance includes generating a varying test pattern by selecting between a first pattern and a second pattern according to a defined sequence; and sending the varying test pattern over the signal path. An apparatus disposed in a communication system includes a selection circuit for generating a varying test pattern to send over the signal path, the selection circuit generating the varying test pattern by selecting between a first pattern and a second pattern according to a select sequence signal, and a sequencer coupled to the selection circuit, the sequencer providing the select sequence signal to the selection circuit, the sequencer generating the select sequence signal according to a mode value. The mark ratio tolerance of a system can be tested, varying the data density of one portion of the signal path while maintaining a constant data density on another portion of the signal path.

Abstract: A method and system for reporting the status of a digital transmission line element, such as a regenerative repeater or a network interface unit, to a remote location. The line element is interconnected to a digital transmission line and receives a data stream via the transmission line from the remote location. The data stream follows predetermined coding rules. In a loopback mode, the line element loops back the data stream via the transmission line to the sending end. The line element includes a detector and an error generator. The detector senses a status query signal in the data stream and responsively enables the error generator to then selectively introduce error message into the data stream being looped back along the transmission line. The error message may then be detected at a remote location to a provide information regarding the line element, such as its location or operating mode.

Abstract: A method for maximizing satellite downlink information rate is disclosed. A ground transmitter (102) applies an outer block code to a data channel, modulates it, and transmits an uplink data stream (104) to a satellite (106) which demodulates the uplink data stream to produce a demodulated uplink data stream consisting of 1 to N user channels (230). The method uses a first multiplexer (232) to produce 1 to M multiplexed data signals (234) which are fed into quality encoders (236). The quality encoders (236) encode the multiplexed data signals (234) according to a selected quality level to produce custom-coded data signals (238). The level of coding applied to the custom-coded data signals (238) may be controlled by information received by a channel measurement element (250). Next, the method passes the custom-coded data signals (238) into a second multiplexer (240) which produces one multiplexed data stream (242).

Abstract: An improved system for allowing a digital transmission line element, such as a regenerative repeater or a network interface unit, to communicate with a remote location. The line element is interconnected to a digital transmission line, which receives an incoming data stream. The data stream follows predetermined coding rules. The line element includes a detector and an error generator. The detector senses when a status inquiry is made and responsively enables the error generator to then selectively introduce an error message into an outgoing data stream along the digital transmission line. The error message may then be detected at a remote location to a provide information regarding the line element, such as its location or operating mode.