Abstract: A failure detector circuit of one embodiment acquires a first signal while transmitted from a first circuit to a second circuit and acquires a second signal while transmitted from the second circuit to a third circuit. The second circuit is located between the first circuit and the third circuit and transmits, to the third circuit, as the second signal, the first signal or a third signal having a given fixed state. The failure detector circuit outputs a fourth signal indicating detection or non-detection of a failure in the second circuit, in accordance with the first signal and the second signal.

Abstract: A method for operating a Low Density Parity Check (LDPC) decoder includes assigning each symbol of a codeword as a variable node value for each of a plurality of variable nodes, performing syndrome checking on each check node based on a parity check matrix, calculating flipping function values of the variable nodes based on syndrome values of check nodes and a flipping function, dividing the flipping function values into a plurality of groups, determining a flipping function threshold value based on a group maximum value of a group among the groups, and selectively flipping a variable node value based on a comparison result of a flipping function value of corresponding variable node and the determined flipping function threshold value.

Abstract: In an aspect of the disclosure an apparatus, e.g., a base station, maybe configured to receive, from a UE, ACK/NACK feedback indicating that a subset of CBGs of a set of transmitted CBGs failed to be properly decoded. The apparatus maybe further configured to retransmit the subset of CBGs based on the ACK/NACK feedback and transmit information indicating the CBGs being retransmitted. In one configuration, a TB of new data maybe transmitted with the retransmitted subset of CBGs in a subframe/slot. In an aspect, a UE may be configured to determine that one or more CBGs of a received set of CBGs failed to be properly decoded at the UE, and send ACK/NACK feedback indicating the one or more CBGs that failed to be decoded. The UE maybe further configured to receive a retransmission of CBGs in the set of CBGs, and information indicating the retransmitted CBGs.

Abstract: A server system is described. The server system comprises first motherboard having first processor module coupled to first memory module, second motherboard having second processor module coupled to second memory module, first back plate having first PCIE switch chip coupled to second PCIE switch chip via PCIE transmission channel. The first processor module is coupled to the first PCIE switch chip and the second processor module is coupled to the second PCIE switch chip. The first processor module converts the memory data of the first memory module into PCIE packet data to be transmitted to the second processor module by first PCIE switch chip and second PCIE switch chip. The second processor module converts the received PCIE packet data into memory data of second memory module for synchronizing the memory data of first motherboard and the second motherboard.

Abstract: Methods and systems are disclosed for communicating in a wireless communications system utilizing a plurality of frequency bands for downlink (DL) transmission and a plurality of frequency bands for uplink (UL) transmission. In an embodiment, a mobile device receives a DL signal via a DL frequency band. The DL signal contains DL-UL frequency-band association information. The DL signal is decoded to obtain the DL-UL frequency-band association information which is used to determine a UL frequency band for UL transmission. The mobile device configures its radio-frequency (RF) circuitry to operate in the UL frequency band for UL transmission.

Abstract: A system and method for testing line state. Traffic through a communications path is determined. A test vector is generated. Attributes of the test vector simulate the traffic. The test vector is communicated to one or more end devices. Performance information for each of the attributes of the test vector is measured. A performance map utilizing the attributes and the performance information is generated.

Abstract: Systems and methods are provided for enhancing the performance and throughput of a low-density parity check (LDPC) decoder. In some embodiments, the enhanced performance and throughput may be achieved by detecting and correcting near-codewords before the decoder iterates up to a predetermined number of iterations. In some embodiments, a corrector runs concurrently with the decoder to correct a near-codeword when the near-codeword is detected. In alternate embodiments, the corrector is active while the decoder is not active. Both embodiments allow for on-the-fly codeword error corrections that improve the performance (e.g., reducing the number of errors) without decreasing the throughput of the decoder.

Abstract: A system and method for self-test of an integrated circuit are disclosed. As one example, an integrated circuit is disclosed. The integrated circuit includes a digital signal processing chain, a random sequence generator coupled to an input of the digital signal processing chain, and a checksum calculator coupled to an output of the digital signal processing chain.

Abstract: A signal processing system according to various aspects of the present invention includes an excursion signal generator, a scaling system and a filter system. The excursion signal generator identifies a peak portion of a signal that exceeds a threshold and generates a corresponding excursion signal. The scaling system applies a real scale factor to contiguous sets of excursion samples in order to optimize peak-reduction performance. The filter system filters the excursion signal to remove unwanted frequency components from the excursion signal. The filtered excursion signal may then be subtracted from a delayed version of the original signal to reduce the peak. The signal processing system may also control power consumption by adjusting the threshold. The signal processing system may additionally adjust the scale of the excursion signal and/or individual channel signals, such as to meet constraints on channel noise and output spectrum, or to optimize peak reduction.

Abstract: Method and system for measuring transmission quality of an audio transmission system under test. Specifically, an input signal (X), such as an original input speech signal, is applied to the audio transmission system which results in an output signal (Y) produced by the transmission system. Both signals X and Y are mutually processed to yield a perceived quality signal. In accordance with the invention, output signal Y and/or input signal X are scaled such that, depending on a ratio of power of these two signals, relatively small deviations of power between these signals are compensated, while relatively larger deviations are only partially compensated. Further, an artificial reference speech signal may be created for which noise levels present in the input speech signal are reduced by a scale factor which reflects a local level of the noise in that input signal.

Abstract: A device and a method for testing SAS channels which are applied to a plurality of pairs of SAS interfaces. The testing device includes a control terminal, a PCI-E microprocessor, a PCI-E-to-SAS adaptor, and a signal feedback module. The control terminal is used for selecting SAS channels and sending a control command; the PCI-E microprocessor is used for receiving the control command and sending a test signal to a PCI-E channel according to the control command; the PCI-E-to-SAS adaptor is used for converting a transmission signal between the PCI-E channel and the SAS channels; and the signal feedback module is used for connecting a first SAS interface to a second SAS interface in the SAS back plate. The PCI-E microprocessor compares whether the test signal sent to the first SAS channel is consistent with the test signal received from the second SAS interface.

Abstract: The invention relates to a method for testing a communication connection (1) in a communication network in an aircraft with at least a first controller (7), a second controller (8) and a third controller (9).

Abstract: The apparatus for analyzing a delay defect of the present invention obtains the RC of the maximal incidence among region codes (RCs) to which check circuits detecting errors caused with gradual increase in the frequency of an operational clock pulse fed to an integrated circuit belongs. The apparatus obtains information on latch in which an error is caused with the RC of the maximal incidence, with reference to a mapping table that describes the mapping relationship between an RC and a latch. The apparatus extracts a circuit portion in which an error can be captured with the region code of the maximal incidence by exhaustively tracing back circuit portions connected with each obtained latch, from the latch to the latch described in the mapping table. The apparatus gives delay defects to the input and the output pin of each of logic elements included in the extracted circuit portion, generates test patterns for detecting the given delay defects, and performs delay tests.

Abstract: Techniques for performing a continuity check operation include sending a pattern of bits over a packet network connection through a first interface on a packet network to a second interface on the packet network. The first interface is monitored for return of the pattern of bits over the packet network connection. A decision whether the continuity check is successful is based on whether the pattern of bits is detected at the first interface during the monitoring. The techniques can be used for both narrowband as well as broadband calls over the packet network.

Abstract: A device and a method for testing SAS channels which are applied to a plurality of pairs of SAS interfaces. The testing device includes a control terminal, a PCI-E microprocessor, a PCI-E-to-SAS adaptor, and a signal feedback module. The control terminal is used for selecting SAS channels and sending a control command; the PCI-E microprocessor is used for receiving the control command and sending a test signal to a PCI-E channel according to the control command; the PCI-E-to-SAS adaptor is used for converting a transmission signal between the PCI-E channel and the SAS channels; and the signal feedback module is used for connecting a first SAS interface to a second SAS interface in the SAS back plate. The PCI-E microprocessor compares whether the test signal sent to the first SAS channel is consistent with the test signal received from the second SAS interface.

Abstract: A system and method to test voice quality over a call path on a packet based network. A call signaling path is established between a first voice quality tester (VQT) and a second VQT. The call signaling path includes one among multiple call signaling stacks, each operating according to a particular call signaling protocol. By using a graphical user interface (GUI), a user can select the call signaling stack to be used, and change between call signaling stacks in real time.

Abstract: A circuit and method of qualified anomaly detection provides detection and triggering on specific analog anomalies and/or digital data within a qualified area of a serial data stream. A start pattern within the serial data stream, such as a packet header, is detected to generate an enable signal. A stop event, such as a packet trailer, a specified digital event, a time interval or the like, is identified to generate a disable signal. The enable and disable signals are combined to produce a qualification signal that allows a trigger circuit to trigger on a specified anomaly within the portion of the serial data stream defined by the qualification signal.

Abstract: Systems and methods of combining OFDM and CDMA signals are provided. An OFDM packet data channel is overlaid over CDMA transmissions. The channel is scheduled slotwise between multiple users. In some embodiments, there is a CDMA packet data channel which is scheduled together with the OFDM packet data channel.

Abstract: A method is disclosed for identifying a physical failure location on an IC without using layout-versus-schematic (LVS) verification tool. In the method, the integrated circuit is tested with one or more test patterns to identify a failure port thereon. Hierarchical information of the failure port is generated through the test patterns. A physical location of the failure port in a layout of the integrated circuit is identified through a relation between the hierarchical information and a floor plan report. Layout information of a routing path associated with the physical location of the failure port is retrieved from a layout database.

Abstract: A method and apparatus according to the present invention enable wafer chips to be configured with a single power on and off sequence and further enable a chip parameter to be adjusted during a wafer test without utilizing that sequence. In particular, each wafer chip under test is assigned a unique programmable identification. Once each chip has been assigned a corresponding identification, the chips may each be individually accessible by that identification to provide parameter values to chip registers to configure that chip. The configured chips may be subsequently tested in parallel to evaluate the parameter settings. In addition, the present invention enables chips to share data I/O pins or lines, thereby reducing the quantity of testing machine pins utilized for each chip and enabling a greater quantity of chips to be tested in a parallel fashion.

Abstract: A communication device which executes proper communications by correcting communication errors caused by noise generated on a transmission line or the like. An encoding device for adding error correction code to an input data sequence is provided with a first code encoding unit for adding binary error correction code to first data blocks into which the input data sequence is divided, and a second code encoding unit for adding a symbol error correction code for correcting errors by a symbol unit of a predetermined length to second data blocks into which the input data sequence is divided in a form different from that of the plurality of first data blocks.

Abstract: A system and method for efficient transfer and buffering of captured data events. The system includes data capture logic configured to capture data events from a nondeterministic data bus; a system memory including a plurality of addressable locations, where a subset of the plurality of addressable locations is configured as a data event buffer; a DMA transfer engine configured to transfer the captured data events from the data capture logic to a region of the data event buffer as portions of the captured data events become available from the data capture logic; and an application configured to access the data event buffer to process the captured data events without the DMA transfer operation being stopped. In response to the region being filled, the DMA transfer engine may perform the DMA transfer operation to a different region of the data event buffer without the DMA transfer operation being stopped.

Abstract: A method for performing CRC calculations on packets with dynamic headers is disclosed. The header may be changed during transmission across a network. When the header is changed, a CRC associated with the header is recalculated such that a residue of the initial seed value is always obtained. A final CRC covers the entire packet including the header and its header CRC, or just the data portion of the packet. The final CRC remains valid and unchanged during transmission of the packet, allowing an endpoint along the network to confirm the validity of the entire packet. By only changing the CRC associated with the changed portion of the packet (the header CRC), the introduction of errors during transmission of the packet is minimized.

Abstract: Techniques for performing a continuity check operation include sending a pattern of bits over a packet network connection through a first interface on a packet network to a second interface on the packet network. The first interface is monitored for return of the pattern of bits over the packet network connection. A decision whether the continuity check is successful is based on whether the pattern of bits is detected at the first interface during the monitoring. The techniques can be used for both narrowband as well as broadband calls over the packet network.

Abstract: A multi-purpose bit error rate tester (MPBERT) and a method of bit error rate (BER) testing of electrical and optical components and subsystems of electrical and optical communications systems is provided. The invention provides for bit error rate testing both in the optical and the electrical domain, and for bit error rate testing at higher than achievable rates in the electrical domain by multiplexing and demultiplexing in the optical domain. An MPBERT constructed according to the invention incorporates at least one optical multiplexer, and advantageously incorporates at least one optical demultiplexer, and in some embodiments uses high data rate optical RZ to NRZ conversion and high data rate optical NRZ to RZ conversion.

Abstract: An orthogonal frequency division multiplexing (OFDM) transmitter method, consistent with certain embodiments of the present invention arranges OFDM data symbols representing data bits for transmission in a packet. A prescribed pattern of OFDM data symbols are removed (212) and replaced (216) with pilot symbols. The packet is then transmitted (220) to an OFDM receiver that receives the packet (224) and determines a channel correction factor from the pilot pattern. The receiver then estimates a plurality of channel correction factors, one for each of the plurality of OFDM symbols representing data (228) and uses these correction factors to correct the OFDM symbols representing data (232). Arbitrary data are then inserted in place of the pilot symbols (236). The OFDM symbols representing data along with the arbitrary data are then decoded using an error correction decoder that corrects the errors induced by substitution of the pilot symbols for data symbols (240).

Abstract: A memory having a circuit including a built-in address counter with a test mode. The address counter may be used to generate the memory array addressing for the different array test patterns. The circuit may comprise a logic circuit and a counter circuit. The logic circuit may be configured to generate one or more control signals in response to one or more control inputs. The counter circuit may be configured to generate a first counter output and a second counter output in response to (i) the control outputs and (ii) one or more inputs. The counter may comprise a first portion configured to generate the first counter output and a second portion configured to generate the second counter output.

Abstract: A system, method and apparatus are disclosed for generating a test signal by selecting a set of frequencies for the test signal and selecting frequency sub-groups from the set of frequencies. The system generates a respective sub-group composite signal for each frequency sub-group selected from the set of frequencies and time shifts each respective sub-group composite signal in relation to other sub-group composite signals. The system then generates the test signal by summing each respective time shifted sub-group composite signal to produce the test signal. The system of the invention can be used to develop test signals for input into xDSL devices under test, and in particular, is highly beneficial when performing missing tone testing of xDSL devices.

Abstract: An adaptive hybrid automatic repeat request system and method, which comprise (a) transmitting a data frame comprised of a data bit and a parity bit that are channel-coded using a predetermined initial coding rate; (b) receiving the data frame, performing channel decoding of the received data frame, and when an error exists in the channel-decoded data frame, correcting the error; (c) when there is no error in the channel-decoded data frame or the error is corrected, transmitting an ACK message to a transmitting terminal; (d) when the error of the channel-decoded data frame is not corrected, measuring an error degree of a corresponding frame and transmitting a NACK message to which the measured error degree is added, to the transmitting terminal; (e) retransmitting a parity frame that is generated by performing channel coding of a parity bit corresponding to a parity level determined in accordance with the error degree added to the NACK message; and (f) combining the retransmitted parity bit with a data bit of

Abstract: A communication hub for providing continuity testing in communication networks. The communication hub comprises a processor coupled to an interface. The processor is configured to process a continuity test instruction to generate a request for continuity acknowledgment message. The interface is configured to receive the continuity test instruction and transmit the request for continuity acknowledgment message.

Abstract: For use in a multiprocessor system in which a plurality of processors share a main memory via a processor bus, an error processing unit (EU) that determines an error level is provided in each processor. When an L2 cache control unit (SU) that controls an L2 cache in the write-back mode, a bus interface unit (PU), and so on, are normal and snoop processing may be continued, the snoop processing is continued in the processor, in which an error occurred, regardless of whether or not the processor is reset. This prevents the system from going down even when data coherence among L2 caches is lost due to an error that occurs in one of processors.

Abstract: An arrangement to analyze the nonlinear properties of a communication channel that uses a test signal having a number of tones. The test signal is transmitted via the communication channel to be evaluated. For the individual tones of the test signal, equidistant tone frequencies are selected, some of these tone frequencies not being used for the test signal. By the use of frequency shifters in the form of digital modulators, which shift the frequency spectrum of the transmitted test signal to zero by in each case one tone frequency value that is not used, nonlinear interference can be determined with the aid of a low-pass filter.

Abstract: A pattern generator that generates a test pattern used for testing an electric part including: a pattern memory that stores test pattern information, which defines the test pattern; a vector memory that stores a vector instruction, which indicates an order for reading out the test pattern information from the pattern memory; an address expansion unit that generates an address of the test pattern information in the pattern memory according to the vector instruction stored in the vector memory; an interruption pattern memory that stores interruption test pattern information, which defines the test pattern during a predetermined interruption process; an interruption vector memory, which is different from the vector memory, that stores an interruption vector instruction which indicates an order for reading out the interruption test pattern information from the interruption pattern memory; an interruption address expansion unit that generates an address of the interruption test pattern information according to th

Abstract: A method and corresponding apparatus for encoding a sequence of bits for transmission as symbols, some of the bit positions of the symbols having a higher bit error rate than other bit positions. The method includes: a step (31, 32, 41, 42) of providing a plurality of sequences of bits using a convolutional encoder (31, 41), in response to a sequence of input bits, each sequence of bits being defined by a predetermined generator polynomial having a predetermined level of sensitivity to puncturing; and a step (33, 44) of mapping the bits of each sequence of bits to symbol positions based on the level of sensitivity of the generator polynomial defining the sequence of bits. With interleaving, the mapping of bits of each sequence of bits to symbol positions (33, 44) can precede a symbol interleaving step (34), or it can follow a bit interleaving step (43).

Abstract: A network link tester couples to a LAN port with the LAN port having both a network transmit pair and a node transmit pair line. The link detector scans the network transmit pair and node transmit pair lines for the presence of link signals. Upon finding a link signal, the link tester indicates if the link signals were on the network transmit pair or on the node transmit pair line. Further, the link tester determines the network standard used and identifies the available operational nodes. The process of using a LAN tester includes coupling the tester to the LAN port, scanning network lines for the presence of link signals and determining and displaying operational capabilities. Optionally, the link tester may generate a tone signal on the network lines to assist in identifying line faults. Further, the link tester may generate link signals responsive to receive link signals.