Abstract: A method for failure detection and role selection for a process in a network of redundant processes including a primary process configured to transmit a heartbeat signal with a predetermined interval to the processes of the network.

Abstract: The current document is directed to methods and systems that efficiently process log/event messages within and among distributed computer facilities. Various different types of initial processing steps may be applied to a stream of log/event messages received by a message-collector system or a message-ingestion-and-processing system. By including a pre-processing step two identify the type of a received log/event message, and by specifying initial-processing-step criteria with respect to log/event-message types, significant increases in the efficiency of log/event-message preprocessing by message-collector systems and message-ingestion-and-processing systems is achieved.

Abstract: A method of determining the presence of a loopback in one or more networks comprises storing information related to a test instance; sending a loopback detection beacon (LPDB) containing information related to the test instance from a port on an originating device; monitoring the port for a predetermined time period to detect LPDBs arriving at the port during the predetermined time period; and determining whether a detected LPDB contains information corresponding to the stored information, to detect the presence of a loopback. The method may determine whether a detected loopback is a port loopback, a tunnel loopback or a service loopback. The stored information related to the test instance may be deleted if an LPDB arriving at the port and containing information corresponding to the stored information is not detected within the predetermined time period.

Abstract: Methods and apparatuses are disclosed that can combine audio content from two encoded input signals into a new encoded output signal without requiring a decode or re-encode of audio content in either encoded input signal. Encoded data representing audio content and spatial location of audio objects in two different input encoded signals are combined to generate an encoded output signal that has encoded data representing audio objects from both of the input encoded signals.

Abstract: A system and method for intelligent management of an array of fans. The system uses mean-time-between-failure, fan usage and other data in add ventilation, subtract ventilation and recycle array routines to maximize the life of the fans and the array. The system comprises a primary embodiment making use of smart fans in the array, each smart fan including a fan and appropriate control electronics capable of processing commands received from a smart fan array controller. Fan control signals are multiplexed over a local operating network power line using carrier communication protocols, command messages and data values, all to accomplish a goal of the system to maximize fan life. In an alternate embodiment, fan and array control electronics are integrated onto the fan array controller itself and power is provided to conventional fans using a conventional wiring harness.

Abstract: A first communication apparatus to be coupled to a second communication apparatus and a third communication apparatus via a ring network, including: a first port to coupled to the ring network; and a second port to coupled to the ring network; wherein the first port and the second port is set to receive a control frame from the second communication apparatus and the third communication apparatus, and either the first port or the second port is set to be disabled to relay a user frame.

Abstract: Aspects of the disclosure pertain to a system and method for providing fast and efficient flushing of a forwarding database in a network processor. The present disclosure provides a deterministic mechanism to implement a flush operation for flushing the forwarding database. A dual FDB approach, a means for switching from one FDB to another in the event of a failure, and FDB flush operation as a background task are key features of this disclosure. The effective time for completing the flush operation is within a sub-50 millisecond time frame and is independent of the number of entries in the forwarding database. The flush operation may be performed using software.

Abstract: Techniques and mechanisms for evaluating I/O buffer circuits. In an embodiment, test rounds are performed for a device including the I/O buffer circuits, each of the test rounds comprising a respective loop-back test for each of the I/O buffer circuits. Each of the test rounds corresponds to a different respective delay between a transmit clock signal and a receive clock signal. In another embodiment, a first test round indicates a failure condition for at least one I/O buffer circuit and a second test round indicates the failure condition for each of the I/O buffer circuits. Evaluation of the I/O buffer circuits determines whether the device satisfies a test condition, where the determining is based on a difference between the delay corresponding to the first test round and the delay corresponding to the second test round.

Abstract: A method for verifying compliance of a communication device with one or more requirement specifications is disclosed.

Abstract: A method of testing an interconnect between an electronic component and an external memory comprises receiving a data word having data bits and translating the data word into multiple cycles. The multiple cycles are transmitted through the interconnect to the external memory one after another such that a value of the data bit being transmitted is switched for each cycle. In another embodiment, an electronic component comprises an interface, a translation unit, and a test module. The translation module is configured to receive a burst from the external memory through the interface and is configured to translate the burst into a data word. The test module is configured to receive the data word from the translation module and is configured to compare the data word to a test pattern to detect an interconnect defect.

Abstract: A video coding system and method for increasing a transmitted output bit rate of a video encoding system by altering the content of the bit stream. A video encoder may receive a coding mode signal from a computer application for coding source video data, the coding mode signal indicating a target bit rate having a risk factor related to transmission error associated to the target bit rate. The coded bitstream may be modified based on the risk factor indicated in the coding mode signal. A modified coded bitstream may be outputted at the target bit rate and at a reduced coding efficiency, and the channel may be tested for transmission errors. Based on the test results, a revised coding mode signal indicating the same target bit rate, but a revised risk factor may be provided. The coded bitstream may be revised by removing the modifications previously made to the coded bitstream and a revised coded bitstream having greater coding efficiency may be output at the target bit rate.

Abstract: A system and method are disclosed for a resilient IP ring protocol. A system that incorporates teachings of the present disclosure may include, for example, a communication device using a resilient internet protocol (IP) ring protocol, including a controller (602) that manages operations of a transceiver (620) for exchanging messages in a communication system with adjacent ring nodes in a communication ring architecture (300). The controller can be programmed to use sub-second level signaling between adjacent ring nodes to determine when adjacent ring nodes have failed and enable failure options upon detection of an adjacent ring-node failure. Additional embodiments are disclosed.

Abstract: Methods and test receiver apparatus are provided for loopback testing of a unidirectional physical layer device. The disclosed methods and test receiver apparatus allow for the phase of a sampling clock implemented at the test receiver apparatus to be aligned with the phase of a test data signal.

Abstract: A built-in self test circuit includes a pattern generator, an elastic buffer, a symbol detector, and a comparison unit. A pattern generator generates a first test pattern to test a port under test and then a result pattern is gotten and stored in the elastic buffer. The symbol detector detects if a starting symbol exists in the test result pattern. If it exists, a second test pattern is generated to be compared with the test result pattern. As a result, a reliability of data transmission of the port under test is determined.

Abstract: A semiconductor device including an electronic circuit, a memory, and an error detecting module. The electronic circuit is configured to receive an input signal having been generated by a test module, and generate an output signal based on the input signal. The memory is configured to store a predetermined output value that is expected to be output from the electronic circuit based on the electronic receiving the input signal, wherein the predetermined output value is stored in the memory prior to the input signal being generated by the test module. The error detecting module is configured to (i) generate a sample value of the output signal, (ii) compare the sample value of the output signal to the predetermined output value stored in the memory, and (iii) generate a result signal that indicates whether the sample value of the output signal matches the predetermined output value.

Abstract: Disclosed is a semiconductor chip with a digital integrated circuit, such as a memory device (e.g., static random access memory (SRAM) arrays, dynamic random access memory (DRAM) arrays, content addressable memory (CAM) arrays, etc), that can be selectively operated in either a functional mode or in a performance screening mode. In the functional mode, a first signal supplied by an external signal generator is used to activate a first device in the circuit and, in response, a second device in the circuit outputs a data output signal. In the performance screening mode, a second signal is internally generated by an internal signal generator based on the data output signal. This second signal is then used to activate the first device in the circuit and, in response, the second device outputs the data output signal.

Abstract: A memory loopback system and method including an address/command transmit source configured to transmit a command and associated address through an address/command path. A transmit data source is configured to transmit write data associated with the command through a write path. Test control logic is configured to generate gaps between successive commands. A loopback connection is configured to route the write data from the write path to a read path. A data comparator is configured to compare the data received via the read path to a receive data source and generate a data loopback status output. Pattern generation logic can be configured to generate a loopback strobe, the loopback strobe being coupled to the read path. The pattern generation logic may be configured to synthesize a read strobe based on the test control logic and to use the synthesized read strobe as the loopback strobe.

Abstract: Communication modules are coupled in a communication ring and are operable to send and receive data from peripheral devices. The modules are operable to send and receive data streams on paths of the ring, and each module is operable, responsive to receiving a predetermined initialization signal, to operate as a master for initially blocking data in the first path and initially sending a block signal to a neighboring module downstream in the second path. The modules are operable, responsive to receiving the block signal in one of the paths, to block data in that one of the paths, so that responsive to initialization of one of the modules as a master, the master and the neighboring module create an inactive virtual link therebetween in order to prevent data from propagating around the ring more than once.

Abstract: A provider edge (PE) node of a network operates to send a trace path message over the network to a receiver PE node, the trace path message recording a list of intermediate nodes of a unicast path from the PE node to the receiver PE node; and receive a join message initiated from the receiver PE node, the join message using the list to propagate to the source PE node through the intermediate nodes such that a branch of a multicast tree is aligned with the unicast path. It is submitted with the understanding that it will not be used to interpret or limit the scope or meaning of the claims. 37 CFR 1.72(b).

Abstract: A built-in self test circuit includes a pattern generator, an elastic buffer, a symbol detector, and a comparison unit. A pattern generator generates a first test pattern to test a port under test and then a result pattern is gotten and stored in the elastic buffer. The symbol detector detects if a starting symbol exists in the test result pattern. If it exists, a second test pattern is generated to be compared with the test result pattern. As a result, a reliability of data transmission of the port under test is determined.

Abstract: Provided is a CAN system that can generate an error signal without requiring hardware for generating an error signal to be connected to a bus. A protocol processing part within a CAN controller incorporates error data into receive data or send data, based on error data information stored in a register.

Abstract: Provided is a CAN system that can generate an error signal without requiring hardware for generating an error signal to be connected to a bus. A protocol processing part within a CAN controller incorporates error data into receive data or send data, based on error data information stored in a register.

Abstract: A smart scheduler is provided to prepare a machine for a job, wherein the job has specific requirements, i.e., dimensions. One or more config jobs are identified to configure the machine to meet the dimensions of the job. Information concerning the machine's original configuration and groupings of config jobs that change the machine's configuration are cached in a central storage. The smart scheduler uses information in the central storage to identify a suitable machine and one or more config jobs to configure the machine to meet the dimensions of a job. The smart scheduler schedules a run for the config jobs on the machine.

Abstract: A chip operating method is provided which includes enabling a transmission mechanism or a receiving mechanism of the chip while normally operating the chip. The method further includes enabling both of the transmission mechanism and the receiving mechanism of the chip while testing the chip.

Abstract: The present invention implements a method and apparatus for using components within a Serializer/DeSerializer (SerDes) to emulate the effects of a backplane in order to facilitate automated test equipment (ATE) testing of the SerDes. The SerDes includes a transmitter pre-emphasis circuit (TPXE) that pre-emphasizes a transmitted signal and a receiver equalization circuit (RXEQ) that equalizes a received signal. The TPXE includes coefficients that are dynamically programmable.

Abstract: A system and method for verifying system-on-chip interconnect includes a first linear feedback shift register coupled to an output interface of a first system-on-chip component, a second linear feedback shift register instantiated in a second system-on-chip component, and a comparator coupled to the second linear feedback shift register and the input interface of the second system-on-chip. Another method for verifying includes generating a pseudo-random number sequence with the first linear feedback shift register and the second linear feedback shift register using an identical first initial state, and comparing an output of the first linear feedback shift register with an output of the second linear feedback shift register and reporting a miss-compare.

Abstract: A system for testing hardware components includes a test pattern injector and a test pattern detector coupled to verification paths that pass through hardware components. The test pattern injector generates unique test patterns. A test pattern tests hardware features of the hardware components of a corresponding verification path. The test pattern injector injects the test patterns into the corresponding verification paths. The test pattern detector establishes expected test patterns. An expected test pattern matches an injected test pattern of a corresponding verification path. The test pattern detector determines whether received test patterns match the expected test patterns.

Abstract: Embodiments of the present invention provide a protocol tester for performing a protocol test, said protocol tester exhibiting an input for the feeding in of data, a protocol decoding device for the decoding of data, and an output for providing the decoded data, the protocol tester also comprising a device for measuring the bit error rate. A corresponding method for performing a protocol test is also provided.

Abstract: A concrete vehicle is described herein which includes a chassis, a concrete handling system, a vehicle subsystem control system, and a wireless communication system configured to communicate with an off-board electronic device. The subsystem control system includes status information for a plurality of vehicle parameters. The wireless communication system is used to communicate status information pertaining to at least one vehicle parameter to the off-board electronic device when the vehicle parameter breaches a threshold.

Abstract: In a preferred embodiment, the invention provides a circuit for reducing bit error rates. A data recovery circuit recovers data from a first HSS link to differential bit pair inputs. Data from the differential bit pair outputs of the data recovery circuit drive differential bit pair inputs to a plurality of FIFOs. The data is then driven from a parallel output of the plurality of FIFOs to the parallel input of a synchronizer. The data is then driven from the parallel output of the synchronizer to the parallel input of a serializer. The serializer, through different bit pair outputs, drives a second serial HSS link.

Abstract: A system and method for self-test of an integrated circuit are disclosed. As one example, an integrated circuit is disclosed. The integrated circuit includes a digital signal processing chain, a random sequence generator coupled to an input of the digital signal processing chain, and a checksum calculator coupled to an output of the digital signal processing chain.

Abstract: Memory apparatus and methods utilizing multiple bit lanes may redirect one or more signals on the bit lanes. A memory agent may include a redrive circuit having a plurality of bit lanes, a memory device or interface, and a fail-over circuit coupled between the plurality of bit lanes and the memory device or interface.

Abstract: A semiconductor integrated circuit includes: an input/output cell that is included in a path captured during propagation delay testing and that has an output-stage buffer on an output bus; and a terminal connected to the output bus and an input bus of the input/output cell. An external load or a testing device is connectable to the terminal. The input/output cell has a switching part that is capable of switching between a first path that loops back at an output side of the output-stage buffer and a second path that loops back at an input side of the output-stage buffer. The first path is selected during normal operation and the second path is selected during the propagation delay testing.

Abstract: A semiconductor device that includes a module under test that is integrated with the semiconductor device, that receives an input signal from a test module, and that provides an output signal to at least one output terminal based on the input signal. An error detecting module is integrated with the semiconductor device, samples values of the output signal, and outputs the sampled values to the test module.

Abstract: A self-synchronizing data bus analyzer is provided which can include a generator linear feedback shift register (LFSR) to generate a first data set, and can include a receiver LFSR to generate a second data set. The data bus analyzer may also include a bit sampler to sample the first data set received through a data bus coupled to the generator LFSR and output a sampled first data set. A comparator can be included to compare the sampled first data set with the second data set generated by the receiver LFSR and provide a signal to the receiver LFSR to adjust a phase of the receiver LFSR until the second data set is substantially the same as the first data set.

Abstract: Disclosed is a system and method for testing a dual mode interface. The dual mode interface includes a first strobe circuit and a second strobe circuit configured to be inoperable during a first operational mode of the interface and operable during a second operational mode of the interface. The dual mode interface also includes a first data circuit and a second data circuit configured to be operable during the first operational mode and the second operational mode. The dual mode interface also includes a signal line connecting an output of the second strobe circuit with an input of the first strobe circuit and a switch element configured to activate said signal line in response to receipt of a test signal.

Abstract: In a communication system based on OSI (Open Systems Interconnection) Reference Model, a pattern body generation circuit of a transmitting device generates and outputs a jitter test pattern body for jitter test. A selector selects an output (frame data) of a transmitting-end upper circuit during normal communication and selects an output (pattern body) of the pattern body generation circuit during jitter test. A transmitting-end MAC circuit performs transmitting-end processing of a MAC layer on the data selected by the selector to thereby obtain a MAC frame. A receiving-end MAC circuit performs receiving-end processing of a MAC layer on a received frame in MAC frame format to thereby obtain a payload. A pattern body verification circuit verifies a pattern body that is a payload obtained by the receiving-end MAC circuit during jitter test against a corresponding pattern body before transmission.

Abstract: An interface test can be performed by, for example, only a self apparatus when interface operation specifications are different between the self apparatus and an original connection partner apparatus. An LSI has a plurality of interfaces (IFs) for transmission/reception of data with an external device, and the LSI includes an emulation control unit for allowing one of the two of the plurality of IFs to perform an operation of emulating an IF of a connection partner device having operation specifications different from those of the LSI, when two IFs are connected to each other via a transmission line.

Abstract: Embodiments of an apparatus and method for high-speed testing of a device under test are described herein, where the device under test is coupled to a tester via a limited passband communication channel. A plurality of test vector patterns is generated having characteristics such that when a given test vector pattern is transmitted electrically at a transmission rate via the communication channel, the test vector pattern has a frequency content that is less than the frequency content of a high frequency test vector pattern if the high frequency test vector pattern were to be transmitted electrically at the transmission rate via the communication channel, and such that the frequency content of each test vector pattern when transmitted electrically at the transmission rate via the communication channel falls within the passband associated with the communication channel.

Abstract: The present invention implements a method and apparatus for using components within a Serializer/DeSerializer (SerDes) to emulate the effects of a backplane in order to facilitate automated test equipment (ATE) testing of the SerDes. The SerDes includes a transmitter pre-emphasis circuit (TPXE) that pre-emphasizes a transmitted signal and a receiver equalization circuit (RXEQ) that equalizes a received signal. The TPXE includes coefficients that are dynamically programmable.

Abstract: A testing method includes selecting a low-pass filter by simulation, generating testing signals with the low-pass filter receiving output signals of an under-test circuit, and outputting the testing signals to an input of the under-test circuit for predetermined measurements. A testing circuit and testing method achieve the same jitter injection as conventional high-speed testing instruments, but save testing cost.

Abstract: A data transmission apparatus comprises an estimation device to estimate a transmission condition of the transmission channel in the transmitter based on at least Jitter information or a packet loss rate obtained from the receiver, and a controller to change at least one of a bit rate of transmission data and a error resilience level according to the estimated transmission condition.

Abstract: A data transmission apparatus comprises an estimation device to estimate a transmission condition of the transmission channel in the transmitter based on at least Jitter information or a packet loss rate obtained from the receiver, and a controller to change at least one of a bit rate of transmission data and a error resilience level according to the estimated transmission condition.

Abstract: A data transmission apparatus comprises an estimation device to estimate a transmission condition of the transmission channel in the transmitter based on at least Jitter information or a packet loss rate obtained from the receiver, and a controller to change at least one of a bit rate of transmission data and a error resilience level according to the estimated transmission condition.

Abstract: A test system for testing a backplane comprising an adapter assembly and a generic boundary-scan test unit. The adapter assembly includes an application-specific mating connector to communicatively couple the adapter assembly to an application-specific port of a backplane and an adapter generic connector. The generic boundary-scan test unit includes a test card generic connector to communicatively couple the generic boundary-scan test unit to the adapter generic connector of the adapter assembly and boundary-scan functionality to transmit at least one output test signal. The backplane is tested by communicating the output test signal from the generic boundary-scan test unit to the application-specific mating connector for testing the backplane and communicating at least one input test signal received from the backplane via the application-specific mating connector to the boundary-scan functionality of the generic boundary-scan test unit.

Abstract: A memory system includes at least one memory module, each of which has a pattern data generating circuit for generating a pattern data, which has a plurality of memories to which a command signal is commonly applied and corresponding data is applied respectively; and a memory controller for respectively applying the command signal and the corresponding data to the plurality of memories, applying a pattern data generating command to the memory module during a timing control operation, calculating time differences among data of reaching each of the plurality of memories using the pattern data outputted from each of the memories and receiving and outputting data using the calculated data reaching time difference. Therefore, a stable data transmission is achieved between the memory controller and the memories.

Abstract: A serial point to point link that communicatively couples an integrated circuit (IC) device to another IC device is initialized by transferring a training sequence of symbols over the link. Registers of the IC device are programmed, to set a symbol data pattern and configure a lane transmitter for the link. A start bit in a register of the IC device is programmed, to request that the link be placed in a measurement mode. In this mode, the IC device instructs the other IC device to enter a loopback mode for the link. The IC device transmits a sequence of test symbols over the link and evaluates a loopback version of the sequence for errors. The sequence of test symbols have a data pattern, and are transmitted, as configured by the registers. Other embodiments are also described and claimed.

Abstract: A data transmission apparatus comprises an estimation device to estimate a transmission condition of the transmission channel in the transmitter based on at least Jitter information or a packet loss rate obtained from the receiver, and a controller to change at least one of a bit rate of transmission data and a error resilience level according to the estimated transmission condition.

Abstract: A self-synchronising data bus analyser comprising a generator LFSR, a receiver LFSR and a comparator wherein the generator LFSR generates a first data set which is transmitted through a data bus to the comparator; and wherein the comparator compares the first data set with a second data set generated by the receiver LFSR and adjusts the receiver LFSR until the second data set is substantially the same as the first data set.

Abstract: Multiple channels of a multi-channel analyzer are allocated among multiple users such that each user can initiate and retrieve the results of separate diagnostic sessions or strategies. Each analyzer channel includes an input connection port, a trace buffer memory and logic circuitry. The input connection port is operably connected to a unique node in the communication network. A host processor assigns ownership of a unique set of analyzer channels to at least two users such that each user can initiate separate simultaneously established traces on the communication network. The logic circuitry monitors frame data on the connection port at each node in accordance with a set of instructions established by the user assigned to the analyzer channel for that node, and the traces are captured in response to the set of instructions such that each user retrieves only results of the analyzer channels assigned to that user.