By Time Limit, I.e., Time-out (epo) Patents (Class 714/E11.003)
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Patent number: 11948147Abstract: Techniques are provided for fallback authorization routing. A merchant processor may receive authorization requests from one or more merchant systems. These authorization requests may be to authorize a transaction. The merchant processor may transmit these authorization requests over a first communication channel to an acquirer processor, which may then forward the requests to a payment network. If the merchant processor determines that the acquirer processor is not receiving the authorization requests, or is otherwise unavailable, the merchant processor may, as a fallback, transmit the authorization requests directly to the payment network through a second communication channel, thereby bypassing the acquirer processor. When the merchant processor receives some indication that the acquirer processor is available to process authorization requests, new authorization requests can be transmitted to the acquirer processor via the first communication channel.Type: GrantFiled: January 20, 2022Date of Patent: April 2, 2024Assignee: VISA INTERNATIONAL SERVICE ASSOCIATIONInventors: Robert Dean McLaughlin, Balakrishnan Kannikeswaran, Biju Abraham, Roshin Joseph
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Patent number: 11809265Abstract: Methods, apparatus, systems, and articles of manufacture to manage resources when performing an account health check are disclosed. An example apparatus includes memory; computer readable instructions; and processor circuitry to execute the computer readable instructions to: perform health checks on a cloud account at a first polling frequency; after a failure count at the first polling frequency meets a first threshold, perform the health checks on the cloud account at a second polling frequency lower than the first polling frequency; and after the failure count at the second polling frequency meets a second threshold, suspend the cloud account.Type: GrantFiled: July 21, 2022Date of Patent: November 7, 2023Assignee: VMware, Inc.Inventors: George P. Dimitrov, Ivan Nushev, Dimitar Chobanov
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Patent number: 11755342Abstract: A circuit includes a guard trigger circuit that includes a first input node adapted to be coupled to a first state signal, a second input node adapted to be coupled to a second state signal and an output node. The circuit also includes a reset synchronizer circuit that includes an input node coupled to the output node of the guard trigger circuit, a clock node adapted to be coupled to a clock signal and an output node. The circuit further includes a timeout circuit including an input node coupled to the output node of the reset synchronizer circuit, a clock node adapted to be coupled to the clock signal and an output node. The circuit still further includes a reset requestor circuit that includes a first input node coupled to the output node of the guard trigger circuit, a second node coupled to the output node of the timeout circuit.Type: GrantFiled: December 16, 2020Date of Patent: September 12, 2023Assignee: TEXAS INSTRUMENTS INCORPORATEDInventors: Ronald Nerlich, Mark Jung, Johann Zipperer, Dietmar Walther
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Patent number: 11748200Abstract: A method of performing safety-critical rendering at a graphics processing unit within a graphics processing system, the method comprising: receiving, at the graphics processing system, graphical data for safety-critical rendering at the graphics processing unit; scheduling at a safety controller, in accordance with a reset frequency, a plurality of resets of the graphics processing unit; rendering the graphical data at the graphics processing unit; and the safety controller causing the plurality of resets of the graphics processing unit to be performed commensurate with the reset frequency.Type: GrantFiled: June 4, 2022Date of Patent: September 5, 2023Assignee: Imagination Technologies LimitedInventors: Philip Morris, Mario Sopena Novales, Jamie Broome
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Patent number: 11650647Abstract: An SCP power unavailability data storage system includes a chassis housing a power system, a central processing system, and an SCP subsystem that are coupled together. The SCP subsystem includes a volatile SCP memory system storing data provided by the central processing system, an SCP processing system coupled to the volatile SCP memory system, and an SCP communication system that, when power is unavailable from the power system, utilizes power received via its data/power port(s) and provides that power to the volatile SCP memory system and the SCP processing system. An SCP data storage engine provided by the SCP processing system will, in response to an unavailability of power from the power system, operate using power received via the data/power port(s), retrieve data stored in the volatile SCP memory system, and transmit the data via port(s) on the SCP communication system and through a network for storage on storage device(s).Type: GrantFiled: October 4, 2021Date of Patent: May 16, 2023Assignee: Dell Products L.P.Inventors: Andrew Butcher, Shawn Joel Dube
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Patent number: 11614958Abstract: A secondary pool of VMs is used to run secondary services or jobs, which may be evicted upon failure of a corresponding primary VM. Upon detection of a failure of a primary resource, the secondary services or jobs are evicted from secondary pool resources, and the secondary pool resources can be automatically allocated to the jobs of the failed primary resource. In this regard, a secondary job may be thought of as a preemptible job and comprises services or jobs that are lower priority than the service or job on the primary resource. By using computing resources in the secondary pool to run secondary or preemptible jobs, this technology makes use of what would be otherwise idle resources. This beneficially avoids having to allocate additional and separate computing resources for secondary jobs, leads to more efficient use of network resources, and reduces costs.Type: GrantFiled: February 11, 2021Date of Patent: March 28, 2023Assignee: Google LLCInventors: Dean Hildebrand, Grigor Avagyan
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Patent number: 11588475Abstract: A semiconductor integrated circuit includes a clock controller generating a clock; and a plurality of blocks that operate by using the clock. The clock controller performs statistical processing for the plurality of blocks, controls a frequency of the clock to a first frequency, changes the frequency of the clock from the first frequency to a second frequency, generates the clock of the second frequency after a time predicted by the statistical processing as a time for which the second frequency is to be continued elapses from a timing when the frequency of the clock is changed, and supplies the generated clock to the blocks. The clock controller generates a third frequency clock obtained by decimating down the second frequency from the first frequency according to a time for which the first and second frequencies are to be continued after the frequency of the clock is changed from the second frequency to the first frequency, and supplies the generated clock to the blocks.Type: GrantFiled: October 13, 2021Date of Patent: February 21, 2023Assignees: KABUSHIKI KAISHA TOSHIBA, TOSHIBA ELECTRONIC DEVICES & STORAGE CORPORATIONInventors: Haruya Iwata, Tatsuya Tokue, Sohei Kushida, Takayuki Mori, Satoshi Kamiya
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Patent number: 11579957Abstract: A system includes a plurality of watchdog components. Each watchdog component is configured to receive a kick signal from its monitored function to determine whether the monitored function is active. Each watchdog component is further configured to receive a respective token from all watchdog components that the each watchdog component is connected to. The respective token determines whether its respective watchdog component has timed out. Each watchdog component is further configured to generate a token responsive to the kick signal and further responsive to the respective token from all watchdog component that the each watchdog component is connected to. Each watchdog component is further configured to transmit the generated token to the all watchdog components that the each watchdog component is connected to.Type: GrantFiled: July 24, 2020Date of Patent: February 14, 2023Assignee: XILINX, INC.Inventors: Edward S. Peterson, Trevor W. Hardcastle, Carl H. Carmichael
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Patent number: 11579995Abstract: An electronic element includes: a module for storing reference data; a module for receiving data from a processor; a module for verifying the received data by comparison by way of reference data; and a module for transmitting an instruction to cut off supply of the processor, the supply cutoff instruction being transmitted after occurrence of a failure event, the failure event being an absence of reception of data or a failure in verifying the data. A system including such an electronic element and a method for monitoring a processor by the electronic element are also described.Type: GrantFiled: February 11, 2020Date of Patent: February 14, 2023Assignee: IDEMIA FRANCEInventors: Sylvestre Denis, Emmanuelle Dottax
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Patent number: 11575652Abstract: A communication system and a communication method for one-way transmission are provided. The communication method includes: transmitting a filtering rule to a programmable logic device by a server; receiving a signal and obtaining data from the signal by the server; packing the data to generate at least one data packet by the server; transmitting the at least one data packet to the programmable logic device by the server; and determining, according to the filtering rule, whether to output the at least one data packet by the programmable logic device.Type: GrantFiled: March 5, 2021Date of Patent: February 7, 2023Assignee: BlackBear (Taiwan) Industrial Networking Security Ltd.Inventors: Yuan Chen Chan, Po-Chih Hsu
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Patent number: 11520654Abstract: A method of performing a system watchdog operation of a data processing system using a system watchdog timer includes creating an initial question, starting a timer of the system watchdog timer, receiving an initial answer and an initial data code, calculating an expected data code in response to the initial question, and comparing the initial data code to the expected data code. In response to a mismatch between the initial data code and the expected data code, a bus error signal is generated. In response to a match, the initial answer is compared to the initial question, and in response to a match between the initial answer and the initial question, the timer is reset and the initial data code is stored as a subsequent question, but in response to a mismatch, a remedial action of the data processing system is performed.Type: GrantFiled: February 3, 2021Date of Patent: December 6, 2022Assignee: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLCInventors: Philippe Debosque, Cornelis Hermanus Voorwinden, Philippe Quarmeau
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Patent number: 11461862Abstract: Systems and methods for patent portfolio management and generation of analytics are described. A system comprises, for example, one or more modules. A first module is configured to combine data received from an official government source and from a docketing system. The data received may pertain to one or more assets of a patent portfolio. A second module is configured to generate a metric of the patent portfolio based on the combined data. The metric may measure a characteristic of the patent portfolio. A third module is configured to receive a request from a client device to display the metric. A fourth module is configured to, in response to the request to display the metric, display the metric in a user interface that includes one or more filtering elements that are selectable to request a filtering of the displayed metric.Type: GrantFiled: May 19, 2014Date of Patent: October 4, 2022Assignee: Black Hills IP Holdings, LLCInventor: Steven W. Lundberg
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Patent number: 11433784Abstract: A seat adjustment system for a seat of a motor vehicle, including at least one motor driving the adjustment and at least one operating element, which can be actuated by an operator, for at least one adjustment function, and the actuation of which closes a switch provided in a line from the motor associated with the adjustment function to a power supply, wherein a relay is provided downstream of the switch to the motor in the line, said relay being open in the non-energized state, and the seat adjustment system has a control unit which is designed to close the relay when an operating element is actuated and there is no collision signal indicating a collision of the motor vehicle and leaves the relay open at least temporarily if there is a collision signal when an operating element is actuated.Type: GrantFiled: June 14, 2018Date of Patent: September 6, 2022Assignee: AUDI AGInventor: Frank Pfeffer
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Patent number: 11347607Abstract: A clustered pair of data storage nodes employs a time-to-live (TTL) mechanism by which a preferred node communicates permission for continued operation to a non-preferred node. During non-errored TTL operation, host I/O requests to a data storage object are serviced, with write-type requests being replicated to the other node. Upon a failure as indicated by errored TTL operation or failure of replication, a polarization operation selects a surviving node to transition to single-node access to the data storage object. The polarization process includes: (1) each node contacting a witness node to request survivor status, (2) the witness node granting survivor status to the first node requesting it and denying survivor status to a later-requesting node, (3) at the node granted survivor status, continuing to service the host I/O requests without replication, and (4) at the other node based on being denied survivor status, discontinuing servicing of the host I/O requests.Type: GrantFiled: April 16, 2021Date of Patent: May 31, 2022Assignee: EMC IP Holding Company LLCInventors: Dmitry Nikolayevich Tylik, David Meiri
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Patent number: 11086869Abstract: Systems and methods are disclosed for interfacing with one or more components of a data intake and query system. The data intake and query system includes a gateway that interfaces between one or more computer-executable applications and one or more components of the data intake and query system. The data intake and query system can include an intake system configured to ingest data, an indexing system configured to generate and store one or more events based on the data, and a query system configured to execute one or more queries. The intake system can include a streaming data processor and at least one ingestion buffer. The indexing system can include at least one containerized indexing node, and the query system can include at least one containerized search node.Type: GrantFiled: October 31, 2018Date of Patent: August 10, 2021Assignee: Splunk Inc.Inventors: Bharath Kishore Reddy Aleti, Alexandros Batsakis, Joseph Gabriel Echeverria, Alexander Douglas James, Sourav Pal, Christopher Madden Pride, Sai Krishna Sajja, Eric Sammer
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Patent number: 10726009Abstract: Systems and methods are disclosed for processing queries against one or more dataset sources. The system tracks query resource data and resource utilization data. The query-resource usage data can indicate resources used to execute queries. The node resource utilization data can indicate current utilization of nodes in the system. Upon receipt of a query that identifies a set of data to be processed and a manner of processing the set of data, the system can use the query-resource usage data and the resource utilization data to define a query processing scheme. The query can then be executed using the query processing scheme. In some cases, the query coordinator can dynamically allocate partitions operating on worker nodes to execute the query.Type: GrantFiled: July 31, 2017Date of Patent: July 28, 2020Assignee: Splunk Inc.Inventors: Sourav Pal, Arindam Bhattacharjee, Christopher Pride
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Patent number: 10169068Abstract: Live migration may be performed for virtual computing resources utilizing network-based storage. A virtual compute instance operating at a source host may be moved to a destination host. The virtual compute instance may be a client of a network-based storage resource that stores data for the virtual compute instance. Access to the data stored for the virtual compute instance may be limited to the source host. When migration is performed, the destination host may be prepared to assume operation of the virtual compute instance. Operation of the virtual compute instance at the source host may be paused and the access to the data at the network-based storage resource may be modified to limit access to the destination host. Operation of the virtual compute instance may then resume at the destination host.Type: GrantFiled: March 9, 2017Date of Patent: January 1, 2019Assignee: Amazon Technologies, Inc.Inventors: Pieter Kristian Brouwer, Kristina Kraemer Brenneman, Marc John Brooker, Jerry Lin, Marc Stephen Olson
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Patent number: 10019602Abstract: Systems and methods for improved security for a core in a portable computing device (PCD), such as a core operating a high level operating system (HLOS) are presented. In operation, a monitor module on the SoC is initialized. The monitor module sends a request to the core of the SoC and the monitor module receives a response from the core. A timer in communication with the monitor module is checked. The timer is reset or disabled by the monitor module if the response from the core is received at the monitor module before the expiration of the timer. Otherwise, the monitor module applies at least one security measure to the core as a result of the timer expiring.Type: GrantFiled: August 28, 2014Date of Patent: July 10, 2018Assignee: QUALCOMM IncorporatedInventors: Yoni Kahana, Laurence Geoffrey Lundblade
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Patent number: 9990258Abstract: In a management computer, a memory stores: association information indicating an association among a first physical computer, a virtual computer that is implemented by the first physical computer, a first physical resource that is allocated to the virtual computer, and a user who uses the virtual computer; failure information indicating a failed physical resource; and an upper limit value for a destruction amount as an amount of a physical resource that has failed by being used by the user. A processor calculates the destruction amount, and transmits, upon determining that the first physical resource has failed, that the destruction amount is equal to or less than the upper limit value, and that any of a plurality of physical computers includes the second physical resource, to the first physical computer an instruction to allocate a second physical resource as a replacement for the first physical resource to the virtual computer.Type: GrantFiled: January 31, 2014Date of Patent: June 5, 2018Assignee: Hitachi, Ltd.Inventors: Tomoyuki Sagiyama, Tomohito Uchida
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Patent number: 9678881Abstract: A data distribution device includes: a memory configured to store cache data of data to be distributed; and a processor coupled to the memory and configured to: read the cache data from the memory in accordance with a request message received from other devices to distribute the cache data to the other devices, update, when the request message is received, a counter value that gets closer to a given value with time, so as to make the counter value move away from the given value in accordance with a reference value that is a reciprocal of a threshold value of a reception rate of the request message, whether or not to store the cache data being determined based on the reception rate; and discard the cache data in the memory when the counter value becomes the given value.Type: GrantFiled: November 20, 2014Date of Patent: June 13, 2017Assignee: FUJITSU LIMITEDInventor: Satoshi Imai
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Publication number: 20130024734Abstract: [This invention] inhibits the response time of the storage control apparatus from being longer even if the response time of the storage apparatus is long. The disk adapter (DKA), receiving a read message from the channel adapter (CHA), sets the timeout time in accordance with specified conditions, and tries to read data from the storage apparatus 4. As the timeout time, either the normal value or the shortened value is selected. If a timeout error occurs, the read job is reset, and correction read is started.Type: ApplicationFiled: April 14, 2010Publication date: January 24, 2013Applicant: HITACHI, LTD.Inventor: Eiju Katsuragi
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Publication number: 20120239989Abstract: A mechanism is provided for monitoring and verifying a clock state of a chip that does not write out clock state information. Responsive to identifying an access to the chip, the access is scanned to identify a chip register and a clock domain that will be accessed. A determination is made as to whether a bit of a clock trust unit associated with the chip register and the clock domain indicates whether to trust a clock state associated with the bit in a logical clock state unit. Responsive to the bit of the clock trust unit indicating that the clock state associated with the bit in the logical clock state unit is trusted, the clock state from the logical clock state unit is identified. Responsive to the clock state matching the clock state required by the access, the access is forwarded to the chip for execution.Type: ApplicationFiled: March 14, 2011Publication date: September 20, 2012Applicant: International Business Machines CorporationInventors: Daniel M. Crowell, David D. Sanner, Thi N. Tran
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Publication number: 20120089892Abstract: A method and an apparatus for data management through timer compensation in a wireless communication system are provided. In the method, when a data loss occurs at a first point, whether a data loss has occurred previously and so whether a timer is being driven are determined. Whether the driven timer stops or expires at a second point is determined. When the timer stops or expires at the second point, a timer value is compensated for with consideration of a time difference between the first point and the second point. A timer for the data loss of the first point is restarted based on the compensated timer value. Therefore, a delay of a retransmission request time for lost data in an RLC (Radio Link Control) layer may be minimized.Type: ApplicationFiled: June 16, 2010Publication date: April 12, 2012Inventor: Dong-Jun Kang
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Publication number: 20120089861Abstract: An approach to detecting processor failure in a multi-processor environment is disclosed. The approach may include having each CPU in the system responsible for monitoring another CPU in the system. A CPUn reads a timestampn+1 created by CPUn+1 which CPUn is monitoring from a shared memory location. The CPUn reads its own timestampn and compares the two timestamps to calculate a delta value. If the delta value is above a threshold, the CPUn determines that CPUn+1 has failed and initiates error handling for the CPUs in the system. One CPU may be designated a master CPU, and be responsible for beginning the error handling process. In such embodiments, the CPUn may initiate error handling by notifying the master CPU that CPUn+1 has failed. If CPUn+1 is the master CPU, the CPUn may take additional steps to initiate error handling, and may broadcast a non-critical interrupt to all CPUs, triggering error handling.Type: ApplicationFiled: October 12, 2010Publication date: April 12, 2012Applicant: International Business Machines CorporationInventors: Charles S. Cardinell, Roger G. Hathorn, Bernhard Laubli, Timothy J. Van Patten
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Publication number: 20110185238Abstract: In plural analog circuits that can operate in parallel and are coupled to a common analog power supply terminal, one analog circuit is controlled in the analog operation start according to timing control data that specifies an interval for suppressing the analog operation start of the one analog circuit in the analog operation cycle of the other analog circuit that has already started the analog operation. The control is conducted so that when the operation of one analog circuit starts, timing when the operation of the one analog circuit is influenced by the analog operation start of the other analog circuits in the operation cycle of the one analog circuit is retained as timing control data in advance, and the analog operation start of the other analog circuits is delayed or temporarily suppressed in synchronization with the operation start of the one analog circuit according to the timing control data.Type: ApplicationFiled: January 26, 2011Publication date: July 28, 2011Inventors: HIROSHI ISHIYAMA, Toru Ichien, Fumiki Kawakami
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Publication number: 20110083031Abstract: A system and method for slow ad detection is provided. An ad tool receives information including round trip times to load web pages, in which each web page is loaded with at least one ad. Additionally, the ad tools calculates, for each ad, a mean round trip time to load each web page loaded with the respective ad. The ad tool then determines a predetermined number of the ads with highest mean round trip to load each of the web pages with the ad. Further, the ad tool enables testing of each of the predetermined number of ads to determine the round trip load time of each of the predetermined number of ads.Type: ApplicationFiled: October 7, 2009Publication date: April 7, 2011Applicant: Yahoo! Inc.Inventor: Sandeep Khunteta
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Publication number: 20100287422Abstract: A transmission device including at least one transmitter/receiver unit that is coupled to another transmission device via a communication line, a power supply unit that supplies power to the at least one transmitter/receiver unit, and a control unit that notifies the another transmission device about first sleep start information specifying time at which an operating mode of the at least one transmitter/receiver unit is to be changed to a sleep mode and that stops the supply of power from the power supply unit to the at least one transmitter/receiver unit at the time specified by the first sleep start information.Type: ApplicationFiled: May 10, 2010Publication date: November 11, 2010Applicant: FUJITSU LIMITEDInventor: Keiji MIYAZAKI
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Publication number: 20100269027Abstract: A data processing system is programmed to provide a method for enabling user-level one-to-all message/messaging (OTAM) broadcast within a distributed parallel computing environment in which multiple threads of a single job execute on different processing nodes across a network. The method comprises: generating one or more messages for transmission to at least one other processing node accessible via a network, where the messages are generated by/for a first thread executing at the data processing system (first processing node) and the other processing node executes one or more second threads of a same parallel job as the first thread. An OTAM broadcast is transmitting via a host fabric interface (HFI) of the data processing system as a one-to-all broadcast on the network, whereby the messages are transmitted to a cluster of processing nodes across the network that execute threads of the same parallel job as the first thread.Type: ApplicationFiled: April 16, 2009Publication date: October 21, 2010Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Lakshminarayana B. Arimilli, Ravi K. Arimilli, Robert S. Blackmore
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Publication number: 20100257404Abstract: Described is an improved method, system, and computer program product for preventing concurrent access and processing of data by multiple threads. The inventive approach may be applied to prevent concurrent access in resequencers.Type: ApplicationFiled: April 4, 2009Publication date: October 7, 2010Applicant: ORACLE INTERNATIONAL CORPORATIONInventors: Atul Singh, Maneesh Joshi, Ashwin Patel, Rakesh Saha
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Publication number: 20100211830Abstract: In a particular embodiment, a storage device includes a data storage medium and a read/write circuit coupled the data storage medium via a communication channel. The read/write circuit includes a formatter circuit to receive a read back signal related to data stored on the data storage medium and to produce an output vector related to the read back signal. The read/write circuit further includes a multiple-input multiple-output (MIMO) equalizer coupled to the formatter circuit and adapted to generate an equalized output vector related to the output vector. The read/write circuit also includes a MIMO detector coupled to the MIMO equalizer and adapted to generate hard bit decisions based on the equalized output vector.Type: ApplicationFiled: February 13, 2009Publication date: August 19, 2010Applicant: Seagate Technology LLCInventors: Sundararajan Sankaranarayanan, Raman Venkataramani
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Patent number: 7774679Abstract: Techniques are provided for performing Galois field arithmetic to detect errors in digital data stored on disks. Two 12-bit numbers or two 10-bit numbers are multiplied together in Galois field using tower arithmetic. In the 12-bit embodiment, a base field GF(2) is first extended to GF(23), GF(23) is extended to a first quadratic extension GF(26), and GF(26) is extended to a second quadratic extension GF(212). In the 10-bit embodiment, the base field GF(2) is first extended to GF(25), and GF(25) is extended to a quadratic extension GF(210). Each of the extensions for the 10-bit and 12-bit embodiments is performed using an irreducible polynomial. All of the polynomials used to generate the first and the second quadratic extensions of the Galois field are in the form x2+x+K, where K is an element of the ground field whose absolute trace equals 1.Type: GrantFiled: February 14, 2005Date of Patent: August 10, 2010Assignee: Hitachi Global Storage Technologies Netherlands B.V.Inventors: Martin Hassner, Vipul Srivastava, Kirk Hwang
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Publication number: 20100153791Abstract: One process of a processing environment maintains state on behalf of another process of the processing environment, and uses that state to determine if a problem exists with the another process. The one process is a non-volatile process, while the another process is a volatile process.Type: ApplicationFiled: December 15, 2008Publication date: June 17, 2010Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Barry P. Gower, Daniel S. Gritter
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Publication number: 20100125747Abstract: Disclosed is a computer implemented method, data processing system, and apparatus to respond to detection of a hardware interface error on a system bus, for example, during a concurrent maintenance operation. The service processor may receive an error on the system bus. The error identifies at least one field replaceable unit and may inhibit the suppression of clock signal to the field replaceable unit. The service processor adds an identifier of the field replaceable unit to an eligible Field Replaceable Unit (FRU) list. The service processor recursively adds at least one field replaceable unit that the field replaceable unit depends upon. The service processor suppresses the clock signal to the field replaceable unit. The service processor inhibits tagging the field replaceable unit as unusable for next initial program load.Type: ApplicationFiled: November 20, 2008Publication date: May 20, 2010Applicant: International Business Machines CorporationInventors: Sheldon Ray Bailey, Bradley W. Bishop, Alongkorn Kitamorn, Erlander Lo, Allegra R. Segura
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Publication number: 20100070814Abstract: Systems and methodologies are described that facilitate utilizing timers in conjunction with transmitting buffer status reports (BSR). A prohibit timer can be utilized to determine when BSRs can be transmitted to an eNB. The prohibit timer can be initialized or restarted upon transmitting a BSR to an eNB. A BSR retransmit timer can be used to determine when to retransmit a BSR. The BSR retransmit timer can be initialized upon transmitting a BSR to an eNB and restarted each time an uplink resource allocation is received from the eNB. Once the timer expires, if an uplink transmission buffer contains data (e.g., size>0), the BSR can be retransmitted to the eNB. Control data feedback can additionally be used to determine when to retransmit the BSR. In addition, in either case, the timer duration values can be provided by the eNB.Type: ApplicationFiled: September 1, 2009Publication date: March 18, 2010Applicant: QUALCOMM INCORPORATEDInventors: Aleksandar Damnjanovic, Sai Yiu Duncan Ho
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Publication number: 20100011258Abstract: An administrator can specify a script sequence including one or more system scripts and database scripts. A graphical user interface is provided to allow the administrator to specify an execution order of individual scripts in the script sequence and a timeout interval for when the script sequence will complete. Once the script sequence is specified, the script sequence can be run without further intervention by the administrator.Type: ApplicationFiled: July 11, 2008Publication date: January 14, 2010Applicant: APPLE INC.Inventors: Erwin Hom, Jonathan Thatcher, Mark Davidson
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Publication number: 20090300403Abstract: A client sends a request message to a process hosted by a remote server via a middleware service, wherein the request message specifies a procedure for the process to execute. The client waits a predetermined time period to receive a response message from the process. If no response message is received within the predetermined time period, the client probes the process to determine why no response message has been received, wherein said probing reveals thread level information about the process.Type: ApplicationFiled: May 30, 2008Publication date: December 3, 2009Inventor: Mark Cameron Little
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Publication number: 20090300435Abstract: A method for monitoring a process execution of a plurality of sequentially executed processes starts one of a plurality of timers in cyclic permutation when one of the processes is started, and outputs a first error signal when a period of time recorded by one of the timers exceeds a predefined maximum period of time.Type: ApplicationFiled: December 30, 2005Publication date: December 3, 2009Inventors: Ruediger Karner, Alexander Jansen
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Publication number: 20090292957Abstract: The present invention provides a computer implemented method and apparatus for unmounting file systems from a plurality of file servers. The method comprises of issuing an unmount command targeting a file system of a first server among the plurality of file servers. The timeout period is then expired without receiving an unmount acknowledgement associated with the unmount command. Thus, the timeout period is associated with an allowable time for the file system to acknowledge unmounting. In response to expiring the timeout period, a ping is transmitted to the first server among the plurality of file servers. The ping timeout then expires based on a failure to receive a ping acknowledgment corresponding to the ping. This action marks the first server for a later retry of unmounting to form a marked set based on the first server.Type: ApplicationFiled: May 21, 2008Publication date: November 26, 2009Applicant: International Business Machines CorporationInventors: Carlie Sue Bower, Saurabh Kumar Gupta, Avanish Kumar Ojha, Muthulaxmi Pearl Srinivasan
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Publication number: 20090276667Abstract: Described are techniques for providing an application program interface that leverages the terminal services session broker infrastructure to support third party plug-in applications. In a typical scenario, when a user requests for a connection to access third party plug-in applications, the application program interface may override the session broker logic and interacts with the session broker process to identify sessions or suitable servers to which the user can be connected. The user may access the third party plug-in applications through the identified sessions or suitable servers.Type: ApplicationFiled: May 2, 2008Publication date: November 5, 2009Applicant: Microsoft CorporationInventors: David T. Dopson, Rouslan Beletski, Sriram Sampath, Ido Ben-Shachar
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Publication number: 20090265576Abstract: The inventive system and method for determining the availability of a computer network comprises a device operable to connect to at least the computer network using internet communications and using GSM, and an alarm service and/or a central server, wherein the device attempts to connect to the computer network using the internet communications and if the device fails to connect within a predetermined value, such as an amount of time or a number of tries, the device uses the GSM to notify the alarm service of the failure to connect. In one embodiment, after the device notifies the alarm service and/or central server of the failure to connect, the device continues to attempt to connect to the computer network, and if the device connects within another predetermined value, the device notifies the alarm service and/or central server of the restoral of service.Type: ApplicationFiled: April 22, 2008Publication date: October 22, 2009Applicant: HONEYWELL INTERNATIONAL INC.Inventor: William R. Blum
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Publication number: 20090204854Abstract: A method, system, and product for monitoring the availability of a data processing system are proposed. The system runs a management application involving the periodic transmission of blocks of data from multiple local computers to a central computer. Whenever a block of data must be transmitted by a generic local computer, an expected transmission delay of a next block of data (with respect to the current one) is estimated and attached to the block of data. The central computer receiving the updated block of data can calculate an expected receiving time of the next block of data accordingly. If the next block of data is not received in due time, the central computer determines a failure of the local computer. The central computer also scans a subset of ports of the local computer, to ascertain whether the problem is due to a temporary unavailability of the application.Type: ApplicationFiled: December 4, 2008Publication date: August 13, 2009Applicant: International Business Machines CorporationInventors: Salvatore D'Alo, Arcangelo Di Balsamo, Alessandro Donatelli
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Publication number: 20090119539Abstract: Provided is a method, system, and program for processing Input/Output (I/O) requests to a storage network including at least one storage device and at least two adaptors, wherein each adaptor is capable of communicating I/O requests to the at least one storage device. An error is detected in a system including a first adaptor, wherein the first adaptor is capable of communicating on the network after the error is detected. In response to detecting the error, a master switch timer is started that is less than a system timeout period if the first adaptor is the master. An error recovery procedure in the system including the first adaptor would be initiated after the system timeout period has expired. An operation is initiated to designate another adaptor in the storage network as the master if the first adaptor is the master in response to detecting an expiration of the master switch timer.Type: ApplicationFiled: January 8, 2009Publication date: May 7, 2009Applicant: International Business Machines CorporationInventors: Matthew John Fairhurst, Michael John Jones, Vernon J. Legvold, Michael P. Vageline
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Publication number: 20090113255Abstract: The invention provides for software fault detection. A software process tracks its own progress. In the event the timer times out, a handler checks the progress. If the progress meets a fault criterion, a fault response is executed.Type: ApplicationFiled: October 30, 2007Publication date: April 30, 2009Inventor: John R. Reilly
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Publication number: 20090070639Abstract: Administering correlated error logs in a computer system having a system controller and one or more redundant node controllers including providing by the system controller to a redundant node controller a unique identifier for error logs; detecting by the system controller a communications failure between the system controller and the redundant node controller; in response to detecting the communications failure, generating by the system controller a system controller error log for the communications failure including the unique identifier; detecting by the redundant node controller the communications failure between the system controller and the redundant node controller; and in response to detecting the communications failure, generating by the redundant node controller a redundant node controller error log for the communications failure including the unique identifier.Type: ApplicationFiled: September 12, 2007Publication date: March 12, 2009Applicant: International Business Machines CorporationInventors: John S. Langford, Atit D. Patel, Joshua N. Poimboeuf
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Publication number: 20090044041Abstract: A redundant data bus system has two data buses between which at least two failsafe control devices are connected. The two data buses operate with the same data bus protocol at essentially the same transmission frequency, and safety-related control messages are transmitted in parallel via both data buses and processed in the control devices. Each control device performs a separate control task via assigned control software. Each control device has two microcomputers which operate independently of one another and which have software for both the first and the second control tasks. When one control device fails, the control task can also be performed by the other. One data interface is arranged between the two microcomputers, via which result data calculated from the safety-related control messages can be exchanged and compared with one another. Based on such comparison a decision means determines which microcomputer or control device carries out a control task.Type: ApplicationFiled: January 15, 2005Publication date: February 12, 2009Inventors: Michael Armbruster, Sascha Paasche, Reinhard Reichel, Andreas Schwarzhaupt, Gernot Spiegelberg, Armin Sulzmann
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Publication number: 20090037770Abstract: A method for handling watchdog events of an electronic device includes detecting a watchdog fault in a normal mode, which is a watchdog event in which a watchdog trigger is not correctly serviced; entering from the normal mode into a first escalation level of nx escalation levels upon detection of the watchdog fault, wherein nx is an integer equal to or greater than 1; detecting correct watchdog events, which are watchdog events in which a watchdog trigger is correctly serviced; and concurrently detecting watchdog faults, leaving the first escalation level if a first escalation condition is met. An electronic device embodiment includes a CPU and program instructions for carrying out the method.Type: ApplicationFiled: July 30, 2008Publication date: February 5, 2009Applicant: TEXAS INSTRUMENTS DEUTSCHLAND GMBHInventors: Rainer Troppmann, Guiseppe Maimone
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Publication number: 20090031163Abstract: A circuit comprises a first plurality of transistors of a first channel length disposed along a speedpath, the first plurality of transistors providing a first timing performance. The circuit also comprises a second plurality of transistors of a second channel length having an expected equivalent functionality as the first plurality of transistors and disposed in parallel with the first plurality of transistors along the speedpath, wherein the second channel length is different from the first channel length. In addition, the circuit comprises an element configured to selectively replace the first plurality of transistors with the second plurality of transistors in response to a determination that the first timing performance of the first plurality of transistors fails a timing requirement of the speedpath. In one embodiment, the second channel length is a sub-minimal geometry with respect to the first channel length.Type: ApplicationFiled: July 27, 2007Publication date: January 29, 2009Inventors: Mahbub M. Rashed, Milind P. Padhye
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Publication number: 20080307273Abstract: A method of predicting failure of an information handling device, such as a server, by monitoring an error rate, i.e., n errors per error period. Errors are reported only if the error rate is exceeded. An error count is kept, and errors are leaked from the count if the time difference between errors is more than the error period.Type: ApplicationFiled: June 6, 2007Publication date: December 11, 2008Applicant: DELL PRODUCTS L.P.Inventors: Tuyet-Huong T. Nguyen, Mukund Khatri
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Publication number: 20080052563Abstract: An apparatus and method for reducing false triggering of a signal due to an electrostatic discharge event are disclosed. The method includes detecting a high voltage on a signal received at an input of a delay circuit and delaying the signal between the input of the delay circuit and an output of the delay circuit for a predetermined amount of time. If a low voltage is detected on the signal after the predetermined amount of time, the high voltage is prevented from propagating to the output of the delay circuit.Type: ApplicationFiled: May 31, 2007Publication date: February 28, 2008Applicant: DELL PRODUCTS L.P.Inventor: Leroy Jones
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Publication number: 20080052557Abstract: Provided is a method, system, and program for processing Input/Output (I/O) requests to a storage network including at least one storage device and at least two adaptors, wherein each adaptor is capable of communicating I/O requests to the at least one storage device. An error is detected in a system including a first adaptor, wherein the first adaptor is capable of communicating on the network after the error is detected. In response to detecting the error, a master switch timer is started that is less than a system timeout period if the first adaptor is the master. An error recovery procedure in the system including the first adaptor would be initiated after the system timeout period has expired. An operation is initiated to designate another adaptor in the storage network as the master if the first adaptor is the master in response to detecting an expiration of the master switch timer.Type: ApplicationFiled: October 30, 2007Publication date: February 28, 2008Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Matthew Fairhurst, Michael Jones, Vernon Legvold, Michael Vageline