Abstract: Certain aspects of the present disclosure generally relate to techniques for compactly describing lifted low-density parity-check (LDPC) codes. A method by a transmitting device generally includes selecting a first lifting size value and a first set of lifting values; generating a first lifted LDPC code by applying the first set of lifting values to interconnect edges in copies of a parity check matrix (PCM) having a first number of variable nodes and a second number of check nodes; determining a second set of lifting values for generating a second lifted LDPC code for a second lifting size value based on the first lifted PCM and the first set of lifting values; encoding a set of information bits based the first lifted LDPC code or the second lifted LDPC code to produce a code word; and transmitting the code word.

Abstract: A method for evaluating a margin of at least one parameter utilized by a transmission interface includes: step (A) setting a value of a first parameter utilized by a host device to a first test value selected from a first group; (B) setting a value of a second parameter utilized by a data storage device to a second test value selected from a second group; (C) controlling the data storage device to perform a predetermined testing procedure to test whether the data storage device functions normally when the first test value and the second test value are applied; and (D) changing the first test value or the second test value and re-performing steps (A) to (C), wherein step (D) is repeatedly performed until all the test values in the first group and the second group have been tested.

Abstract: A fault detection method includes: obtaining a scheduling table of a target task, where the scheduling table is used to indicate at least one test pattern, the at least one test pattern is used to detect a fault in a target logic circuit, and the target logic circuit is a logic circuit configured to execute the target task; and executing the at least one test pattern based on the scheduling table, to detect the fault in the target logic circuit.

Abstract: A character recognition device includes a recognizer that recognizes at least one character string from an image including a trailer captured by an imaging device, and a selector. The selector selects character strings conforming to a specified notation format among the character strings recognized by the recognizer as candidates of a trailer ID/container ID, and that selects one of the candidates of the trailer ID/container ID, which has a similarity to master data of a previously held trailer ID/container ID equal to or larger than a predetermined threshold value as the trailer ID/container ID.

Abstract: An information processing apparatus includes: one or more processors; and one or more memories storing one or more computer programs. The one or more computer programs, when executed by the one or more processors, cause the information processing apparatus to function as: a reception unit configured to receive history information, from a device, indicating an operation history of a predetermined operation in the device; an analysis unit configured to analyze a condition of the device based on the history information in a case where an execution condition is satisfied; and a setting unit configured to set the execution condition, and wherein the setting unit sets the execution condition based on an analysis result by the analysis unit.

Abstract: Methods, systems, and devices for techniques for memory error correction are described. A memory device operates in cycles associated with refresh operations and in cycles associated with refresh with error correction (ECC) operations independently. For example, the memory device includes an ECC patrol block having an error correction counter which indicates a row on which to perform an error correction procedure. Additionally, the memory device may include a refresh counter which indicates a row on which to perform a refresh operation. In response to receiving a command of a first type, the memory device modifies the error correction counter and maintains the refresh counter. Alternatively, in response to receiving a command of a second type, the memory device modifies the refresh counter and maintains the error correction counter.

Abstract: A method is performed by a bus coupler of a subnetwork of one or more local subnetworks coupled to an overall network is provided, including performing a local discovery process for discovering and identifying one or more bus devices included in the subnetwork. The method further includes submitting an internet protocol (IP) address request to obtain an IP address for the bus coupler, receiving at the bus coupler the IP address of the bus coupler in response to the IP address assignment request, submitting a configuration request for configuration information associated with a device name for the bus coupler, receiving the configuration information in response to the configuration request, and configuring at least one feature of the bus coupler using the configuration information, wherein the device name is based on identifier(s) of the respective one or more bus devices obtained by the discovery process.

Abstract: A method of dynamic configuration of reaction policies in virtualized fault management system includes disabling a fault handler circuit comprising a reaction core in response to receiving a request to modify a respective first reaction policy including a plurality of first recovery actions of the reaction core, wherein each of the first recovery actions is responsive to a respective fault indication. At least one event status is cleared from an event table of the fault handler circuit. The at least one event status is set in response to the fault handler circuit receiving the respective fault indication. The reaction core is configured with a second reaction policy including a plurality of second recovery actions.

Abstract: Described herein is a generic hardware/software communication (HSC) channel that facilitates the re-use of pre-silicon DPI methods to enable FPGA-based post-silicon validation. The HSC channel translates a DPI interface into a hardware FIFO based mechanism. This translation allows the reuse of the methods without having to re-implement the entire flow in pure hardware. The core logic for the transactor remains the same, while only a small layer of the transactor is converted into the FIFO based mechanism.

Abstract: A family of digital logic functions has the same specifications for input and output voltages and the same number of bond pads. A digital logic integrated circuit for the family includes a substrate of semiconductor material having a core area and a peripheral area; a certain number of bond pads formed in the peripheral area, the certain number of bond pads determining the total area of the substrate; programmable digital logic transistor circuitry formed in the core area for each of the digital logic functions in the family; programmable input and output circuitry formed in the peripheral area; programming circuitry for programming the programmable digital logic transistor circuitry into a selected digital logic function; and programmable input and output means for programming the input and output circuitry into input and output circuits for the selected digital logic function.

Abstract: A configuration setting manager of a memory device receives a request to perform an adjustment operation on a set of configuration setting values for the memory device, where each configuration setting value of the set of configuration setting values is stored in a corresponding configuration register of a set of configuration registers; determines a configuration adjustment definition associated with one or more configuration setting values of the set of configuration setting values; calculates an updated set of configuration setting values by applying a multiplier value to the configuration adjustment definition, wherein the multiplier value is associated with a number of programming operations performed on the memory device; and stores the updated set of configuration setting values in the corresponding configuration registers.

Abstract: A system includes a memory and a processor. The memory stores a queue that includes a sequence of slots, each of which is configured to store a request. The processor receives, from a user device, a request for information. In response, the processor stores the request in an end slot of the queue. The processor collects values for parameters associated with the system. The processor determines, based on the request and the collected values for the parameters, an estimate of a time to generate a response to the request. Generating the response includes identifying an application for use in generating the response, generating, based on a set of videos of processes previously performed using the application, instructions for interfacing with the application to generate the response, and executing the instructions to interface with the application. The processor further transmits, to the user device, the estimate of the time.

Abstract: Certain aspects of the present disclosure generally relate to techniques for compactly describing lifted low-density parity-check (LDPC) codes. A method by a transmitting device generally includes selecting a first lifting size value and a first set of lifting values; generating a first lifted LDPC code by applying the first set of lifting values to interconnect edges in copies of a parity check matrix (PCM) having a first number of variable nodes and a second number of check nodes; determining a second set of lifting values for generating a second lifted LDPC code for a second lifting size value based on the first lifted PCM and the first set of lifting values; encoding a set of information bits based the first lifted LDPC code or the second lifted LDPC code to produce a code word; and transmitting the code word.

Abstract: A non-volatile storage apparatus includes a plurality of non-volatile memory cells formed on a memory die, each non-volatile memory cell configured to hold a plurality of bits of data, and a control circuit formed on the memory die. The control circuit is configured to calculate parity data for data to be stored in the memory cells and program the memory cells to first distributions. The control circuit is also configured to read memory cells in the first distributions, recover the data from results of reading the memory cells in the first distributions combined with the parity data, and further program the memory cells from the first distributions to second distributions to store the data.

Abstract: An apparatus and/or system is described including a memory device including a memory range and a temporal data management unit (TDMU) coupled to the memory device to receive from an interface, the memory range and a temporal range corresponding to validity of data in the memory range, check the temporal range against a time and/or date value provided by a timer or clock to identify the data in the memory range as expired, and invalidate the data that is expired in the memory device. In some embodiments, the TDMU includes hardware logic that resides on a memory module with the memory device and is coupled to invalidate expired data when the memory module is decoupled from the interface. Other embodiments may be disclosed and claimed.

Abstract: Stratigraphic picks data from at least one first database are processed to ensure conformance with data conditions. The stratigraphic picks data can be filtered by removing at least some of the stratigraphic picks data that does not conform with the data conditions to generate filtered stratigraphic picks data. At least some data in a second database that matches at least some of the filtered stratigraphic picks data is identified. The identified at least some data can be processed to remove the identified at least some data from the second database, and to process the filtered stratigraphic picks data to add the filtered stratigraphic picks data to the second database. Further, a report can be generated identifying any of the filtered stratigraphic picks data that were successfully added to the second database and any of the stratigraphic data that were not successfully added to the second database.

Abstract: A method for optimizing a verification regression includes obtaining data, by a processor, of previously executed runs of at least one verification regression session; extracting from the data, by the processor, values of one or a plurality of control knobs and values of one or a plurality verification metrics that were recorded during the execution for each of the previously executed runs of said at least one verification regression; finding, by the processor, correlation between said one or a plurality of the control knobs and each said one or a plurality of verification metrics, and generating a set of one or a plurality of control conditions based on the found correlation; and applying, by the processor, the generated set of one or a plurality of control conditions on the verification environment or on the DUT, or on both, to obtain a new verification regression session.

Abstract: Methods, systems, and devices for memory operations are described. A codeword may be associated with a set of data and stored in a memory device may be detected as having a plurality of bit errors. Based on detecting the plurality of bit errors in the codeword, an address of the codeword may be stored and an indication that at least one codeword stored in the memory device has a plurality of bit errors may be indicated. Based on indicating that at least one codeword in the memory device has a plurality of bit errors, a write command for writing, to the memory device, a second codeword associated with the set of data may be received. Additionally, or alternatively, a command that triggers an error correction operation at an address range of the memory device may be received at a memory device.

Abstract: Apparatus might include an array of memory cells and a controller for access of the array of memory cells. The controller might be configured to cause the apparatus to apply a sense voltage level to a control gate of a memory cell of the array of memory cells, generate N determinations whether the memory cell is deemed to activate or deactivate while applying the sense voltage level, wherein N is an integer value greater than or equal to three, deem the memory cell to have a threshold voltage in a first range of threshold voltages lower than the sense voltage level in response to a majority of the N determinations indicating activation of the memory cell, and deem the memory cell to have a threshold voltage in a second range of threshold voltages higher than the sense voltage level in response to a majority of the N determinations indicating activation of the memory cell.

Abstract: Methods and systems for load balancing are described. A network node may replicate content. A lag time may be determined. A data structure may be generated that comprises the lag time.

Abstract: A method and system for determining and resolving network issues impacting application performance in multi-domain networks is disclosed. The method includes obtaining at least one of health and performance data associated with an application and one or more alerts related to fault and/or performance issues associated with the application. The method further includes determining at least one of network faults and performance issues that influence at least one of fault and/or performance issues associated with the application. The method further includes determining one or more underlying network problems that impact performance of the application. The method further includes determining at least one appropriate resolution action to address the one or more underlying network problems, implementing the at least one appropriate resolution action; monitoring an effectiveness of the implementation of the at least one appropriate resolution action; and adapting at least one of rules, parameters, and thresholds.

Abstract: Systems, methods, and computer program products for searching objects, metadata associated with the objects, and attributes assigned to or associated with the metadata. Referring to herein as metadata for the metadata, these attributes may be associated with one or more metadata field values of a metadata field name which, in turn, may be associated with an object being or already indexed in a search index of a search system. Each attribute may be optional, dynamically created, indexed, and searchable via the search index. There can be multiple attributes associated with the same metadata field value, each being represented as a key-value pair. This metadata for the metadata approach can be highly efficient. For example, the ability to search multiple attributes associated with the same metadata field can eliminate the potential need to create multiple metadata fields for the same value in different languages, countries, etc.

Abstract: In some examples, an analyzer manager configured to select one of a program code analyzer, a static data analyzer, and an unused memory location analyzer for malware detection within memory of a system. The program code analyzer can be executed to evaluate instruction data for executing a computer program at a first set of memory locations within the memory for malware in response to being selected by the analyzer manager. The static data analyzer can be executed to evaluate static data for use by the computer program at a second set of memory locations within the memory for the malware in response to being selected by the analyzer manager. The unused memory location analyzer can be executed to evaluate null data indicative of unused memory locations at a third set of memory locations within the memory for the malware in response to being selected by the analyzer manager.

Abstract: An information processing device includes: an identifier adding unit that adds identifiers including at least one type of valid identifier to each of a plurality of pieces of information; a plurality of input memories that hold the plurality of pieces of information and the identifiers, respectively; a plurality of output memories that hold a plurality of pieces of information processed by the processing unit and the identifiers added to the plurality of pieces of information, respectively; and an identifier inspecting and verifying unit that performs inspection and verification by comparing at least one identifier that becomes an inspecting and verifying target identifier among the identifiers to the valid identifier held in the input memory corresponding to the output memory that holds the inspecting and verifying target identifier.

Abstract: Techniques for command bus training to a memory device includes triggering a memory device to enter a first or a second command bus training mode, outputting a command/address (CA) pattern via a command bus and compressing a sampled CA pattern returned from the memory device based on whether the memory device was triggered to be in the first or the second command bus training mode.

Abstract: The disclosure relates to system and method for managing security risk of information technology (IT) systems in an enterprise. The method includes determining valid trustware components that need to be evaluated for security risk of an IT system within the enterprise; correlating information associated with each of the valid trustware components in a set of data repositories; generating a mapping list comprising the valid trustware components, test cases corresponding to each of the valid trustware components, and test environments corresponding to each of the valid trustware components based on the correlation; triggering trustware security units for testing the valid trustware components based on the mapping list; and identifying security issues associated with the valid trustware components based on the testing. The trustware security units are arranged in a sequential manner or a parallel manner to align with execution of the test cases corresponding to each of the valid trustware components.

Abstract: A chiplet system can include a Serial Peripheral Interface (SPI) bus for communication. A controller or primary device coupled to the SPI bus can generate a message with read or write instructions for one or more secondary devices. In an example, the primary device can be configured to use information on a data input port or data input bus to determine a communication status of one or multiple secondary devices on the bus.

Abstract: Methods and apparatuses for improve data clock to reduce power consumption are presented. The apparatus includes a memory configured to receive a data clock from a host via a link and to synchronize the data clock with the host. The memory includes a clock tree buffer configured to toggle based on the data clock to capture write data or to output read data and a command decoder configured to detect a data clock suspend command while the data clock is synchronized between the host and the memory. The clock tree buffer is configured to disable toggling based on the data clock in response to the command decoder detecting the data clock suspend command. the host includes a memory controller configured to provide a data clock suspend command to the memory via the link while the data clock is synchronized between the host and the memory.

Abstract: A PPR memory location reporting system includes BIOS coupled to a non-volatile memory system and a volatile memory system. During boot operations, the BIOS identifies a memory location identifier in the non-volatile memory system for a memory location that is included in the volatile memory system and that is associated with PPR, performs PPR operations on the memory location, and determines that the PPR operations on the memory location have failed. In response to determining that the PPR operations on the memory location have failed, the BIOS stores the memory location identifier in a boot error report table that is configured for use by an operating system to prevent use of the memory location by the operating system, and reserves the memory location identifier in a memory map that is configured for use by the operating system to prevent use of the memory location by the operating system.

Abstract: An automated testing framework and associated tools for executable applications such as games focus on integration testing, wherein users create data-driven tests by using test modules and configuration data as building blocks. The tools facilitate cooperation between coders and non-technical Quality Assurance (QA) staff in creating automated tests, by simplifying the user interface for configuring tests. Components of the tools simulate user interactions with the application under test, for example, gamepad button presses. The tools are also capable skipping portions of gameplay or other interactive activity and directly jumping into a desired game mode during automated testing, and other functions.

Abstract: A method for transmitting an information block on the basis of a low density parity check (LDPC) code in a wireless communication system, according to the present disclosure, may comprise: encoding an information block on the basis of a LDPC basegraph H_BG including [MATRIX]; and transmitting the encoded information block. Each element of H_BG is either zero (“0”) or one (“1”), and each element which is “0”, among the elements of H_BG, may represent a Z×Z zero matrix, and each element which is “1”, among the elements of H_BG, may represent a Z×Z matrix acquired on the basis of a circular permutation matrix acquired by circularly shifting a Z×Z identity matrix to the left or right. The submatrix T_BG of H_BG may be a dual diagonal matrix, and the submatrix D_BG of H_BG may be a dual diagonal matrix. The encoding of the information block on the basis of H_BG may comprise encoding the information block on the basis of a parity check matrix (PCM) H which corresponds to H_BG.

Abstract: In an approach to extending the lifespan of a flash-based storage device, responsive to receiving a signal from a storage device that the storage device is low on extra blocks, one or more free logical blocks that are no longer needed are released. The storage device is notified of the one or more free logical blocks that are no longer needed. Responsive to determining that the number of valid physical blocks is greater than the number of used logical blocks, the advertised capacity of the storage device is reduced.

Abstract: A data processing device for processing telemetry data obtains sampled data based on output data from a plurality of sensors associated with a vehicle. The data processing device generates first and second sets of sampled values using the sampled data. The first set of sampled values are associated with a first sampling time and the second set of sampled values are associated with a second, subsequent sampling time. The data processing device derives a set of data elements, a data element being indicative of a measure of a change between a sampled value in the first set and a corresponding sampled value in the second set, a position of a given data element in the set of data elements having been determined based on at least one mapping rule. The data processing device encodes the set of data elements and outputs data comprising at least the encoded set of data elements for transmission to a remote data processing unit.

Abstract: This disclosure provides techniques hierarchical address virtualization within a memory controller and configurable block device allocation. By performing address translation only at select hierarchical levels, a memory controller can be designed to have predictable I/O latency, with brief or otherwise negligible logical-to-physical address translation time. In one embodiment, address transition may be implemented entirely with logical gates and look-up tables of a memory controller integrated circuit, without requiring processor cycles. The disclosed virtualization scheme also provides for flexibility in customizing the configuration of virtual storage devices, to present nearly any desired configuration to a host or client.

Abstract: An automated warehouse has a main path, secondary paths, a main vehicle movable along the main path, one or more auxiliary vehicles movable along the secondary paths, and an access point. On each vehicle a wireless device receiving and sending wireless signals and a control unit associated with safety modules including a safety-certified watchdog timer and a counter are installed. The wireless devices send check signals containing the value of the counter of the respective vehicle to the access point, which sends signals in response to received check signals When a response signal is received from a wireless device, the respective counter is incremented and the associated watchdog timer starts to measure time when the value of the counter differs from the value received via check signals. Each control unit de-energizes the respective vehicle when a time longer than a predetermined time is detected via the watchdog timer.

Abstract: Disclosed herein are a cryptocurrency trading system and method. The cryptocurrency trading system includes: a first matching server configured to generate a transaction pair by matching an order requesting a cryptocurrency transaction with another order to be concluded in conjunction with the former order in order to process the former order; and a coordination device configured to add the first matching server to the cryptocurrency trading system. When the first matching server fails, the coordination device registers a second matching server and allows the second matching server to process the former order.

Abstract: A mechanism is provided for relaying events from a storage controller to a host server. Responsive to identifying an event occurring within a storage device, a notification is sent to a device server in the host server with which the event is associated. A server virtual disk is identified using a unique identification of the server virtual disk. Responsive to identifying the server virtual disk, at least one device executing an application on the host server is notified of an impending degradation in a mode of operation.

Abstract: A system, method, and computer program product are provided for redirecting internet relay chat (IRC) traffic identified utilizing a port-independent algorithm and controlling IRC based malware. In use, IRC traffic communicated via a network is identified utilizing a port-independent algorithm. Furthermore, the IRC traffic is redirected to a honeypot.

Abstract: The present inventions are related to systems and methods for an LDPC decoder with dynamic Tanner graph modification, and in particular, to a non-erasure channel LDPC decoder that implements a probabilistic approach to Tanner graph modification.

Abstract: The present inventions are related to systems and methods for an LDPC decoder with variable node hardening, and in particular, to an LDPC decoder that temporarily hardens the value of a variable node by using check node to variable node (C2V) messages from a previous iteration that are likely to be correct when generating variable node to check node (V2C) messages.

Abstract: An electronic device including a NAND flash memory, an auxiliary memory, and a controller is provided. A code for detecting a read command sequence of the NAND flash memory is stored in the auxiliary memory. During a boot procedure of the electronic device, the controller reads the code from the auxiliary memory and executes the code to obtain the read command sequence of the NAND flash memory, so as to access content stored in the NAND flash memory according to the read command sequence.

Abstract: Disclosed are embodiments of an integrated circuit that incorporates an asynchronous circuit with a built-in self-test (BIST) architecture using a handshaking protocol for at-speed testing to detect stuck-at faults. In the embodiments, a test pattern generator applies test patterns to an asynchronous circuit and an analyzer analyzes the output test data. The handshaking protocol is achieved through the use of a single pulse generator, which applies a single pulse to the test pattern generator to force switching of the test pattern request signal and, thereby to control application of the test patterns to the asynchronous circuit and subsequent switching of the test pattern acknowledge signal. Generation of this single pulse can in turn be forced by the switching of the test pattern acknowledge signal. Optionally, a time constraint can be added to the capture of the output test data to allow for detection of delay faults.

Abstract: In storage subsystems, due to the significant increase in HDD capacity, the time for executing online verification is elongated, affecting accesses from the host computer. By comprehending the status of accesses to the HDD, the sections where error has occurred and the status of restoration thereof, it becomes possible to detect defective or error sections efficiently at an early stage, according to which the reliability and access performance of the storage subsystem can be improved. The present storage subsystem executes one or more of the following processes: (M1) intensive verification of a circumference of an error LBA, (M2) an area-based prioritized verification, and (M3) continuous verification performed for a long period of time to (V1) an area in which error has occurred via IO access, (V2) a highly accessed area, and (V3) during a period of time when IO access is low.

Abstract: An information processing apparatus includes: a memory in which an apparatus-unique key is stored, the apparatus-unique key being a key that is unique to the information processing apparatus; an input section that inputs user operation information; a communication section that performs data reception processing; a data processor that executes validity determination processing for the apparatus-unique key; and an output section that outputs a result of the validity determination processing executed by the data processor. The data processor receives, via the communication section, key-validity determination data for determining whether the apparatus-unique key is valid or invalid. The data processor also executes the apparatus-unique-key validity determination processing by using the key-validity determination data in response to a user instruction input via the input section, and outputs a result of the validity determination processing to the output section.

Abstract: In a system, a data receiving device comprises a timing signal generation unit that generates a timing signal used for receiving the divided transmission data in each of the transmission paths, a data receiving unit that receives the divided transmission data transmitted by the data transmitting device for each of the transmission paths by using the timing signal generated by the timing signal generation unit, and an error detection unit that extracts the error detection information from the divided transmission data received for each of the transmission paths by the data receiving unit and detects an error of transmission data included in the divided transmission data by using the extracted error detection information.

Abstract: A method for detecting and reporting changes in functional features of a simulation model caused by a software revision is disclosed. In one aspect, the method is independent of simulation model architecture. One performs regression testing with a plurality of feature-specific modules. The feature-specific modules are configured to generate a first set of information with the simulation model and compare the first set of information to a second set of corresponding information from the simulation model. In the above-described testing, the first set of information postdates the software revision and the second set of information predates the software revision.

Abstract: The exemplary embodiments of the present invention provide a method for efficiently identifying the bad component(s) in a multi-node system. The method includes assigning a unique ID to each of a plurality of nodes on the multi-node system, generating test statistics from a test on a plurality of nodes, and comparing the test statistics for the plurality of nodes against a first topology to generate a first number of clusters of bad nodes. The method further includes comparing the test statistics for the plurality of nodes against a second topology to generate a second number of clusters of bad nodes, and identifying the bad nodes by comparing the cluster sizes to a topology threshold.

Abstract: A staggered execution environment is provided to safely execute an application program against software failures. In an embodiment, the staggered execution environment includes one or more probe virtual machines that execute various portions of an application program and an execution virtual machine that executes the same application program within a time delay behind the probe virtual machines. A virtualization supervisor coordinates the execution of the application program on one or more probe virtual machines. The probe virtual machines are used to detect and correct software failures prior to the execution virtual machine encountering them. The virtualization supervisor embargos output data in order to ensure that erroneous data is not released which may adversely affect external processes.

Abstract: A system embodiment comprises a nonvolatile memory device, a memory, and a controller. The nonvolatile memory device includes a plurality of nonvolatile memory cells. Each nonvolatile memory cell is adapted to store at least two bits. The memory is adapted to store a program when the system powers up. The controller is adapted to implement the program to provide instructions used to program and erase nonvolatile memory cells. A method embodiment comprises loading a program into memory upon powering up a memory system, and implementing the program using a controller, including programming and erasing multi-bit nonvolatile memory cells.

Abstract: A method for error detection during execution of a real-time operating system, wherein logically-identical instances of the real-time operating system are executed in parallel on a plurality of processor cores of a first processor in a shared virtualization environment. The hypervisor supervises the parallel execution of the instances, and during execution of a hardware access initiated by the instances, the data transmitted during the hardware access for each instance of the logically-identical instances is compared with each other by the hypervisor. In the event of a discrepancy between the transmitted data or in the event of a unilateral hardware access initiated by one of the instances, an error is deemed to be detected by the hypervisor.