Abstract: An actuator control device configured to control an operation of an actuator includes: a detection unit and a restriction unit. The detection unit is configured to monitor a battery voltage and to detect a descent time which is a drop time of the battery voltage from a preset first voltage to a second voltage lower than the first voltage. The restriction unit imposes, when the descent time is equal to or longer than a time threshold, a stronger restriction on an operation of the actuator than an occasion of when the descent time is less than the time threshold.

Abstract: A power converter includes a voltage conversion unit that provides a first driving voltage at a first output electrode by converting a power supply voltage in response to a first control signal, the voltage conversion unit being configured to provide a second driving voltage at a second output electrode by converting the power supply voltage after a short detection period, the voltage conversion unit being configured to shut down in response to a third control signal, and a short detection unit that generates the third control signal by comparing a magnitude of a voltage of the second output electrode with a magnitude of a reference voltage during the short detection period.

Abstract: A memory system includes a memory device and a controller. The memory device is configured to supply a read voltage into a plurality of non-volatile memory cells and transfer values obtained from the plural non-volatile memory cells. The controller is coupled to the memory device via at least one channel. The controller adjusts a level of the read voltage based on a cell difference probability (CDP) calculated from the values when a read operation to the plurality of non-volatile memory cells fails.

Abstract: Apparatus and methods are disclosed, including a controller circuit, a volatile memory, a non-volatile memory, and a reset circuit, where the reset circuit is configured to receive a reset signal from a host device and actuate a timer circuit. The timer circuit, where the timer circuit is configured to cause a storage device to reset after a threshold time period. The reset circuit is further configured to actuate the controller circuit to write data stored in the volatile memory to the non-volatile memory before the storage device is reset.

Abstract: A power converter includes a voltage conversion unit that provides a first driving voltage at a first output electrode by converting a power supply voltage in response to a first control signal, the voltage conversion unit being configured to provide a second driving voltage at a second output electrode by converting the power supply voltage after a short detection period, the voltage conversion unit being configured to shut down in response to a third control signal, and a short detection unit that generates the third control signal by comparing a magnitude of a voltage of the second output electrode with a magnitude of a reference voltage during the short detection period.

Abstract: One or more configuration parameters for an object gateway instance are received at an interface to a provider network, the parameters including an identifier of a first object store of the provider network for which to cache objects in a first object cache of the object gateway instance and an indication of a data transfer mode that controls when objects written to the first object cache are written to the first object store. The one or more configuration parameters are stored in a data store of the provider network and sent to the object gateway instance. A read request that includes the identifier of the first object store and a first object identifier is received from the object gateway instance, and a first object associated with the first object identifier and stored in the first object store is sent to the object gateway instance.

Abstract: A test circuit includes a control circuit and a counting circuit. The control circuit is configured to control a charging operation and a discharging operation on a test node. The counting circuit is configured to generate counting information by performing a counting operation during a unit measurement interval.

Abstract: A method, comprising: detecting that a storage device is experiencing a failure, the storage device being part of a computing device; identifying a cooling fan that is associated with the storage device, the cooling fan being part of the computing device, the cooling fan being identified based on one or more data structures that map the cooling fan to the storage device; and increasing a speed of the cooling fan from a first speed level to a second speed level, the speed of the cooling fan being increased in response to detecting that the storage device is experiencing the failure, wherein the speed of the cooling fan is increased proactively.

Abstract: In one embodiment, a method for preventing an operable state in a plurality of components of an information handling system in response to a reset of a power supply includes: receiving, by an embedded controller of the information handling system, power from the power supply after the reset of the power supply; causing a platform controller hub of the information handling system to receive the power from the power supply; receiving a signal from the platform controller hub indicating that the plurality of components should be placed in the operable state from an inoperable state; determining that the reset of the power supply was caused by the power supply being previously removed from the information handling system; determining that a position of a lid of the information handling system is in a closed position; and causing the plurality of components to remain in the inoperable state.

Abstract: A system and method for MIMO communications is provided. A method includes receiving a data block of P matrices from a transmitter, and determining if operating conditions are met. The method also includes if operating conditions are not met, computing a test position, selecting a codeword based on the test position, and computing a metric. The metric may then be compared with an error radius to determine a validity of the codeword. If the codeword is invalid, another codeword is selected. If the codeword is valid, then the codeword is stored if all matrices have been evaluated, else another matrix is selected for evaluation. If matrices earlier in the data block have untested codewords while all codewords for a matrix being evaluated have been tested, backtracking may be performed. After the codewords for the data block have been found, the stored data may be outputted and processed.

Abstract: Memory devices and/or error control codes (ECC) decoding methods may be provided. A memory device may include a memory cell array, and a decoder to perform hard decision decoding of first data read from the memory cell array by a first read scheme, and to generate output data and error information of the output data. The memory device may also include and a control unit to determine an error rate of the output data based on the error information, and to determine whether to transmit an additional read command for soft decision decoding to the memory cell array based on the error rate. An ECC decoding time may be reduced through such a memory device.

Abstract: A detecting method for the consistency of a link scrambling configuration, comprises: setting the first threshold of the data packet error rate received by the receiving end; when the receiving end receiving date from the link, counting the received data packet error rate; judging whether the error rate is above the set first threshold; if yes, determining that the link scrambling configurations between transmitting end and receiving end are inconsistent; if not, determining that the link scrambling configurations between transmitting end and receiving end are consistent. The invention provides that the ports could detect the consistency of the link scrambling configuration automatically when configuring the link scrambling code, thereby enables the receive device to adjust the configuration of scrambling code to achieve the consistency of scrambling code between both ends of the link, and improves the maintenance of devices.

Abstract: A voltage identifier (VID) sorting system is provided that optimizes processor power and operating voltage guardband at a constant processor frequency. The VID sorting system determines a voltage versus current curve for the processor. The VID sorting system then uses the voltage versus current characteristics to calculate the power for each VID to determine an acceptable range of VIDs within the maximum power criteria. The VID sorting system then tests VIDs in the range and selects a VID from the range to optimize for minimum power and/or maximum voltage guardband at a constant processor frequency.

Abstract: A reproducing device performs error correction, detects a medium defect at an early stage and performs erasure correction. A reproducing device having an error correction circuit is provided with a medium defect detector. The medium defect detector computes a moving average value of the reproducing signal, slices this moving average value with a threshold Th, and detects a defect. A continuous amplitude drop can be detected accurately compared with a simple threshold detection, and deterioration of error correction capability due to a detection error can be suppressed. Also a defect can be detected in a previous stage of the error correction decoding, so a defect can be detected at an early stage, and erasure can be corrected at an early stage during error correction.