Abstract: A watchdog timer device according to one or more embodiments may include a mode setting unit that sets a first mode or a second mode. In the first mode, the watchdog timer device monitors an operation state of a monitored device and generates an interrupt signal to cause the monitored device to perform recovery processing at a first timeout. In the second mode, the watchdog timer device monitors the recovery processing and generates a reset signal to restart the monitored device at a second timeout. The watchdog timer device uses different logic to execute determining the first timeout in the first mode and determining the second timeout in the second mode.

Abstract: A method for configuring a storage circuit, including: writing data via an input line into the storage circuit by a software write access; writing a bit-wise inverted form of the data via the input line into the storage circuit by a subsequent software write access; and generating an error signal if a comparison based on the written data and the written bit-wise inverted form of the data indicates a storage circuit configuration error, wherein the storage circuit permits hardware read access and lacks software read access.

Abstract: A method for the secured storing of a data element in an external memory, which is connected to a microcontroller via an interface module, which is configured to calculate memory addresses for data to be stored and for error correction values. The method includes receiving the data element to be stored by the interface module, a calculation by the interface module of a memory address in the external memory for the data element to be stored, and a writing, starting at the memory address, of the data element and of the error correction value via the interface module into the external memory, the error correction value immediately following the data element being written and the writing taking place within one addressing phase. A corresponding interface module, a corresponding microcontroller, and a corresponding control unit are also described.

Abstract: A semiconductor device includes first and second memory regions spaced apart from each other and a fail information storage region disposed between the first and second memory regions. A parity including error information on data is stored in a first parity region of the fail information storage region while a write operation is applied to the first memory region. The parity is stored in a second parity region of the fail information storage region while the write operation is applied to the second memory region. An error of the data is corrected by the parity stored in the first parity region while a read operation is applied to the first memory region. The error of the data is corrected by the parity stored in the second parity region while the read operation is applied to the second memory region.

Abstract: An apparatus comprising an integrated circuit configured to accept a plurality of operands; multiply the operands producing an result in a first binary format; and distribute the result in the first binary format over a plurality of data units in a second binary format, each unit having W bits with k>0 most significant bits set to zero.

Abstract: Techniques for decoding levels in non-volatile memory. A level of a cell in a multi-bit non-volatile memory is read. A minimum of Log-Likelihood Ratio (LLR) and a modified LLR to decode the level, wherein the modified LLR is a function of a misplacement probability is used. A value corresponding the decoded level is written to a volatile memory.

Abstract: An information processing service is allowed to be immediately recovered from failure without clustering information apparatuses that provide an information processing service.

Abstract: Methods of writing data to and reading data from memory devices and systems for writing and reading data are disclosed. In a particular embodiment, a method includes writing data bits a first time into a memory. Auxiliary parity bits are written in the memory, where the auxiliary parity bits are computed based on the data bits. Subsequent to writing the data bits a first time and writing the auxiliary parity bits, the data bits are written a second time into the memory. Writing the data bits the first time and writing the data bits the second time are directed to one or more storage elements at a common physical address in the memory. Subsequent to writing the data bits the second time, the auxiliary parity bits are discarded while maintaining the data bits in the memory.

Abstract: An apparatus comprising an integrated circuit configured to accept a plurality of operands; multiply the operands producing an result in a first binary format; and distribute the result in the first binary format over a plurality of data units in a second binary format, each unit having W bits with k>0 most significant bits set to zero.

Abstract: A system for automatic lane failover includes a first device coupled to a second device via a serial communication link having a plurality of a communication lanes. The devices may communicate by operating the link in a normal mode and a degraded mode. During normal mode operation, the devices may send frames of information to each other via the serial communication link. Each frame of information may include a number of data bits and a number of error protection bits. In response to either device detecting a failure of one or more of the communication lanes, the first device may cause the serial communication link to operate in a degraded mode by removing the one or more failed communication lanes. In addition, each device may reformat and send the frame of information on the remaining communication lanes with fewer data bits and the same number of error protection bits.

Abstract: A data processing system has cache circuitry having a plurality of ways. Mirroring control logic indicates a mirrored way pair and a non-mirrored way of the plurality of ways. The mirrored way pair has first and second ways wherein the second way is configured to store cache data fields redundant to cache data fields of the first way. In one form, comparison logic, in response to an address hitting in the first way or the second way within the mirrored way pair, performs a bit comparison between cache data from the first way addressed by an index portion of the address with cache data from the second way addressed by the index portion of the address to provide a bit parity error signal. In another form, allocation logic uses a portion of the address and line locking information to determine whether a mirrored or non-mirrored way is selected for allocation.

Abstract: Device and method for controlling caches, comprising a decoder configured to decode additional information of datasets retrievable from a memory, wherein the decoded additional information is configured to control whether particular ones of the datasets are to be stored in a cache.

Abstract: An apparatus and a method for adapting data in a communications system to be transmitted from a sender to a receiver, to a transport unit of a predefined size involve representing said data as a combination of bits over a finite field, wherein said data comprises of an information part and a control part; adapting said represented data to fit said predefined size of said transport unit, by expressing both said information and control parts with bits, wherein said bits are less in number that said represented combination of bits and a number of removed bits is known to said receiver, said removed bits comprise of bits from both said information and control parts.

Abstract: A communication interface device, system, method, and design structure for bit shadowing in a memory system are provided. The communication interface device includes shadow selection logic to select a driver bit position as a shadowed driver value, and line drivers to transmit data for the selected driver bit position and the shadowed driver value on separate link segments of a bus. The communication interface device also includes shadow compare logic to compare a selected received value with a shadowed received value from the bus and identify a miscompare in response to a mismatch of the compare, and shadow counters to count a rate of the miscompare relative to a bus error rate over a period of time. A defective link segment is identified in response to the rate of the miscompare within a predefined threshold of the bus error rate.

Abstract: The present invention produces a low-cost reliable non-volatile memory with multiple write cycles. The memory circuit trades full configurability for increased reliability and decreased cost by providing a limited number of write or rewrite cycles utilizing an indirectly accessible register set that writes data into fully configurable memory. The circuit is useful for both providing upgrade capability to electronic computational systems and data robustness to logic storage systems. Less configurable non-volatile memory (NVM) block 201 is utilized in tandem with directly accessible fully configurable memory block 207. Arbiter 206 implements the redundant addressing that enables the multiple write cycle NVM functionality. Each block of less configurable memory contains an address segment 203 and a data segment 204. Address segment 203 refers to a specific cell in directly accessible memory 209.

Abstract: A first value from a set of bit cells of a sector of a non-volatile memory device is sensed based on a first read reference. A second value from the set of bit cells is sensed based on a second read reference different than the first read reference. A third read reference for a first subsequent access to the sector of the non-volatile memory device is determined based on at least one of the first read reference and the second read reference in response to determining a first error code condition associated with the first value and a second error code condition associated with the second value represent different error code conditions.

Abstract: A method is disclosed for determining a configuration for a computer tomograph for the purpose of error diagnosis, a module, a computer tomograph and a system of appropriate design. The computer tomograph includes a multiplicity of detector modules. In at least one embodiment, a respective detector module is designed to have an identification device which is intended to provide a signature, the signature being uniquely associated with the respective module. The detector module transmits the measurement data it captures and its signature. The digital, electronic signature allows remote maintenance of the computer tomograph.

Abstract: A method of the invention uses an outer code that is a concatenation of code words generated by a parity check encoder. The outer code word is then permuted by an interleaver. The high rate coding provides good performance with a simple structure. According to the method, an odd parity check bit is generated for each data word of received systematic dates. Code words are formed by adding a generated parity bit to each data word. Groups of code words are permuted to form encoded input for transmission in a communication channel. The invention further includes encoding to maintain a runlength-limiting (RLL) constraint at the channel input. Interleaved runlength encoded system data is used to generate error code bits, which may be parity bits. Insertion of error code bits in the system data at the channel input is controlled to limit the number of error code bits inserted per a defined grouping of system bits.