Abstract: A winglet is configured to be removably coupled to a missile launcher that is secured to a wing of an aircraft. The winglet includes an airfoil, and one or more couplers configured to removably couple to a coupling interface of the missile launcher.

Abstract: Systems and methods are provided for arbitrating sensor and actuator signals in various devices. One system includes input/output (I/O) circuitry, redundant computation circuits coupled to the I/O circuitry, and an arbitration circuit coupled between the I/O circuitry and the redundant computation circuits. The I/O circuitry is configured to be coupled to multiple non-redundant systems, and the redundant computation circuits are configured to be coupled to one of multiple system buses. One such device is an aircraft including multiple non-redundant systems and a plurality of system buses that are configured to transmit redundant messages to the non-redundant systems.

Abstract: A method, computer readable medium, and system independently managing network applications within a network traffic management device communicating with networked clients and servers include monitoring with a network device a plurality of applications communicating over a plurality of direct memory access (DMA) channels established across a bus. The network device receives a request from a first application communicating over a first DMA channel in the plurality of DMA channels to restart the first DMA channel. In response to the request, the first DMA channel is disabled with the network device while allowing other executing applications in the plurality of applications to continue to communicate over other DMA channels in the plurality of DMA channels. A state of the first DMA channel is cleared independently from other DMA channels in the plurality of DMA channels, and communications for the first application over the first DMA channel are resumed with the network device.

Abstract: Embodiments of a hardware processor including a plurality of machine state registers (MSRs) are described. At least one of the MSRs includes an erroring logical processing (ELP) bit which when set, indicates that a particular thread executing on the hardware processor caused an error.

Abstract: Processors, microprocessors and logical block systems and methods, error detection systems and methods, and integrated circuits are disclosed. In an embodiment, a logic-based computing system includes a first processing core; a second processing core generated from the first processing core and including an inverted logical equivalent of the first processing core such that an output of the second processing core is a complement of an output of the first processing core; and comparator logic coupled to receive the outputs of the first and second processing cores as inputs and provide an error output if the output of the second processing core is not the complement of the output of the first processing core.

Abstract: Device for determining an error induced by a high-pass filter in a signal, including a unit (3) for calculating the error according to the formula: E(t)=Ve(t)?Vs(t)=2·?·Fc·??=t0t(Vs(?)? Vs(?))·d?+E(t0) with: E(t) the value of the error induced by the high-pass filter, as a function of the time variable t, ? the trigonometric constant, Fc the cutoff frequency of the high-pass filter, t0 the initial instant, ? integration variable, Ve the signal input to the high-pass filter, Vs the signal output by the high-pass filter, Vs the mean value of the signal Vs. A method of correcting the error induced is also presented and applicable to the error correction of a piezoelectric pressure sensor.

Abstract: A microprocessor includes a bus interface unit that interfaces the microprocessor to a bus that includes a signal that, when asserted, instructs all bus agents to refrain from initiating bus transactions. Microcode causes the bus interface unit to assert the signal in response to detecting an event and resets the microprocessor, but does not reset a portion of the bus interface unit that asserts the signal on the bus. After the reset, the microcode causes the bus interface unit to deassert the signal on the bus. Additionally, the microcode sets a flag and saves the microprocessor state to memory before resetting itself, but does not reset the interrupt controller. After the reset, the microcode reloads the state of the microprocessor from the memory. However, if the microcode determines that the flag is set, it forgoes reloading the state of the interrupt controller.

Abstract: A system recovery method and an apparatus supporting the same are disclosed. A software image is downloaded, and a system is loaded with the downloaded software image, and the system is recovered by a software image used before the updating, if the system loading fails.

Abstract: The present invention provides a CEC communications device which eliminates a troublesome process to solve the CEC-related communication malfunction when the CEC communications device detects a CEC-related communication malfunction caused by a software malfunction and improves serviceability of the CEC communications by automatically resetting the CEC to execute a CEC communication recovery. In the CEC communications device, when a CEC communications line monitoring unit detects a CEC-related communication malfunction caused by a software malfunction, a CEC control unit determines a reset order of a CEC appliance found on a CEC network, and notifies the CEC resetting unit of a CEC resetting request. The CEC resetting unit resets the CEC of a CEC appliance found on the CEC network via an HDMI line (DDC in FIG. 1) other than the CEC to recover the CEC communications.

Abstract: A method and system of calibrating estimates for software projects is provided. More particularly, a method and system is provided to continuously provide calibration estimation and improvement options across a software integration life cycle. The method is implemented in a computer infrastructure having computer executable code tangibly embodied on a computer readable storage medium having programming instructions operable to: compare actual data associated with a phase of a project to expected results used to develop a strategic development plan for the project; and calibrate efforts in the strategic development plan for future activities of the project based on the actual data.

Abstract: A method, system and computer program product for enabling a register file to recover from detection of a parity error. A first register file and a second register file are associated with a parallel file structure. When the parity error is detected, the system determines whether the first register file or second register file is associated with the parity error. The register file determined to have the parity error is associated with an offending register and a non-offending register is associated with the “good” register file. Subsequent to the detection of the parity error, the system executes a repair sequence, whereby the register file associated with the offending register receives data from the register file associated with the non-offending register. The offending register file recovers from the parity error with or without the use of a parity interrupt.

Abstract: Method, system and computer program product embodiments for, in an input/output (I/O) link handling complex instruction chains, a messaging scheme incorporating a method of error recovery between an initiator processor and a receiver processor, are provided. An operation initiation message is been sent from the initiator processor to the receiver processor for the receiver processor to begin work on an operation. If determined to be necessary, a terminate operation message is sent from the initiator processor to the receiver processor. The initiator processor withholds sending additional messages for the operation until a terminate operation response message is received. Once the terminate operation message is received, outstanding messages in process are flushed from the receiver processor. The receiver processor withholds sending additional messages to the initiator processor as the outstanding messages are completed.

Abstract: An information processing system includes I/O devices, I/O switches each of which is coupled to the I/O devices, multiple server apparatuses which are coupled to the I/O switch and with which a cluster can be constructed, and a management server. In the system, a management server is that: stores an identifier and a coupling port ID of the I/O switch to which any of the server apparatuses and any of the I/O devices are coupled; stores information as to whether or not each of the I/O devices can use loopback function for the heart beat signal; selects one of the I/O devices available for the loopback function in constructing the cluster between the server apparatuses; generates a heart beat path using the selected I/O device as a loopback point; and performs settings on the I/O device.

Abstract: A data processing apparatus is provided in which a processing unit, by means of a read access request, accesses a storage device which stores data values and error data associated with those data values. When the processing unit accesses a data value in the storage device, error detection circuitry detects if an error is present in that data value and, if necessary, error correction circuitry corrects the read data value. An error cache having at least one entry stores corrected replacement data values, a corrected data value being allocated into an entry of the error cache for every corrected data value that is generated, and the read access request is re-performed. Replacement data values are read from the error cache in preference to data values stored in the storage device. This ensures that the retry mechanism will succeed irrespective of whether the error was a soft error or a hard error.

Abstract: Provided are a method, system, and program for handling a fabric failure. A module intercepts a signal indicating a failure of a path in a fabric providing a connection to a shared device. The module generates an interrupt to a device driver in an operating system providing an interface to the shared device that is inaccessible due to the path failure. The device driver requests information from the module on a status of a plurality of devices that are not accessible due to the path failure and receives information indicating the inaccessible device. The device driver reconfigures to discontinue use of the inaccessible device.

Abstract: A redundancy system that can perform synchronization even if a failure occurs to an application. According to the redundancy system of the present invention, a synchronization data memory area, a management bit map table having a flag created for each segment of the synchronization data memory area, and a management memory area for storing the starting address of the segment are set in each device. In the service application process, a service is performed using one or more segments, a flag corresponding to the segment is set, and synchronization information is written to the management memory each time the segment is written or overwritten. In the read process, each flag in the management bit map table is checked, and if a flag being set exists, the synchronization data is read from the segment corresponding to the synchronization information stored in the management memory, and the flag is reset.

Abstract: A method, computer program product and system that establishes and maintains a business continuity policy in a server consolidation environment. Business continuity is ensured by enabling high availability of applications. When an application is started, restarted upon failure, or moved due to an overload situation, a system is selected best fulfilling the requirements for running the application. These requirements can include application requirements, such as an amount of available capacity to handle the load that will be placed on the system by the application. These requirements can further include system requirements, such as honoring a system limit of a number of applications that can be run on a particular system. Respective priorities of applications can be used to determine whether a lower-priority application can be moved to free resources for running a higher-priority application.

Abstract: System and method for managing data fail-over for a computing system comprising a plurality of computers, e.g., computer blades, coupled through a network. A fail-over condition may indicate a component failure, an imminent failure, and/or a need to modify or replace some aspect of a computer. Computers in the system may back up their information to other computers in the system. If a fail-over condition is detected on a first computer, a replacement computer may be loaded with the information from the first computer, optionally from a backup copy stored on another computer (or distributed across multiple computers), and the first computer's peripheral devices (human interface) switched over to the replacement computer. The method may be used to replace a single computer, swap two computers, and/or perform a cascade move among multiple computers, and may be performed automatically in response to the fail-over condition, or initiated by a system administrator.