Error Or Fault Processing Without Redundancy, I.e., By Taking Additional Measures To Deal With The Error/fault (epo) Patents (Class 714/E11.022)
  • Publication number: 20110320874
    Abstract: A method for estimating a candidate cause in a failure occurred in an information processing apparatus by a computer, the method includes retrieving, by the computer, a first set of incident information from a data storage region on the basis of failure symptom data which is set on the computer, the data storage region storing incident information, each piece of the incident information including failure symptom data, first cause data of a positive judgment result of a cause in the failure, and second cause data of a negative judgment result of the cause in the failure, each of the first set including the failure symptom data identical to the set failure symptom data.
    Type: Application
    Filed: December 20, 2010
    Publication date: December 29, 2011
    Applicant: FUJITSU LIMITED
    Inventors: Kuniaki Shimada, Yukihiro Watanabe, Yasuhide Matsumoto
  • Publication number: 20110302463
    Abstract: In one embodiment, a method includes selecting a subset of rays from a set of all rays to use in an error calculation for a constrained conjugate gradient minimization problem, calculating an approximate error using the subset of rays, and calculating a minimum in a conjugate gradient direction based on the approximate error. In another embodiment, a system includes a processor for executing logic, logic for selecting a subset of rays from a set of all rays to use in an error calculation for a constrained conjugate gradient minimization problem, logic for calculating an approximate error using the subset of rays, and logic for calculating a minimum in a conjugate gradient direction based on the approximate error. In other embodiments, computer program products, methods, and systems are described capable of using approximate error in constrained conjugate gradient minimization problems.
    Type: Application
    Filed: June 7, 2010
    Publication date: December 8, 2011
    Inventor: Jeffrey S. Kallman
  • Publication number: 20110185229
    Abstract: A computer implemented fault diagnosis method employing both probabilistic models and statistical learning that diagnoses faults using probabilities and time windows learned during the actual operation of a system being monitored. In a preferred embodiment, the method maintains for each possible root cause fault an a-priori probability that the fault will appear in a time window of specified length as well as maintaining—for each possible resulting symptom(s)—probabilities that the symptom(s) will appear in a time window containing the fault and probabilities that the alarm will not appear in a time window containing the fault. Consequently, the method according to the present invention may advantageously determine—at any time—the probability that a fault has occurred, and report faults which are sufficiently likely to have occurred. These probabilities are updated based upon past time windows in which we have determined fault(s) and their cause(s).
    Type: Application
    Filed: January 27, 2010
    Publication date: July 28, 2011
    Inventors: George Lapiotis, David Shallcross
  • Publication number: 20110029819
    Abstract: There is provided a system and method of providing program tracking information. An exemplary method comprises compiling a program into a plurality of instruction bundles. The exemplary method also comprises placing an instruction to store program tracking information in a local path table or a global path table into at least one of the plurality of instruction bundles.
    Type: Application
    Filed: July 31, 2009
    Publication date: February 3, 2011
    Inventors: Virendra Kumar Mehta, Xiaohua Zhang
  • Publication number: 20110010577
    Abstract: A method for reactivating at least one media transfer protocol-compatible (MTP-compatible) device when an unrecoverable error occurs includes: temporarily storing a transaction ID of a latest operation performed on the MTP-compatible device; and selectively communicating with the MTP-compatible device by utilizing the transaction ID when an unrecoverable error of the MTP-compatible device occurs. An associated host for reactivating at least one MTP-compatible device when an unrecoverable error occurs includes a storage unit and a processing circuit. The storage unit is arranged to temporarily store a transaction ID of a latest operation performed on the MTP-compatible device. In addition, the processing circuit is arranged to selectively communicate with the MTP-compatible device by utilizing the transaction ID when an unrecoverable error of the MTP-compatible device occurs.
    Type: Application
    Filed: August 20, 2009
    Publication date: January 13, 2011
    Inventor: Jian Zhang
  • Publication number: 20100332942
    Abstract: A memory controller 4 for a NAND memory array 2 includes error detecting circuitry having input circuitry 6, fast zero-error detecting circuitry 10, fast-path error correcting circuitry 16, 24, slow-path error correcting circuitry 18, 22 and fast-bad-block detecting circuitry 28.
    Type: Application
    Filed: September 10, 2008
    Publication date: December 30, 2010
    Applicant: ARM Limited
    Inventors: Martinus Cornelis Wezelenburg, Thomas Kelshaw Conway, Dominic Hugo Symes
  • Publication number: 20100293532
    Abstract: In one embodiment, the invention is a method and apparatus for failure recovery for stream processing applications. One embodiment of a method for providing a failure recovery mechanism for a stream processing application includes receiving source code for the stream processing application, wherein the source code defines a fault tolerance policy for each of the components of the stream processing application, and wherein respective fault tolerance policies defined for at least two of the plurality of components are different, generating a sequence of instructions for converting the state(s) of the component(s) into a checkpoint file comprising a sequence of storable bits on a periodic basis, according to a frequency defined in the fault tolerance policy, initiating execution of the stream processing application, and storing the checkpoint file, during execution of the stream processing application, at a location that is accessible after failure recovery.
    Type: Application
    Filed: May 13, 2009
    Publication date: November 18, 2010
    Inventors: Henrique Andrade, Bugra Gedik, Gabriela Jacques da Silva, Kun-Lung Wu
  • Publication number: 20100211815
    Abstract: A system and method for modifying execution scripts associated with a job scheduler may include monitoring for the execution of a task to determine when the task has failed. Details of the failed task may be identified and used to attempt recovery from the task failure. After initiating any recovery tasks, execution of the recovery tasks may be monitored, and one or more supplementary recovery tasks may be identified and executed, or the original task may be rerun at an appropriate execution point based on the initial point of failure. Thus, when a task has failed, an iterative process may begin where various effects of the failed task are attempted to be rolled back, and depending on the success of the rollback, the initial task can be rerun at the point of failure, or further recovery tasks may be executed.
    Type: Application
    Filed: January 11, 2010
    Publication date: August 19, 2010
    Applicant: Computer Associates Think, Inc.
    Inventors: Serguei Mankovskii, Colin Banger, Jody Steele, Tomas Gray
  • Publication number: 20100195499
    Abstract: In one example embodiment, an apparatus is provided and includes a network device that identifies a data type of a payload of a data packet to be transmitted. The network device adapts one or more of data transmission rates according to the data type that was identified. A control portion of the data packet is used to identify the data type. In more specific embodiments, the data transmission rates are controlled by one or more link layer configuration parameters, which are controlled according to the identified data type of the data packet. In still other embodiments, the network device identifies data packets with payloads relating to Intra-coded picture frames (I-frames), Predicted pictures frames (P-frames), and Bi-directional predictive pictures frames (B-frames).
    Type: Application
    Filed: February 5, 2009
    Publication date: August 5, 2010
    Inventors: Siddhartha Dattagupta, Allen J. Huotari
  • Publication number: 20100185697
    Abstract: A plurality of catalogs are maintained, and wherein each catalog of the plurality of catalogs includes data sets and attributes of the data sets. An indication that a new data set is to be defined is received. A selected catalog is determined from the plurality of catalogs, wherein the selected catalog is suitable for including the new data set and attributes of the new data set. An entry that indicates a data set name corresponding to the new data set and an index to the selected catalog is inserted in a group table.
    Type: Application
    Filed: January 22, 2009
    Publication date: July 22, 2010
    Inventors: Douglas Lee Lehr, Franklin Emmert Mccune, David Charles Reed, Max Douglas Smith
  • Publication number: 20100138701
    Abstract: A system, method, and apparatus for retrieving trouble codes from an equipment under diagnosis and retrieving only relevant diagnostic information relative to the returned codes from one or more remote diagnostic libraries. An electronic diagnostic library contains diagnostic vehicle information tagged with trouble code identification ID's at a first location, and a diagnostic tool at a second location requests only relevant diagnostic information from the electronic library that is tagged with trouble code identification ID's corresponding to the retrieved trouble codes and information identifying the equipment under diagnosis. The diagnostic tool receives the specific diagnostic vehicle information at the first location and may store the specific vehicle information locally prior to displaying an index to the information to a repair technician.
    Type: Application
    Filed: December 3, 2008
    Publication date: June 3, 2010
    Applicant: Snap-on Incorporated
    Inventor: David Costantino
  • Publication number: 20100131830
    Abstract: A system and method are provided for framing messages in a forward error correction (FEC) structure for data streams encoded with redundant signal conditioning information. The method accepts signal conditioning-encoded words at a first bit rate, and eliminates redundant information in the signal conditioning-encoded words, creating N reduced-bit words of k bits. The k-bit words are mapped into a payload field of N*(k/p) p-bit words. Overhead (OH) and FEC parity fields are generated, and a frame is created including the OH field, payload field, and FEC parity field. The bit values in the frame are then pseudorandomly scrambled and the scrambled frame is transmitted at the first bit rate. A system and method are also presented for recovering the signal conditioning-encoded words from an FEC frame.
    Type: Application
    Filed: November 24, 2008
    Publication date: May 27, 2010
    Inventors: Matthew Brown, Sean Campeau
  • Publication number: 20100122116
    Abstract: A mechanism is provided for internally controlling and enhancing advanced test and characterization in a multiple core microprocessor. To decrease the time needed to test a multiple core chip, the mechanism uses micro-architectural support that allows one core, a control core, to run a functional program to test the other cores. Any core on the chip can be designated to be the control core as long as it has already been tested for functionality at one safe frequency and voltage operating point. An external testing device loads a small program into the control core's dedicated memory. The program functionally running on the control core uses micro-architectural support for functional scan and external scan communication to independently test the other cores while adjusting the frequencies and/or voltages of the other cores until failure. The control core may independently test the other cores by starting, stopping, and determining pass/fail results.
    Type: Application
    Filed: November 12, 2008
    Publication date: May 13, 2010
    Applicant: International Business Machines Corporation
    Inventors: Michael S. Floyd, Robert B. Gass, Norman K. James
  • Publication number: 20100083072
    Abstract: Methods and corresponding systems in an interleaver include loading K symbol data, in a linear order, into a matrix memory having (R·C) storage locations corresponding R rows and C columns. A sequence of interleaved addresses is produced for reading the K symbol data in an interleaved order from the matrix memory. Next, (R·C)?K interleaved addresses are queued in a first-in-first-out (FIFO) memory. After queuing (R·C)?K interleaved addresses in the FIFO memory, symbol data is output using the interleaved addresses in the FIFO memory to address and output the symbol data in the matrix memory in the interleaved order. The FIFO memory can contain at least 234 memory locations.
    Type: Application
    Filed: September 30, 2008
    Publication date: April 1, 2010
    Inventors: Mohit K. Prasad, Clark H. Jarvis
  • Publication number: 20100074173
    Abstract: The present disclosure generally pertains to systems and methods for updating script images in wireless sensor networks. In one exemplary embodiment, a system has logic that is configured to display a list of nodes of a wireless sensor network. The logic is further configured to display a script source of a first script image stored at one of the nodes in response to a selection of the one node from the displayed list of nodes. The logic is also configured to modify the script source based on user input and to convert the modified script source to a second script image. The logic is configured to transmit at least one remote procedure call through the wireless sensor network to the one node. The one node is configured to write the second script image in memory of the one node in response to the at least one remote procedure call.
    Type: Application
    Filed: May 8, 2009
    Publication date: March 25, 2010
    Inventor: David B. Ewing
  • Publication number: 20100077261
    Abstract: The present invention relates to a realistic service and system using a five senses integrated interface, and more particularly, to an apparatus and method for encoding the five senses and a system and method for providing realistic service using a five senses integrated interface, to allow a user to select a product to sensorially experience through an integrated interface in a remote location, which includes a integration recognizer detecting data selected by the user and recognizing an object, and transmitting five senses data of the object through a network, a five senses data analyzer receiving a five senses data packet including the five senses data of the object through the network, and extracting and analyzing the five senses data packet in terms of data on each of the five senses, and a five senses integration representer representing five senses using the data on each of the five senses.
    Type: Application
    Filed: December 3, 2007
    Publication date: March 25, 2010
    Inventors: Young Giu Jung, Mun Sung Han, Jun Seok Park
  • Publication number: 20100064194
    Abstract: A remote communication method of a network includes a main controller and a plurality of control units, wherein each control unit is serially connected to the main controller and the control unit at next stage through a transmission terminal and a transmitter. Each control unit receives the data sent from the main controller and identifies the received data as one of a first, a second and a third packet. If it is the first packet and the main controller attempts to read data from each control unit, a switch in the control unit is turned on and a response data is transmitted to the main controller. If it is the second packet and a connection index is equal to a target unit address, then data is written to a corresponding single control unit. If it is the third packet and a target unit address is zero, data is written to all control units.
    Type: Application
    Filed: October 27, 2008
    Publication date: March 11, 2010
    Inventor: Shu-Chun LIAO
  • Publication number: 20090292971
    Abstract: Techniques are described that include reading a portion of a memory and determining whether there is any uncorrectable codeword. Due to time varying errors present during a read operation, the uncorrectable codeword may become read as a correctable codeword at another time. If any uncorrectable codeword is present in the portion, the portion can be re-read to determine whether any uncorrectable codeword is instead correctable. Prior to re-reading the portion, a reference level used to determine whether a logic zero or one is stored can be adjusted. Adjusting the reference level can allow an uncorrectable codeword to become a correctable codeword.
    Type: Application
    Filed: October 22, 2008
    Publication date: November 26, 2009
    Inventors: Chun Fung Man, Jonathan Schmidt, Scott Nelson
  • Publication number: 20090292947
    Abstract: Techniques for maintaining a cascading index are provided. In one approach, one or more branch node compression techniques are applied to the main index of a cascading index. In an approach, a Bloom filter is generated and associated with, e.g., a branch node in the main index. The Bloom filter is used to determine whether, without accessing any leaf blocks, a particular key value exists, e.g., in leaf blocks associated with the branch node. In an approach, a new redo record is generated in response to a merge operation between two levels of the cascading index. The new redo record comprises (a) one or more addresses of blocks that are affected by the merge operation, (b) data is that being “pushed down” to a lower level of the cascading index, and (c) one or more addresses of blocks that are written to disk storage as a result of the merge operation.
    Type: Application
    Filed: May 20, 2009
    Publication date: November 26, 2009
    Inventors: Amit Ganesh, Juan R. Loaiza, Krishna Kunchithapadam
  • Publication number: 20090228766
    Abstract: A method includes estimating quadrature amplitude modulated QAM symbols in an LDPC encoded OFDM signal for transmission, performing channel estimation by training sequence to determine channel coefficients in reception of the LDPC encoded OFDM signal; and obtaining channel information detection and decoding of the LDPC encoded signal.
    Type: Application
    Filed: March 6, 2008
    Publication date: September 10, 2009
    Inventors: Ivan Djordjevic, Ting Wang, Lei Xu, Milorad Cvijetic
  • Publication number: 20090217135
    Abstract: A method for address generation checking including receiving a starting memory address for a data, an ending memory address for the data, a length value of the data, and an address wrap indicator value that indicates if the data wraps from an end of a memory block to a start of the memory block, determining whether the ending memory address is equal to a sum of the starting memory address added to a difference of the length value to the address wrap indicator value, and transmitting an error signal that indicates an error occurred in a generation of the starting memory address or the ending memory address if the ending memory address is not equal to the sum.
    Type: Application
    Filed: February 25, 2008
    Publication date: August 27, 2009
    Inventors: Fadi Y. Busaba, Bruce C. Giamei
  • Publication number: 20090119566
    Abstract: Provided is a transmitter for continuously and sequentially transmitting data with a variable unit for playback. The transmitter includes an obtaining section, a buffer, a computing section and a transmitting section. The obtaining section sequentially obtains segment data of the data to be transmitted. The buffer stores an error correction code to correct an error caused in the data by transmission. The computing section computes, every time newly obtained segment data reaches a predetermined size, XOR of the error correction code already stored in the buffer and the newly obtained segment data, and then updates the error correction code with the computed XOR. The transmitting section sequentially transmits the obtained segment data, as well as reads from the buffer and transmits the updated error correction code every time the computing section computes XOR for data in a size corresponding to the unit for playback.
    Type: Application
    Filed: November 5, 2008
    Publication date: May 7, 2009
    Inventors: Toshiro Hiromitsu, Seiichi Idei, Kazuaki Numano, Yasushi Tsukamoto
  • Publication number: 20090113271
    Abstract: A method and apparatus for parallel structured Latin square interleaving in a communication system are provided. The method includes dividing input information bits into sub-blocks according to a parallel processing order, generating a first Latin square matrix or a second Latin square matrix by comparing the parallel processing order with a predetermined threshold, and interleaving by reading out the information bits divided into the sub-blocks according to the generated Latin square matrix.
    Type: Application
    Filed: October 30, 2008
    Publication date: April 30, 2009
    Inventors: Seul-Ki Bae, Seung-Hee Han, Jong-Hyeuk Lee, Hong-Yeop Song, Dae-Son Kim, Joon-Sung Kim
  • Publication number: 20090102976
    Abstract: This method is for processing data frames (Fi) received over a communication channel, each data frame (Fi) comprising a data section (Si) for forming part of a data table and location information (Mi) associated with the data section and designating a location of said section within the data table. The data table and a metadata table (MT) are built and stored as the data frames are received, to be made available to a host processor (2). The method comprises the following steps for each received data frame: —buffering (10, 12) the data section of the received frame and the associated location information; —determining (14) an address for the data section in a table memory (8) based on the location information; —writing the data section at the determined address into the table memory; and—writing an entry of a metadata table, wherein said entry comprises the location information.
    Type: Application
    Filed: March 6, 2007
    Publication date: April 23, 2009
    Inventors: Henri Fallon, Stephane De Marchi
  • Publication number: 20090106630
    Abstract: In the field of coding/decoding in telecommunications networks, an error correcting decoder and associated decoding method are adapted to a mesh network. In particular, the system for the decoding of a plurality of coded copies of a data word includes at least a first decoding stage with: a plurality of soft decision decoders, each decoder being arranged for decoding a coded copy received as decoder input, and a graph-based decoder comprising a plurality of nodes, each node of said graph-based decoder receiving the soft output value from a corresponding decoder and the graph-based decoder determining a decoding value of said data word on the basis of said soft output values.
    Type: Application
    Filed: October 17, 2008
    Publication date: April 23, 2009
    Inventors: Philippe Le Bars, Pierre Berthet
  • Publication number: 20090077419
    Abstract: A system and computer program product for monitoring a data processing system is proposed. The system and computer program product involve the measuring of state parameters of the system. Indicators of the performance of the system are then inferred from the state parameters by applying fuzzy-logic rules. The proposed solution is based on the idea of estimating a trust value, based on the effectiveness of the corrective actions. If the previous corrective actions prove to be effective than the trust value is enhanced and the system is allowed a higher level of autonomy. Otherwise the intervention of an operator might be invoked.
    Type: Application
    Filed: November 5, 2008
    Publication date: March 19, 2009
    Applicant: International Business Machines Corporation
    Inventors: Andrea Di Palma, Antonio Perrone
  • Publication number: 20090077432
    Abstract: Disclosed is a semiconductor memory device capable of arbitrarily setting an upper limit of the number of error corrections during a test operation. The semiconductor memory device has a counter, a register, and a comparison circuit. The counter counts the number of error corrections. The register, when an upper limit setting signal (in the case shown in FIG. 1, an external upper limit fetch signal) is externally inputted to change the upper limit of the number of error corrections, changes the upper limit. The comparison circuit compares the number of error corrections with the changed upper limit.
    Type: Application
    Filed: November 18, 2008
    Publication date: March 19, 2009
    Applicant: FUJITSU LIMITED
    Inventors: Toshikazu Nakamura, Akira Kikutake, Kuninori Kawabata, Yasuhiro Onishi, Satoshi Eto
  • Publication number: 20090070656
    Abstract: A memory system includes: a memory controller including an error correction decoder. The error correction decoder includes: a demultiplexer adapted to receive data and demultiplex the data into a first set of data and a second set of data; first and second buffer memories for storing the first and second sets of data, respectively; an error detector; an error corrector; and a multiplexer adapted to multiplex the first set of data and the second set of data and to provide the multiplexed data to the error corrector. While the error corrector corrects errors in the first set of data, the error detector detects errors in the second set of data stored in the second buffer memory.
    Type: Application
    Filed: August 14, 2008
    Publication date: March 12, 2009
    Inventors: Nam Phil JO, Jun Jin KONG, Chan Ho YOON, Dong Hyuk CHAE, Kyoung Lae CHO
  • Publication number: 20090063908
    Abstract: Methods, systems, and products are disclosed for verifying the integrity of web server content. Communication with a server is initiated and content is retrieved that is specified by a Uniform Resource Locator. The content is parsed and searched for an error message. When the content contains linked content, then the linked content is parsed and also searched for the error message. The error message is logged to indicate an existence of a partial page error.
    Type: Application
    Filed: October 8, 2008
    Publication date: March 5, 2009
    Inventors: Karthiksundar Sankaran, Zakir Patrawala, Timothy A. Hill
  • Publication number: 20090055705
    Abstract: There are provided a method and apparatus for decoding Raptor code. The apparatus includes a decoder for decoding a sequence of packets representative of a sequence of encoding symbols. The decoder at least partially recovers at least some lost or corrupted packets of the sequence using Raptor code.
    Type: Application
    Filed: January 31, 2007
    Publication date: February 26, 2009
    Inventor: Wen Gao
  • Publication number: 20090024895
    Abstract: A system and method for transmission control by an access device in a wireless communication system including a plurality of receiving devices, including receiving, from a super ordinate device, first transmission data for transmission to a subscriber device, wherein the access device communicates with the plurality of receiving devices, and the subscriber device is one of the plurality of receiving devices. The system and method further include transmitting the first transmission data to the subscriber device, and generating, by the access device, a first access receipt indicator corresponding to the first transmission data.
    Type: Application
    Filed: July 1, 2008
    Publication date: January 22, 2009
    Inventor: TZU-MING LIN
  • Publication number: 20090024903
    Abstract: A wireless device to include a non-volatile memory to execute an encoding scheme to provide single-cell error detection and correction on program operations in which the initial nibble value is Fh and on program operations that result in a nibble value of 0h. The non-volatile memory uses multiple writes to program a nibble more than once with non-zero data between erase cycles.
    Type: Application
    Filed: July 17, 2007
    Publication date: January 22, 2009
  • Publication number: 20090024878
    Abstract: An apparatus and computer program product are disclosed for performing in-memory hardware tracing in a processor using an existing system bus. The processor includes multiple processing units that are coupled together utilizing the system bus. The processing units include a memory controller that controls a system memory. Information is transmitted among the processing units utilizing the system bus. The information is formatted according to a standard system bus protocol. Hardware trace data is captured utilizing a hardware trace facility that is coupled directly to the system bus. The system bus is utilized for transmitting the hardware trace data to the memory controller for storage in the system memory. The memory controller is coupled directly to the system bus. The hardware trace data is formatted according to the standard system bus protocol for transmission via the system bus.
    Type: Application
    Filed: August 29, 2008
    Publication date: January 22, 2009
    Inventors: Ra'ed Mohammad Al-Omari, Alexander Erik Mericas, William John Starke
  • Publication number: 20090006907
    Abstract: In a data processing system, in order to provide its operating system with a better mechanism to identify and track addressing errors with a high potential to cause a storage overlay, it is first determined whether or not, a program interrupt has occurred. It is next determined whether or not this interrupt involves or occurs as a result of an address translation. It is then determined whether or not, the instruction involved calls for an update of storage. If it is determined that all three of these conditions are satisfied, then a flag is set in an area of storage accessible to the operating system so that it may provide a more specific event monitoring record.
    Type: Application
    Filed: June 29, 2007
    Publication date: January 1, 2009
    Inventor: Patricia B. Little
  • Publication number: 20080307253
    Abstract: A method and apparatus implement redundant memory access using multiple controllers on the same bank of memory, and a design structure on which the subject circuit resides is provided. A first memory controller uses the memory as its primary address space, for storage and fetches. A second redundant controller is also connected to the same memory. System control logic is used to notify the redundant controller of the need to take over the memory interface. The redundant controller initializes if required and takes control of the memory. The memory only needs to be initialized if the system has to be brought down and restarted in the redundant mode. This invention allows the system to continue to stay up and continue running during a memory controller or link failure.
    Type: Application
    Filed: October 15, 2007
    Publication date: December 11, 2008
    Inventors: Gerald Keith Bartley, Darryl John Becker, John Michael Borkenhagen, Paul Eric Dahlen, Philip Raymond Germann, William Paul Hovis
  • Publication number: 20080288812
    Abstract: A cluster system including: a transmission side server cluster consisting of a plurality of computers; a receiving side server cluster consisting of a plurality of computers; and a network that interconnects both the transmission side server cluster and the receiving side server cluster, wherein an active-transmission computer which is included in the transmission side server cluster selects a standby-transmission computer from the computers in the transmission side server cluster, based on load information, and transmits a backup-copy of a message to the standby-transmission computer when the active-transmission computer transmits the message to a computer in the receiving side server, the stand-by transmission computer for back-up handling of the message in the event of occurrence of a fault in the active-transmission computer.
    Type: Application
    Filed: July 28, 2008
    Publication date: November 20, 2008
    Inventors: Yuzuru Maya, Koji Ito, Masaya Ichikawa, Takaaki Haruna
  • Publication number: 20080276149
    Abstract: An Error Control Code (ECC) apparatus may include a control signal generator that generates an ECC control signal based on channel information. The ECC apparatus also may include: a plurality of ECC encoding controllers that output data respectively inputted via storage elements corresponding to the ECC control signal; and/or an encoding unit that encodes, using a plurality of data outputted from the plurality of ECC encoding controllers, encoding input data into a number of subdata corresponding to the ECC control signal. In addition or in the alternative, the ECC apparatus may include: a plurality of ECC decoding controllers that output data respectively inputted via the storage elements corresponding to the ECC control signal; and/or a decoding unit that decodes, using a plurality of data outputted from the plurality of ECC decoding controllers, a number of decoding input data corresponding to the ECC control signal into one piece of output data.
    Type: Application
    Filed: October 3, 2007
    Publication date: November 6, 2008
    Inventors: Jun Jin Kong, Seung-Hwan Song, Young Hwan Lee, Dong Hyuk Chae, Kyoung Lae Cho, Nam Phil Jo, Sung Chung Park, Dong Ku Kang
  • Publication number: 20080155374
    Abstract: A device, method, and program are provided to prevent an increase of the probability of erroneous correction for a burst error having a length exceeding detection capability even if high correction capability is selected for a random error. In one embodiment, an apparatus corrects errors in a product code block including C1 codes in a row direction and C2 codes in a column direction. First, a C1 decoder performs C1 correction for each of an even C1 including even-numbered bytes in the C1 code and an odd C1 including odd-numbered bytes in the C1 code. Next, a C2 decoder performs erasure correction in C2 correction in the case where any one of the C1 correction results for the even C1 and the odd C1 is correction failure, and where one of the results is the 3-byte correction while the other one is the correction failure or the 3-byte correction.
    Type: Application
    Filed: December 4, 2007
    Publication date: June 26, 2008
    Inventor: Keisuke Tanaka
  • Publication number: 20080082891
    Abstract: Provided a method and device for efficiently retransmitting packets of which transmissions failed in wired/wireless network including detecting continuity by detecting whether or not a sequence ID of a received packet is continuous with a start sequence ID or an end sequence ID of packets included in reception blocks which are generated in advance of the received packet; depending on the result of the detection, manipulating reception blocks to renew or delete the reception blocks or generate a new reception block by using the sequence ID of the received packet; and transmitting an EBN (Explicit Block NACK) for requesting retransmission of lost packets in units of a block when discontinuity is detected.
    Type: Application
    Filed: July 9, 2007
    Publication date: April 3, 2008
    Inventors: Noseong Park, Yoonmee Doh, Sun Joong Kim, Cheol Sig Pyo
  • Publication number: 20080046800
    Abstract: Detecting, avoiding and/or correcting problematic puncturing patterns in parity bit streams used when implementing punctured Turbo codes is achieved without having to avoid desirable code rates. This enables identification/avoidance of regions of relatively poor Turbo code performance. Forward error correction comprising Turbo coding and puncturing achieves a smooth functional relationship between any measure of performance and the effective coding rate resulting from combining the lower rate code generated by the Turbo encoder with puncturing of the parity bits. In one embodiment, methods to correct/avoid degradations due to Turbo coding are implemented by puncturing interactions when two or more stages of rate matching are employed.
    Type: Application
    Filed: October 12, 2007
    Publication date: February 21, 2008
    Applicant: InterDigital Technology Corporation
    Inventors: Philip Pietraski, Gregory Sternberg
  • Publication number: 20080034252
    Abstract: A memory management method for managing a non-volatile memory into which writing is performed in units of blocks includes the steps of assigning a plurality of blocks of the non-volatile memory to a management area formed of at least one block for storing management information, to a code area formed of a plurality of blocks into which program code is written, to a substitution area formed of a plurality of blocks for substituting for a defective block, and to an interference area formed of at least one block; storing at least correspondence information between the blocks of the substitution area and a defective block of a substitution target as management information within the management area; and using the block of the substitution area in place of the defective block on the basis of the correspondence information when the defective block is to be used.
    Type: Application
    Filed: July 31, 2007
    Publication date: February 7, 2008
    Applicant: Sony Ericsson Mobile Communications Japan, Inc.
    Inventors: Katsumi Aoyagi, Tomohiro Ichikawa, Yoshinori Motoyama, Satoshi Hirano, Toshihisa Sanbommatsu, Toru Hayami, Tadashi Kamohara, Kazutoshi Nagatani