Error Or Fault Handling (epo) Patents (Class 714/E11.023)
  • Patent number: 9015714
    Abstract: A diagnostic virtual machine having access to resources of an infrastructure as a service cloud may be created. A user device may be provided access to the diagnostic virtual machine. In some embodiments, the diagnostic virtual machine may be configured to monitor a cluster of hypervisors, and the resources of the infrastructure as a service cloud which the diagnostic virtual machine has access to may include physical resources of the infrastructure as a service cloud that are associated with the cluster of hypervisors.
    Type: Grant
    Filed: November 27, 2012
    Date of Patent: April 21, 2015
    Assignee: Citrix Systems, Inc.
    Inventors: Chiradeep Vittal, Alex Huang, Kevin Kluge
  • Patent number: 8949681
    Abstract: A correction apparatus includes an acquirer that acquires the execution time of an instruction in a given block among a block group that includes blocks obtained by dividing program code; a detector that detects a first resource group designated by a tail instruction in a preceding block that is executed before the given block and a second resource group designated by a head instruction of the given block; an identifier that identifies a resource common to the first and the second resource groups; a calculator that from the time when the identified resource is used by the head instruction and the time when use of the identified resource by the tail instruction ends, calculates a delay period caused by the preceding block; a corrector that based on the calculated delay period, corrects the acquired execution time; and an output device that outputs the corrected execution time.
    Type: Grant
    Filed: June 28, 2012
    Date of Patent: February 3, 2015
    Assignee: Fujitsu Limited
    Inventors: Shinya Kuwamura, Atsushi Ike
  • Patent number: 8750423
    Abstract: A data receiving device includes a receiving unit, an inverse conversion unit and an error correction unit. The receiving unit receives converted data, which is obtained by converting data including transfer data of a plurality of bits, and an error detection code for error detection of the transfer data, according to a predetermined first procedure. The inverse conversion unit inversely converts the received converted data according to a predetermined second procedure. If it is impossible for the inverse conversion unit to inversely convert the converted data, if it is possible for the inverse conversion unit to inversely convert inverted data obtained by inverting a portion of the bits of the converted data, and if an error is not detected in data obtained by inversely converting the inverted data based on the error detection code, the error correction unit performs error correction by inversely converting the inverted data.
    Type: Grant
    Filed: May 10, 2011
    Date of Patent: June 10, 2014
    Assignee: Fuji Xerox Co., Ltd.
    Inventors: Tsutomu Hamada, Manabu Akamatsu
  • Publication number: 20140136890
    Abstract: Computer program product and system to limit core file generation in a massively parallel computing system comprising a plurality of compute nodes each executing at least one task, of a plurality of tasks, by: upon determining that a first task executing on a first compute node has failed, performing an atomic load and increment operation on a core file count; generating a first core file upon determining that the core file count is below a predefined threshold; and not generating the first core file upon determining that the core file count is not below the predefined threshold.
    Type: Application
    Filed: November 14, 2012
    Publication date: May 15, 2014
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Michael E. Aho, John E. Attinella, Thomas M. Gooding
  • Publication number: 20140122922
    Abstract: Methods and structure for enabling re-training of a DDR memory controller in a storage device without loss of data in the DDR memory devices of the cache memory in response to detecting failure of the memory subsystem during operation of the storage device. In response to detecting a failure of the memory subsystem, the memory controller is reset without resetting the memory devices. The memory controller is then re-trained for operation with the memory device. During the re-training, self-refresh mode of the memory devices is disabled and manual refresh is performed by a processor of the storage device to thereby retain any user data in the memory device.
    Type: Application
    Filed: October 26, 2012
    Publication date: May 1, 2014
    Applicant: LSI Corporation
    Inventors: Brandon L. Hunt, Luke E. McKay, Moby J. Abraham, Lakshmana M. Anupindi
  • Publication number: 20140122947
    Abstract: Sequential circuits with error-detection are provided. They may, for example, be used to replace traditional master-slave flip-flops, e.g., in critical path circuits to detect and initiate correction of late transitions at the input of the sequential. In some embodiments, such sequentials may comprise a transition detector with a time borrowing latch.
    Type: Application
    Filed: October 30, 2012
    Publication date: May 1, 2014
    Inventors: Keith A. Bowman, James W. Tschanz, Nam Sung Kim, Janice C. Lee, Christopher B. Wilkerson, Shih-Lien L. Lu, Tanay Karnik, Vivek K. De
  • Publication number: 20140115385
    Abstract: A task unit included in an application is executed. The task unit includes instructions for executing an application task. An exception is thrown by the task unit. A program fragment for resolving the exception is identified and used to obtain user input to resolve the exception.
    Type: Application
    Filed: October 19, 2012
    Publication date: April 24, 2014
    Applicant: VERIZON PATENT AND LICENSING INC.
    Inventors: Don G. Archer, Matt R. Bruce, William D. York
  • Publication number: 20140108862
    Abstract: A processor includes a store queue that stores information representing store instructions. In response to retirement of a store instruction, the processor invalidates the corresponding entry in the store queue, thereby indicating that the entry is available to store a subsequent store instruction. The store address is not removed from the queue until the subsequent store instruction is stored. Accordingly, the store address is available for comparison to a dependent load address.
    Type: Application
    Filed: October 17, 2012
    Publication date: April 17, 2014
    Applicant: Advanced Micro Devices, Inc.
    Inventors: Matthew A. Rafacz, Matthew M. Crum, Michael E. Tuuk
  • Publication number: 20140108856
    Abstract: A system, and in particular a system operating in real-time, may have its operation rely on a particular sequence of trigger signals, hardware or software, for proper operation. A trigger sequence checker provides a way to monitor in real-time predetermined sequences of triggers and is configured to generate an error signal upon detection of a faulty operation or sequence. Rules for sequences of triggers are stored in memory and are used by the trigger sequence checker to verify one or more sequences of triggers received as an input to the checker. A plurality of triggers may be handled by the checker. In one embodiment the checker is configurable to be set in a learning mode to capture triggers rules.
    Type: Application
    Filed: October 17, 2012
    Publication date: April 17, 2014
    Applicant: SCALEO CHIP
    Inventors: Bruno Salle, Eric Miniere
  • Publication number: 20140082406
    Abstract: A memory system may enact emergency activities, such as preventing a write abort, by identifying when a power loss occurs at the earliest time possible. The prediction of a power loss during the process of programming a page, but before all power is lost may allow for the memory to initiate emergency activities. A power loss prediction mechanism may utilize a data link lost signal to trigger data protection. The data link lost signal may indicate that the data connection between the memory and a host has been lost. The signal indicating a data link loss may precede the actual detection of a power loss so that data protection can be implemented quicker.
    Type: Application
    Filed: September 18, 2012
    Publication date: March 20, 2014
    Applicant: SANDISK TECHNOLOGIES INC.
    Inventor: Eran Erez
  • Publication number: 20140068365
    Abstract: An apparatus having a first circuit and a second circuit is disclosed. The first circuit may be configured to (i) read data from a region of a memory circuit during a read scrub of the region and (ii) generate a plurality of statistics based on (a) the data and (b) one or more bit flips performed during an error correction of the data. The memory circuit is generally configured to store the data in a nonvolatile condition. One or more reference voltages may be used to read the data. The second circuit may be configured to (i) update a plurality of parameters of the region based on the statistics and (ii) compute updated values of the reference voltages based on the parameters.
    Type: Application
    Filed: August 29, 2012
    Publication date: March 6, 2014
    Inventors: Zhengang Chen, Earl T. Cohen
  • Publication number: 20140040655
    Abstract: The present disclosure provides techniques for operating a tape drive. A method of operating a tape drive includes monitoring a parameter of the tape drive during a data access operation. The method also includes detecting an access failure. The method further includes selecting a treatment based on the parameter, applying the treatment, and performing a retry.
    Type: Application
    Filed: July 31, 2012
    Publication date: February 6, 2014
    Inventors: Donald J. Fasen, Vernon L. Knowles
  • Publication number: 20140041022
    Abstract: Methods for managing a communication session in a communication network are disclosed. For example, a method includes detecting, by a first endpoint comprising at least one processor, an error condition associated with the communication session, sending, by the first endpoint, a notification of the error condition to a second endpoint that is using a transport layer session and receiving, by the first endpoint, a communication from the second endpoint, proposing a response to the error condition. Another method includes receiving, by a first endpoint comprising at least one processor, a notification of an error condition associated with the communication session, selecting, by the first endpoint, a response to the error condition, and sending, by the first endpoint, a communication to a second endpoint that is using a transport layer session, proposing a response to the error condition.
    Type: Application
    Filed: July 31, 2012
    Publication date: February 6, 2014
    Inventors: DAVID B. SMALL, THOMAS SPENCER, IV
  • Publication number: 20140032957
    Abstract: Provided are a computer program product, system, and method for synchronous mode replication to multiple clusters receiving a write to a volume from a host. A received write is cached in a memory. A determination is made of a replication rule indicating one of a plurality of replication modes for a first cluster and a second cluster used for replication for the write, wherein one of the replication modes comprises a synchronous mode. A determination is made that the replication rule indicates a synchronous mode for the first and the second clusters. The write is transmitted from the memory to the first cluster to store in a first non-volatile storage of the first cluster and to the second cluster to store in a second non-volatile storage in response to determining that the replication rule indicates the synchronous mode.
    Type: Application
    Filed: July 25, 2012
    Publication date: January 30, 2014
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Ralph T. Beeston, Erika M. Dawson, Gavin S. Johnson, Katsuyoshi Katori, Joseph M. Swingler
  • Publication number: 20140026003
    Abstract: An apparatus having a first circuit and a second circuit is disclosed. The first circuit may be configured to (i) generate a reference voltage used by a memory circuit in a first read of a set of data and (ii) adjust the reference voltage based on a plurality of parameters to lower an error rate in a second read of the set from the memory circuit. The second circuit may be configured to update the parameters in response to an error correction applied to the set after the first read from the memory circuit. The memory circuit is generally configured to store the data in a nonvolatile condition by adjusting a plurality of threshold voltages.
    Type: Application
    Filed: July 23, 2012
    Publication date: January 23, 2014
    Inventors: Zhengang Chen, Yunxiang Wu
  • Publication number: 20140019800
    Abstract: An abnormal termination recovery is performed where storage is referenced shortly after the storage has been freed. More specifically, when storage is freed, and that storage is accessed, an abnormal termination error (e.g., a page translation exception event) occurs due to referencing storage that has not been obtained. When the abnormal termination error occurs, an abnormal termination recovery operation is accessed. The abnormal termination recovery operation scans a history of storage freeing operations (e.g., FREEMAIN operations) to determine whether the storage location accessed by the storage access that caused the abnormal termination error was recently freed from within the same address space. If the storage location was recently freed, then the abnormal termination recovery operation reverses the storage freeing operation by issuing a storage obtaining operation (e.g., a GETMAIN operation) to re-obtain the storage.
    Type: Application
    Filed: July 12, 2012
    Publication date: January 16, 2014
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Derek L. Erdmann, Dustin A. Helak, David C. Reed, Max D. Smith
  • Publication number: 20140019797
    Abstract: A system executes a method that includes monitoring the systems that provide the provisioning of computing infrastructure resources to provide services for services executing on the resources, to monitor provisioning changes on the infrastructure resources. It further uses the information gathered by the monitoring of the provisioning resource(s) to provide a tag, which denotes the current assignment of each resource with a service name and an instance of the service associated with the resource identifier and a time stamp, and storing this a relational database, as a part of the record of the state, or performance data for that resource during that time interval.
    Type: Application
    Filed: July 11, 2012
    Publication date: January 16, 2014
    Applicant: CA, Inc.
    Inventor: Wilson T. MacDonald
  • Publication number: 20140006854
    Abstract: File system errors are handled and computing systems are recovered by, responsive to receiving a page buffer request, initializing a sleep timer according to a detection interval value plus a hang resolution range value; responsive to the timer expiring, detecting that a process, thread, application program, daemon, or task is waiting on availability of the requested page buffer; and responsive to the detection, quarantining metadata associated with the requested page buffer, failing the page buffer request and releasing one or more locks on the requested page buffer. This process is then optionally repeated for additional processes, threads, application programs, daemons, tasks or combinations thereof which are waiting for availability of the requested page buffer, optionally randomizing the detection interval value in order to avoid an instantaneous recovery from the error.
    Type: Application
    Filed: July 2, 2012
    Publication date: January 2, 2014
    Applicant: INTERNATIONAL BUSINESS MACHINES CORP
    Inventors: Adekunle Bello, Aruna Yedavilli
  • Publication number: 20140006883
    Abstract: Systems and methods are disclosed for aligning multiple data bits by adjusting the timing of input lines for those data bits. Embodiments include a hierarchical structure for comparing the timing of multiple sets of bits. Other embodiments include aligning data bits from multiple chips in a 3D die stacking architecture.
    Type: Application
    Filed: July 2, 2012
    Publication date: January 2, 2014
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Ying-Yu HSU, Ruey-Bin SHEEN, Shih-Hung LAN, Chih-Hsien CHANG
  • Publication number: 20140006847
    Abstract: Defect management logic extends a useful life of a memory system. For example, as discussed herein, failure detection logic detects occurrence of a failure in a memory system. Defect management logic determines a type of the failure such as whether the failure is an infant mortality type failure or a late-life type of failure. Depending on the type of failure, the defect management logic performs different operations to extend the useful life of the memory system. For example, for early life failures, the defect management logic can retire a portion of the block including the failure. For late life failures, due to excessive reads/writes, the defect management logic can convert the failing block from operating in a first bit-per-cell storage density mode to operating in a second bit-per-cell storage density mode.
    Type: Application
    Filed: June 28, 2012
    Publication date: January 2, 2014
    Inventors: Xin Guo, Yogesh B. Wakchaure, Kiran Pangal, Hiroyuki Sanda
  • Publication number: 20130346791
    Abstract: A SAS storage enclosure to provide storage drive information that includes an expander and a storage manager. The expander supports communication between initiators and associated zoned storage drives of the storage enclosure, and the storage drive information table is to store extended storage drive status information of storage drives of the storage enclosure. The storage manager is to store to the storage drive information table extended storage drive status information of storage drives of the storage enclosure in response to receipt from an initiator a SAS command to store the information, in the event that the storage manager receives from an initiator a command to exchange data with a zoned storage drive and then a storage drive failure occurs with the zoned storage drive. The storage manager sends to the initiator the information in response to receipt from an initiator a SAS command to retrieve the information.
    Type: Application
    Filed: June 25, 2012
    Publication date: December 26, 2013
    Inventors: Michael G. Myrah, Balaji Natrajan, Brian M. Spencer
  • Publication number: 20130346803
    Abstract: In one embodiment, a virtual machine replication system may test a replica data set while continuing to replicate a primary data set. A data storage 250 may store a replica data set for a replica virtual machine 302 to back up a primary data set for a primary virtual machine 304. The data storage 250 may preserve a test point in time 322 in the replica data set using a test differencing disk 344. A processor 220 may execute a test virtual machine 342 that performs a test operation on the test point in time 322 while the replica data set continues to replicate the primary data set.
    Type: Application
    Filed: June 26, 2012
    Publication date: December 26, 2013
    Applicant: Microsoft Corporation
    Inventors: Phani Chiruvolu, Vinod Atal, Gaurav Sinha
  • Publication number: 20130346786
    Abstract: Systems, methods, and software are provided for dynamically escalating service conditions associated with data center failures. In one implementation, a monitoring system detects a service condition. The service condition may be indicative of a failure of at least one service element within a data center monitored by the monitoring system. The monitoring system determines whether or not the service condition qualifies for escalation based at least in part on an access condition associated with the data center. The access condition may be identified by at least another monitoring system that is located in a geographic region distinct from that of the first monitoring system. Upon determining that the service condition qualifies for escalation, the monitoring system escalates the service condition to an escalated condition and initiates an escalated response.
    Type: Application
    Filed: June 20, 2012
    Publication date: December 26, 2013
    Applicant: MICROSOFT CORPORATION
    Inventors: Greg Thiel, Jon Avner, Yogesh Bansal
  • Publication number: 20130339811
    Abstract: Embodiments relate to a method for bitline deletion include, based on detecting a high bitline error rate condition in the cache at a selected bitline address, wherein the high bitline error rate condition indicates a high rate of errors at the selected bitline address, activating the programmable switch in the cache. The method also includes, based on the programmable switch being activated and encountering an error associated with the selected bitline address, automatically deleting, by the computer system, one or more cache lines associated with subsequent errors in the cache regardless of an address of the subsequent errors based on the activated programmable switch, wherein the automatic line deletion indicates a line is unavailable.
    Type: Application
    Filed: June 14, 2012
    Publication date: December 19, 2013
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Ekaterina M. Ambroladze, Patrick J. Meaney
  • Publication number: 20130339779
    Abstract: Aspects of the present invention provide a tool for analyzing and remediating an update-related failure. In an embodiment, a failure state of a computer system that has been arrived at as a result of an update is captured. A semantic diff that includes the difference between the failure state and at least one of an original state or a completion state is then computed. This semantic diff is transformed into a feature vector format. Then the transformed semantic diff is analyzed to determine a remediation for the update. Failure and/or resolution signatures can be constructed using the semantic diff and contextual data, and these signatures can be used in comparison and analysis of failures and resolutions.
    Type: Application
    Filed: August 2, 2012
    Publication date: December 19, 2013
    Applicant: INTERNATIONAL BUSINESS MACHINES COPORATION
    Inventors: Vasanth Bala, Niyu Ge, Ea-Ee Jan, Darrell C. Reimer, Lakshminarayanan Renganarayana, Xiaolan Zhang
  • Publication number: 20130332767
    Abstract: A system for managing communications to add a first Remote Direct Memory Access (RDMA) link between a TCP server and a TCP client, where the first RDMA link references first remote memory buffer (RMB) and a second RMB, and further based on a first remote direct memory access network interface card (RNIC) associated with the TCP server and a second RNIC associated with the TCP client. The system determines whether a third RNIC is enabled. The system adds a second RDMA link, responsive to a determination that the third RNIC is enabled. The system detects a failure in a failed RDMA link. The system reconfigures the first RDMA link to carry at least one TCP message of a connection formerly assigned to the failed RDMA link, responsive to detecting the failure. The system communicates at least one message of the at least one connection on the first RDMA link.
    Type: Application
    Filed: June 12, 2012
    Publication date: December 12, 2013
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Michael J. Fox, Jeffrey D. Haggar, David A. Herr, Hugh E. Hockett, Constantinos Kassimis, Benjamin P. Segal, Jerry W. Stevens
  • Publication number: 20130332772
    Abstract: A registration status manager may poll a user device, such as a session initiation protocol (SIP) endpoint device, for a registration state value indicative of its registration state. The registration status manager may receive the registration state value and determine that it indicates a registration state error such as an out-of-service no dial tone (NDT) condition. The registration status manager may determine a possible cause for failure associated with the registration state error. Subsequently, the registration status manager may determine a possible solution associated with the possible cause for failure.
    Type: Application
    Filed: June 12, 2012
    Publication date: December 12, 2013
    Applicant: Comcast Cable Communications, LLC
    Inventors: Jeswanth Joel PAUL, Thomas Jack TAYLOR, Chirag KHANDELWAL, Kalpa G. SUBRAMANIAN
  • Publication number: 20130326271
    Abstract: According to example configurations, a monitor resource monitors hardware executing a software program. In response to detecting occurrence of a failure associated with an attempted execution of a given software instruction in the software program, the hardware generates a notification. The monitor resource receives the signal generated by the hardware. In response to receiving the signal, the monitor resource initiates computation of the data value associated with the given software instruction. For example, via a communication from the monitor resource to the hardware executing the software program, the monitor resource initiates computation of the value associated with the given instruction by directing the hardware to initiate execution of a specific routine. By way of example, the monitor resource can initiate a lazy computation based on execution of a fault handling function or subroutine to compute a value for the failed instruction.
    Type: Application
    Filed: April 8, 2010
    Publication date: December 5, 2013
    Inventor: Scott E. Petersen
  • Publication number: 20130305087
    Abstract: A method of organizing on-chip data memory in an embedded system-on-chip platform whereon a deterministic application needs to meet a guaranteed constraint on its functional system behavior is disclosed. In one aspect, the method includes: a) dividing the deterministic application into blocks one of which corresponds to a part of a subtask of the application, the block receiving input data and/or generating output data and including internal intermediate data for transforming the input data into the output data, b) splitting the internal intermediate data into state and non-state data, and c) putting the non-state data and a part of the state data in a protected buffering module being part of the data memory and being provided with an error detection and correction module, so that they are available for mitigating the effect of faults on the functional system behavior on-line while meeting the at least one guaranteed constraint.
    Type: Application
    Filed: May 9, 2012
    Publication date: November 14, 2013
    Applicant: IMEC
    Inventors: Francky Catthoor, Mohamed Sabry, Zhe Ma, David Atienza Alonso
  • Publication number: 20130305080
    Abstract: A method, an apparatus and an article of manufacture for detecting an event storm in a networked environment. The method includes receiving a plurality of events via a plurality of probes in a networked environment, each of the plurality of probes monitoring a monitored information technology (IT) element, aggregating the plurality of events received into an event set, and correlating the plurality of events in the event set to determine whether the plurality of events are part of an event storm by determining if the plurality of events in the event set meet one or more event storm criteria.
    Type: Application
    Filed: May 11, 2012
    Publication date: November 14, 2013
    Applicant: International Business Machines Corporation
    Inventors: Michael Man Behrendt, Rafah A. Hosn, Ruchi Mahindru, Harigovind V. Ramasamy, Soumitra Sarkar, Mahesh Viswanathan, Norbert G. Vogl
  • Publication number: 20130297964
    Abstract: Embodiments perform automatic selection of hosts and/or datastores for deployment of a plurality of virtual machines (VMs) while monitoring and recovering from errors during deployment. Resource constraints associated with the VMs are compared against resources or characteristics of available hosts and datastores. A VM placement engine selects an optimal set of hosts/datastores and initiates VM creation automatically or in response to administrator authorization. During deployment, available resources are monitored enabling dynamic improvement of the set of recommended hosts/datastores and automatic recovery from errors occurring during deployment.
    Type: Application
    Filed: May 3, 2012
    Publication date: November 7, 2013
    Applicant: VMware, Inc.
    Inventors: Gururaja HEGDAL, Kiran KASALA, Marichetty M.S.
  • Publication number: 20130283113
    Abstract: Various embodiments of the present invention provide systems and methods for data processing. For example, data processing systems are disclosed that include: a data decoder circuit, a decoder log, a mis-correction detection circuit, and a controller circuit.
    Type: Application
    Filed: April 20, 2012
    Publication date: October 24, 2013
    Inventors: Shaohua Yang, Chung-Li Wang
  • Publication number: 20130283087
    Abstract: A mechanism is provided for handling incidents occurring in a managed environment. An incident is detected in a resource in the managed environment. A set of incident handling actions are identified based on incident handling rules for an incident type of the incident. From the set of incident handling actions, one incident handling action is identified to be executed based on a set of impact indicators associated with the set of incident handling rules. The identified incident handling action is then executed to address the failure of the resource.
    Type: Application
    Filed: April 24, 2012
    Publication date: October 24, 2013
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Michael M. Behrendt, Rafah A. Hosn, Ruchi Mahindru, HariGovind V. Ramasamy, Soumitra Sarkar, Mahesh Viswanathan, Norbert G. Vogl
  • Publication number: 20130283112
    Abstract: Techniques are described for detecting faults in media content based on the behavior of users viewing the media content. Embodiments stream a first instance of media content to one or more users. The behavior of the one or more users is monitored while the users are viewing the streaming first instance of media content. Embodiments then determine whether the first instance of media content is faulty, based on the monitored behavior of the one or more users.
    Type: Application
    Filed: April 19, 2012
    Publication date: October 24, 2013
    Applicant: NETFLIX INC.
    Inventors: Gregory S. ORZELL, John FUNGE, David CHEN
  • Publication number: 20130283086
    Abstract: Resolving virtual machine (VM) issues, by executing VM and operating system (OS) diagnostic monitors, including, monitoring a set of VM and OS health status metrics of a system at a first level, analyzing data of the monitored health status metrics to determine that an instability has occurred when the data exceeds defined bounds for the health status metrics, responding to the instability by monitoring additional VM and OS health status metrics, whereby a level of monitoring of the system is increased from the first level to a second level, greater than the first level, identifying the instability, repairing the system by taking corrective action based on the identified instability; and removing at least one of the set of monitoring and profiling tools to reduce the level of monitoring to a third level once the instability has been resolved, wherein the third level is less than the second level.
    Type: Application
    Filed: April 20, 2012
    Publication date: October 24, 2013
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Lisa M. W. Bradley, Kevin Grigorenko, Rohit D. Kelapure, Dana L. Price
  • Publication number: 20130262947
    Abstract: A mark adding unit adds first information that is erroneously generated error detecting data of first data stored in a first storage area of a memory to the first data and adds second information that is erroneously generated error detecting information of second data stored in a second storage area to the second data. A mark removing unit removes the second information in the second data by rewriting the second information with the error detecting information of the second data without rewriting the first information in the first data when the second storage area out of the first storage area and the second storage area is configured to be usable. An error detecting unit performs an error detecting process of read-out data using information that is added to the read-out data in a case where the data stored in the memory is read out.
    Type: Application
    Filed: September 12, 2012
    Publication date: October 3, 2013
    Applicant: FUJITSU LIMITED
    Inventor: Hideyuki UNNO
  • Publication number: 20130262962
    Abstract: In a method, by a first circuit, a plurality of bits is converted in a first format to a second format. By a second circuit, the plurality of bits in the second format is used to program a plurality of memory cells corresponding to the plurality of bits. The first circuit and the second circuit are electrically coupled together in a first chip. The plurality of bits is selected from the group consisting of 1) address information, cell data information, and program information of a memory cell that has an error; and 2) word data information of a first word and error code and correction information corresponding to the word data information of the first word.
    Type: Application
    Filed: March 29, 2012
    Publication date: October 3, 2013
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Yun-Han CHEN, Sung-Chieh LIN, Kuoyuan (Peter) HSU
  • Publication number: 20130246875
    Abstract: A system for signal processing includes: a plurality of signal processing units associated with corresponding channels; a feedback channel for receiving a selected feedback signal through a selector of an output associated with each of the signal processing units; and a correlator connected to the feedback channel and having a receiving unit to receive the selected feedback signal, an error calculating unit to calculate an error based at least in part on the selected feedback signal, and a correction calculation unit to generate a correcting information based at least in part on the error. In some cases, the association between the signal processing units and the signal channels is configured based on a mode.
    Type: Application
    Filed: March 15, 2012
    Publication date: September 19, 2013
    Applicant: Broadcom Corporation
    Inventors: Timothy RYAN, Ravichandran Ramachandran
  • Publication number: 20130238927
    Abstract: A device power is supplied for running a storage device. When a device error occurs, a recovery operation is performed on the storage device. When the recovery operation fails, the device power is reset in a compatibility verification operation and the recovery operation is performed again on the storage device.
    Type: Application
    Filed: March 8, 2012
    Publication date: September 12, 2013
    Applicant: SYNOLOGY INCORPORATED
    Inventors: Hsuan-Ting Chen, Kuei-Huan Chen, Ming-Hung Tsai
  • Publication number: 20130227368
    Abstract: A data processing device can perform error detection and correction in two stages: in the first stage, error detection is performed for the load data using the in-line error detection information. If a first type of error is detected in the data segment, the error is corrected using the in-line error detection information. If a second type of error is detected error correction is performed using the residual sum.
    Type: Application
    Filed: February 27, 2012
    Publication date: August 29, 2013
    Applicants: BOSTON UNIVERSITY, FREESCALE SEMICONDUCTOR, INC.
    Inventors: Ravindraraj Ramaraju, Ajay J. Joshi, Bobak A. Nazer
  • Publication number: 20130227369
    Abstract: Example embodiments described herein may relate to memory devices, and may relate more particularly to error detection or correction of stored signals in memory devices.
    Type: Application
    Filed: February 28, 2012
    Publication date: August 29, 2013
    Applicant: Micron Technology, Inc.
    Inventor: Ferdinando Bedeschi
  • Publication number: 20130227336
    Abstract: In one embodiment, an intermediate device transmits a data message away from a root device toward a receiver device in a computer network, the data message transmitted by utilizing, in reverse, a link that had been previously selected by the receiver device toward the root device. In response to detecting that the data message did not reach the receiver device, a discovery message is may be sent to one or more neighbor devices, wherein the discovery message carries an identification (ID) of the receiver device and a discovery scope indicating how many hops the discovery message is allowed to traverse to reach the receiver device, and wherein the receiver device, upon receiving the discovery message, triggers a local link repair of the link from the receiver device toward the root device.
    Type: Application
    Filed: February 28, 2012
    Publication date: August 29, 2013
    Applicant: Cisco Technology, Inc.
    Inventors: Navneet Agarwal, Jean-Philippe Vasseur
  • Publication number: 20130219211
    Abstract: A method, an apparatus and an article of manufacture for cloud-driven application execution. The method includes determining a plurality of attributes of a failed application, wherein the plurality of attributes comprises at least one policy context attribute and at least one context attribute, correlating each of the plurality of attributes to at least one alternative asset, wherein the at least one alternative asset is a part of an environment on which the failed application can be executed, using the plurality of attributes correlated to the at least one alternative asset to identify an alternative asset set of alternative assets, wherein the alternative asset set is capable of enabling an alternative environment on which to execute the failed application, and provisioning the alternative assets in the alternative asset set from at least one cloud network to create the alternative environment on which the failed application is executed.
    Type: Application
    Filed: February 17, 2012
    Publication date: August 22, 2013
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Ramesh Gopinath, Andrzej Kochut, Kathiravan M. Ramaswami, Anca Sailer, Charles O. Schulz, Hidayatullah Shaikh
  • Publication number: 20130219234
    Abstract: An apparatus for providing a data integrity field implementation in a data processing system includes a controller operative to interface between a host device and a destination device in the data processing system for transferring at least one data block therebetween. The data processing system further includes an error detection module associated with the controller. The error detection module is operative to determine a probability of an error occurrence based at least in part on a measured current error rate for the data processing system. The controller is operative to implement an error correction methodology which is selectively adaptable as a function of the probability of an error occurrence.
    Type: Application
    Filed: February 16, 2012
    Publication date: August 22, 2013
    Applicant: LSI CORPORATION
    Inventors: Varun Shetty, Debjit Roy Choudhury, Dipankar Das, Ashank Reddy
  • Publication number: 20130212422
    Abstract: Various embodiments provide a method and apparatus of providing a rapid disaster recovery preparation in cloud networks that proactively detects disaster events and rapidly allocates cloud resources. Rapid disaster recovery preparation may shorten the recovery time objective (RTO) by proactively growing capacity on the recovery application(s)/resource(s) before the surge of recovery traffic hits the recovery application(s)/resource(s). Furthermore, rapid disaster recovery preparation may shorten RTO by growing capacity more rapidly than during “normal operation” where the capacity is increased by modest growth after the load has exceeded a utilization threshold for a period of time.
    Type: Application
    Filed: February 14, 2012
    Publication date: August 15, 2013
    Applicant: Alcatel-Lucent USA Inc.
    Inventors: Eric J. Bauer, Randee S. Adams, Daniel W. Eustace
  • Patent number: 8510564
    Abstract: Embodiments are directed to establishing the integrity of a portion of data on at least one level of a plurality of network stack levels and automatically continuing an established federation relationship between at least two federation computer systems. In an embodiment, a first federation computer system receives a digital signature corresponding to a computer system signed by a digital signature which includes the computer system's identity and other federation relationship information configured to establish a trusted federation relationship between a first federation computer system and a second federation computer system. The first federation computer system attempts to validate the received digital signature at a first level of a network stack and determines that the validation at the first network stack layer was unsuccessful. The first federation computer system then validates the received digital signature at a second, different level of the network stack.
    Type: Grant
    Filed: August 6, 2010
    Date of Patent: August 13, 2013
    Assignee: Microsoft Corporation
    Inventors: David J. Nicholson, David Lewis Fisher, Michael D. Ritche, Chun-Hung Lin, Christopher B. Dove, Kavitha Radhakrishnan
  • Publication number: 20130198558
    Abstract: Devices, methods and instructions encoded on computer readable medium for implementation of a dual-adjacency between edge devices of a network site. A first edge device comprises one or more local interfaces configured for communication, via a local network, with one or more network devices co-located in a first network site. The first edge device also comprises one or more overlay interfaces configured for communication, via a core network, with one or more network devices located in one or more other network sites connected to the core network. The first edge device comprises a processor configured to establish, via at least one of the local interfaces, a site communication channel with a second edge device co-located in the first network site. The processor is further configured to establish an overlay communication channel, via at least one of the overlay interfaces, with the second edge device.
    Type: Application
    Filed: January 30, 2012
    Publication date: August 1, 2013
    Applicant: CISCO TECHNOLOGY, INC.
    Inventors: Dhananjaya Rao, Victor M. Moreno, Hasmit Grover, Gaurav Badoni
  • Publication number: 20130198556
    Abstract: Methods and apparatus are provided for determining a lowest total cost maintenance plan. The method comprises receiving a sequence of maintenance actions in an order of a waiting time for each maintenance action, wherein one of the maintenance actions is likely to repair the failure mode. Each maintenance action has an associated cost equal to a waiting time cost, an execution time cost and a material cost, wherein the waiting time of each maintenance action is the time required to requisition and receive material required to perform the maintenance action. The method also constructs a maintenance plan comprising a primary requisition and a secondary requisition by assigning each of the sequence of maintenance actions to one of the primary and secondary requisition.
    Type: Application
    Filed: February 1, 2012
    Publication date: August 1, 2013
    Applicant: HONEYWELL INTERNATIONAL INC.
    Inventors: David Michael Kolbet, Ravindra Patankar, Randy R. Magnuson
  • Publication number: 20130185609
    Abstract: A nonvolatile memory system is provided. The nonvolatile memory device includes a multi-level memory array and a page buffer; and a memory controller configured to control first page data to be to read from the multi-level memory array and stored in the page buffer, a first error bit of the first page data to be detected, an error of the first page data stored in the page buffer to be to corrected using first corrected data having an error corrected in the first error bit, and a first refresh program operation of the error-corrected first page data to be performed on the multi-level memory array.
    Type: Application
    Filed: November 5, 2012
    Publication date: July 18, 2013
    Applicant: SAMSUNG ELECTRONICS CO., LTD.
    Inventor: SAMSUNG ELECTRONICS CO., LTD.
  • Publication number: 20130179607
    Abstract: Data is buffered for concurrent writing to tape. For a magnetic tape drive having a magnetic head with multiple sets of transducers; a drive mechanism configured to pass a magnetic tape past the magnetic head; interfaces from two different hosts; and at least one buffer configured to buffer data; and a control; the buffering comprises receiving data from two different hosts at the interfaces; buffering the received data in separate buffer space of the buffer(s) associated with each host, and adjustably size the separate buffer space for each host in accordance with a data transfer rate of the host associated with the separate buffer space; and concurrently writing data from the separate buffer spaces with the magnetic head to separate partitions of the magnetic tape.
    Type: Application
    Filed: January 5, 2012
    Publication date: July 11, 2013
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: SHAWN O. BRUME, FAHNMUSA C. JANGABA