Abstract: A computer system is configured to manage a value of a variable via firmware. Managing the value of the variable includes detecting a system management interrupt (SMI), causing the computer system to enter a system management mode, in which a request associated with the SMI is handled by the firmware. In response to determining that the SMI is generated by a baseboard management controller (BMC) and that a cause thereof is associated with reading or writing a value of a variable, one or more parameters associated with the variable are obtained from the BMC. Based on the cause of the request and the one or more parameters, the value of the variable is read or overwritten with a new value. The value or the new value is then sent to the BMC, which in turn passes the value or new value to a second computer system over a network.

Abstract: A node mesh contains an originating node and several node groups, each node group consisting of one or more nodes with interfaces connected to other nodes of the node group. Each node of a node group has an associated route table with an association between an applied DC voltage and an output interface to couple the input signal to. When the originating node outputs a DC voltage accompanied by differential signaling, each node in turn directs the DC voltage and differential signaling to an output interface as directed by the node local route table to a local termination in a node, which may be coupled to a training processor of inference processor for machine learning applications.

Abstract: A connection switching device for an aircraft network includes a switching network and a second identification device. The switching network connects input/output devices, such that applications may be interconnected or such that an application may be connected to a peripheral device. The second identification device detects an input/output device that is connected to the connection switching device.

Abstract: Systems and methods are provided for arbitrating sensor and actuator signals in various devices. One system includes input/output (I/O) circuitry, redundant computation circuits coupled to the I/O circuitry, and an arbitration circuit coupled between the I/O circuitry and the redundant computation circuits. The I/O circuitry is configured to be coupled to multiple non-redundant systems, and the redundant computation circuits are configured to be coupled to one of multiple system buses. One such device is an aircraft including multiple non-redundant systems and a plurality of system buses that are configured to transmit redundant messages to the non-redundant systems.

Abstract: A communications link includes multiple continuously calibrated parallel lines, wherein one or more lines are at least partially powered down while being continuously calibrated to reduce power consumption. In one aspect, at least N+1 lines (where N is the logical bus width) are periodically recalibrated, and at least one redundant line is powered down between calibrations. The redundant line could be either a true spare available for use as a replacement, or an extra line which carries functional data while other lines are being calibrated in turn. In another aspect, the logical bus width is variable, but does not exceed NMAX. When N<NMAX, lines not carrying functional data are partially powered down between calibrations.

Abstract: Method and apparatus for providing failover operation for a connection between a first PCIE bridge and a first input/output (IO) device are provided. A first set of bussed bits is exchanged between the first PCIE bridge and the first IO device over a first link using a first set of lanes of the first PCIE bridge. In response to detecting a failure in the first link, at a PCIE bridge end, the first set of lanes is swapped with a second set of lanes of the first PCIE bridge for exchanging a second set of bussed bits between the first PCIE bridge and the first IO device over a second link using the second set of lanes, the second link connecting a second PCIE bridge with a second IO device. In response to detecting the failure in the first link, at an IO device end, the first set of lanes is switched with the second set of lanes for exchanging the second set of bussed bits between the first PCIE bridge and the first IO device over the second link using the second set of lanes.

Abstract: A method for diagnosing a control system for a stacked battery. The control system comprises a plurality of processors, a plurality of controllers, and a monitoring unit (control unit). The method comprises sending a diagnostic information from the central unit to a top processor of the plurality of processors, transmitting a return information from the top processor of the plurality of processors to the central unit, comparing the diagnostic information sent from the central unit with the return information received by the central unit, and indicating a communication problem if the diagnostic information sent from the central unit is different from the return information received by the central unit. The steps are repeated by eliminating the top processor from a previous cycle and assigning a new top processor if there is no problem with the reconfigurable communication system.

Abstract: An information processing apparatus determines an abnormal unit by: determining whether or not there is an abnormal point in access to a slave unit by a first master unit that controls a plurality of slave units connected by a serial bus; requesting a second master unit having redundancy with the first master unit to access a specific slave unit when the abnormal point is determined to exist in access to the specific slave unit in the determining; and determining a unit having an abnormality by use of an access result relating to the abnormal point determined to have an abnormality in the determining and an access result indicating a result of the request made in the requesting.

Abstract: Methods and apparatus are described for an aircraft network that permits an automatic configuring and/or repairing of the network.

Abstract: A communications link of multiple parallel communications lines includes at least one redundant line. In a first aspect, the lines are periodically recalibrated one at a time while the others carry functional data. If a fault is detected, the faulty line is disabled and the remaining previously calibrated lines transmit functional data. In a second aspect, impending line malfunction is detected from anomalies during calibration. In a third aspect, line malfunction is detected from receiver circuit output by determining a logical lane upon which each detected error occurs, and by mapping the logical lane to a physical line currently carrying the logical lane data.

Abstract: A method for detecting peripheral component interconnect (PCI) system errors is applied in a computing device. The computing device includes a north bridge, a baseboard management controller (BMC) connected to the north bridge, and a PCI bus connected to the north bridge. The north bridge detects a PCI system error of the PCI bus, and notifies the BMC of the PCI system error. In response to notification of the PCI system error, the BMC records error information of the PCI system error in a storage system of the computing device.

Abstract: A semiconductor memory device includes: first test circuits each of which operates in a first test mode in which the first test circuit receives a plurality of comparison result signals each indicating a comparison result of storage contents of a plurality of memory cells included in a memory cell array in parallel and generates a first output signal by converting the comparison result signals into serial signals or a second test mode in which the first test circuit generates a second output signal by compressing the data amount of the plurality of comparison result signals. Each of the first test circuits outputs the first and second output signals to a common bus.

Abstract: When a controller identifies a universal serial bus (USB) device connected to a USB interface, it outputs a control signal to close a relay and a first start test signal to an electronic device to test a USB interface of the electronic device. When the test of the USB interface is completed, to the controller adds one to an inside counter, and determines whether the count value reaches a preset count value. If the count value reaches the preset count value, the controller outputs a finish test signal to the electronic device. If the count value does not reach the preset count value, the controller controls the closed relay to open and outputs a second start test signal to close a next relay to test a next USB interface of the electronic device corresponding to the now closed relay.

Abstract: An automatic testing system and method for judging whether a universal serial bus device is configured to a computer are provided. The automatic testing system includes a computer and a testing device for testing the universal serial bus device. By judging whether the universal serial bus device is configured to the computer, the automatic testing system could determine the timing of performing an automatic testing procedure on the universal serial bus device.

Abstract: A system and method for interfacing redundant devices to a distributed control system, includes a first and second redundant field bus modules communicably coupled to the distributed control system and to one another via switches. A pair of redundant field devices are coupled to the switches, one FD having an address. The FBMs adopt respective roles as master FBM and tracker FBM, so that the master FBM is configured to capture data from the one FD using the address, and to pass any data changes periodically to the tracker FBM, through the switches. The master FBM is configured to point to the other field device in the event the other field device has assumed the address. The FBMs are configured to switch roles in the event communication is disrupted between the master FBM and the FD having the address.

Abstract: A master includes a unit configured to register, for each slave, an expected communication time needed to exchange control data; a unit configured to register a slave in which a communication error is detected during exchange of the control data in a communication period; and a unit configured to re-execute exchange of the control data with the registered slave in the same communication period as that in which the communication error is detected. The unit configured to re-execute exchange of control data calculates a remaining resending time that can be used to re-execute exchange of the control data and, when the remaining resending time is longer than the expected communication time of the registered slave, resends the control data.

Abstract: Multiple embodiments relate to a method for detecting a fault on a data line in a bus system in a two-line data network having at least two control units. A data signal is emitted by a transmitter-receiver unit on the two data lines as a differential voltage signal that includes a defined quiescent current. The data lines are mutually connected through a resistance bridge for detecting the middle voltage. The middle voltage is detected directly by a microcontroller after a low-pass filter or as a digital value after an analog-to-digital conversion. The result is displayed and/or stored. A circuit arrangement for implementing the method is also provided.

Abstract: The bus control device includes a reset control unit which resets the input and output bus in response to receipt of reset instruction; a reset inhibition unit which inhibits a reset of the input and output bus triggered by a fault occurrence in the input and output bus; a log collection unit which collects log information of an input and output device connected to a fault occurrence section in the input and output bus triggered by the fault occurrence in the input and output bus; and an input and output interface which transfers the log information collected by the log collection unit to the processor. The reset inhibition unit cancels inhibition of the reset after the collection of the log information by the log collection unit has been completed.

Abstract: A bus fault detecting unit 21 detects a closed PCI bus, and outputs to an OS 1, a PCI card disconnection instructing signal that requires the OS 1 to disconnect PCI cards connected to the closed PCI bus and PCI buses downstream of this PCI bus. The OS 1 disconnects the designated PCI cards from its control, and outputs to a BIOS 2, a power-off instructing signal that instructs to turn off the power of the disconnected PCI cards. In response to this, a PCI card disconnection handling unit 23 activates a bus diagnosing unit 24, and the bus diagnosing unit 24 diagnoses whether the closed PCI bus functions normally or not. In a case where the closed PCI bus functions normally, a bus opening unit 25 opens the closed PCI bus.

Abstract: A method of operation of a computer system having a master and slave Inter-IC (I2C) bus network includes detecting and isolating an I2C bus failure, configuring a failed I2C bus as offline, reconfiguring a remaining I2C bus as a multi-mastered bus, and masking the failed I2C bus from operation until the failed I2C bus can be repaired. A first test request is sent to a remote device from a local device. If the remote device receives the first test request, a remote bus mode is switched to a failure position, a local bus mode is switched to a multi-master position, and a second request is sent to the remote device to indicate position changes.

Abstract: A bus station circuit (14) operates in an electronic system with a bus (10). The bus station determines an initial synchronization time point by detecting a synchronization signal pattern on the bus and switching to a synchronization enabled state upon detection of the synchronization signal pattern. Starting points of successive messages are determined head to tail from the end points of immediately preceding messages, when operating in the synchronization enabled state. The content of the messages is tested for validity. The bus station switches to a synchronization disabled state in response to detection of a message with invalid content. While in the synchronization disabled state, use of messages that are received is disabled in the bus station circuit. In the synchronization disabled state the bus station waits for a synchronization event to switch back to the synchronization enabled state.

Abstract: An automated system for validating Peripheral Component Interconnect (PCI) bus adapters or PCI-X bus adapters has a computer, motherboard, a PCI-X bus and isolated test slot for operatively coupling a PCI/PCI adapter under test through the PCI-X bus to the motherboard. The isolated test slot is adapted and arranged to minimize degradation of data flow on the PCI-X bus such that a PCI-X adapter, mounted in the isolated test slot, can negotiate a required operating rate greater than PCI operating rates. It can be configured as a low profile slot in a low profile computer system, such as a 2U low profile system. A method for validating the PCI/PCI-X bus adapters comprises operatively coupling the bus adapter under test to the motherboard, negotiating to the required operating rate and testing the functionality of the adapter. The operating rate of the bus adapter can be verified to ensure the PCI/PCI-X bus adapters are tested at required PCI/PC-X rates.