Error Detection Or Correction Of The Data By Redundancy In Hardware (epo) Patents (Class 714/E11.054)

  • Patent number: 8984373
    Abstract: An exemplary method for accessing a flash memory. The method comprising obtaining a first random sequence; utilizing the first random sequence as a first seed for generating a second random sequence, wherein the first random sequence is not equivalent to the second random sequence; scrambling data according to the second random sequence for generating scrambled data; performing an error correction encoding operation upon the first random sequence and the scrambled data for generating parity check code; and storing the scrambled data and the parity check code to the flash memory.
    Type: Grant
    Filed: February 22, 2012
    Date of Patent: March 17, 2015
    Assignee: Silicon Motion, Inc.
    Inventor: Tsung-Chieh Yang
  • Patent number: 8948960
    Abstract: Systems and methods are provided for arbitrating sensor and actuator signals in various devices. One system includes input/output (I/O) circuitry, redundant computation circuits coupled to the I/O circuitry, and an arbitration circuit coupled between the I/O circuitry and the redundant computation circuits. The I/O circuitry is configured to be coupled to multiple non-redundant systems, and the redundant computation circuits are configured to be coupled to one of multiple system buses. One such device is an aircraft including multiple non-redundant systems and a plurality of system buses that are configured to transmit redundant messages to the non-redundant systems.
    Type: Grant
    Filed: November 30, 2007
    Date of Patent: February 3, 2015
    Assignee: Honeywell International Inc.
    Inventor: Scot E. Griffith
  • Patent number: 8775899
    Abstract: An error correction device includes: an error correction code generator that generates, from information unit data of data with a parity bit which includes m bytes of information unit data in which each byte has n bits of data and a total of m parity bits where 1 bit is provided for every 1 byte of the information unit data, a bit other than a bit corresponding to the parity bit out of bits constituting an error correction code used for correcting an error in the information unit data; an error detector that detects an error in the information unit data by generating an exclusive-OR of the data with a parity bit; and an error corrector that corrects an error in the information unit data by using a parity bit included in the data with a parity bit and the bit generated by the error correction code generator.
    Type: Grant
    Filed: August 3, 2012
    Date of Patent: July 8, 2014
    Assignee: Fujitsu Limited
    Inventor: Shiro Kamoshida
  • Publication number: 20140108852
    Abstract: Provided are a computer program product, system, and method for processing main cause errors and sympathetic errors in devices in a system. Error data for the devices in the system are analyzed to determine a main cause error for one of the devices that cause at least one sympathetic error in the system. A main cause event object for the determined main cause error and at least one sympathetic event object for the determined at least one sympathetic error resulting from the main cause error are generated. A determination is made from the at least one sympathetic event object of at least one sympathetic event action to perform. The determined at least one sympathetic event action is performed to recover from the at least one sympathetic error represented by the at least one sympathetic event object providing the at least one sympathetic event action.
    Type: Application
    Filed: October 17, 2012
    Publication date: April 17, 2014
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Ricardo S. Padilla, Todd C. Sorenson, David V. Valverde, Wang Ping He
  • Publication number: 20140059377
    Abstract: Aspects of the disclosure pertain to a system and method for providing dynamic y-buffer size adjustment for retained sector reprocessing (RSR). The system and method implement dynamic y-buffer size adjustment for RSR for promoting improved Sector Failure Rate (SFR) performance of the system. The system is a read channel system.
    Type: Application
    Filed: August 24, 2012
    Publication date: February 27, 2014
    Applicant: LSI CORPORATION
    Inventors: Fan Zhang, Yang Han, Weijun Tan, Shaohua Yang
  • Publication number: 20140053020
    Abstract: A system for and method improving order and transaction flow-though and processing. The method may include receiving an order request from a user corresponding to the order. The method may further include determining a set of order particulars associated with the user and the order for resolution against an external system for order fulfillment, and determining if any order particular is incorrect or missing. The method may also include identifying the missing or correct order particular, and updating the set of order particulars to include the missing or correct order particular without requesting missing or correct order particular from the user. The method may include transmitting the updated order particulars to the external system for order fulfillment.
    Type: Application
    Filed: August 20, 2012
    Publication date: February 20, 2014
    Applicant: VERIZON PATENT AND LICENSING, INC.
    Inventors: Dhanrai J. NAIR, Mirela E. COSUTA, Priya HARIHARAN, Narayanasamy RENGASAMY
  • Publication number: 20140047293
    Abstract: A semiconductor circuit comprising a digital circuit portion, which comprises a combinatorial logic block. The semiconductor circuit further comprises a scan chain for loading and applying a predefined digital test pattern to inputs of the combinatorial logic block. A bi-directional communication port is adapted for writing incoming data to an address space of the digital circuit portion. Scan control hardware comprises a plurality of individually addressable scan control registers which are mapped to the address space of the bi-directional communication port. A method of testing the digital circuit portion involves, using the scan chain, writing bit values to inputs of the individually addressable scan control registers, and reading bit values from at least one output of an individually addressable scan control register. The method and semiconductor circuit allow thorough testing and diagnosing of failing semiconductor devices, including core logic thereof, while mounted on a printed circuit board.
    Type: Application
    Filed: August 13, 2012
    Publication date: February 13, 2014
    Applicant: ANALOG DEVICES A/S
    Inventors: David Lamb, Kendrick Owen Daniel Franzen, David Hossack
  • Publication number: 20140019801
    Abstract: A method includes monitoring a plurality of HyperSwap sessions between one or more storage systems located at a first location and one or more storage systems located at a second location, wherein at least one of the one or more storage systems located at the first location and at the second location are designated as a primary storage system. The method includes detecting an error event and freezing communications between the storage systems located at the first location and the second location in response to the error event. The method also includes designating either the first location or the second location as a preferred location and modifying the designation of all of storage systems at the preferred location to be primary storage systems in response to the error event.
    Type: Application
    Filed: July 12, 2012
    Publication date: January 16, 2014
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Peter G. Sutton, William J. Rooney
  • Publication number: 20140013153
    Abstract: Responsive to a cluster manager for a particular node from among multiple nodes allocating at least one leased resource for a resource group for an application workload on the particular node, on fallover of the resource group from another node to the particular node, setting a timer thread, by the cluster manager for the particular node, to track an amount of time remaining for an initial lease period of the at least one leased resource. Responsive to the timer thread expiring while the resource group is holding the at least one leased resource, maintaining, by the cluster manager for the particular node, the resource group comprising the at least one leased resource for an additional lease period and automatically incurring an additional fee, only if the particular node has the capacity to handle the resource group at a lowest cost from among the nodes.
    Type: Application
    Filed: July 5, 2012
    Publication date: January 9, 2014
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: JES KIRAN CHITTIGALA, RAVI A. SHANKAR
  • Publication number: 20130346812
    Abstract: The present disclosure relates to wear leveling memory using error rate. A number of embodiments comprise: programming data to a selected group of a number of groups of memory cells based, at least partially, on a process cycle count corresponding to the selected group; determining an error rate corresponding to the selected group; and adjusting the process cycle count corresponding to the selected group based, at least partially, on the determined error rate corresponding to the selected group.
    Type: Application
    Filed: June 22, 2012
    Publication date: December 26, 2013
    Applicant: MICRON TECHNOLOGY, INC.
    Inventors: Shirish D. Bahirat, Todd A. Marquart
  • Publication number: 20130311854
    Abstract: A memory controller adds the redundant information that is used to correct an error for each of data of a predetermined length and stores the data into the nonvolatile memory in the case in which data is written to the nonvolatile memory, the memory controller reads data and the redundant information that has been added to the data from the nonvolatile memory in the case in which data is read from the nonvolatile memory, and the memory controller corrects an error based on the redundant information in the case in which the data includes an error. The memory controller stores data that is in a basic unit that is a unit of an error correction configured by the data of a predetermined length and the redundant information that is added to the data of a predetermined length into a plurality of predetermined pages in a dispersed manner.
    Type: Application
    Filed: May 18, 2012
    Publication date: November 21, 2013
    Inventors: Takashi Tsunehiro, Akifumi Suzuki, Junji Ogawa
  • Publication number: 20130297987
    Abstract: A page buffer for a NAND memory array has a data register and a cache register that are suitably organized and operated to eliminate gaps and discontinuities in the output data during a continuous page read. The cache register may be organized in two portions, and the page data in the cache may be output from the cache portions in alternation. ECC delay may be eliminated from the output by performing the ECC computation on one cache portion while the other is being output. The data register may also be organized in two portions corresponding to the cache portions, so that data may be transferred to one cache portion while the other is being output. In a variation, the continuous page read may be done without ECC.
    Type: Application
    Filed: May 4, 2012
    Publication date: November 7, 2013
    Applicant: WINBOND ELECTRONICS CORPORATION
    Inventors: Anil Gupta, Oron Michael, Robin John Jigour
  • Publication number: 20130262915
    Abstract: An aspect of this invention is a method that includes evaluating a computing environment by performing auditing of a fault tolerance ability of the computing environment to tolerate each of a plurality of failure scenarios; constructing a failover plan for each of the plurality of scenarios; identifying one or more physical resource limitations which constrain the fault tolerance ability; and identifying one or more physical resources to be added to the computing environment to tolerate each of the plurality of failure scenarios.
    Type: Application
    Filed: March 30, 2012
    Publication date: October 3, 2013
    Applicants: International Business Machines Corporation
    Inventors: David C. FRANK, Richard E. Harper, Jeffrey Lucash, Kyung D. Ryu, Ravi A. Shankar, Thomas Weaver
  • Publication number: 20130219247
    Abstract: An exemplary method for accessing a flash memory. The method comprising obtaining a first random sequence; utilizing the first random sequence as a first seed for generating a second random sequence, wherein the first random sequence is not equivalent to the second random sequence; scrambling data according to the second random sequence for generating scrambled data; performing an error correction encoding operation upon the first random sequence and the scrambled data for generating parity check code; and storing the scrambled data and the parity check code to the flash memory.
    Type: Application
    Filed: February 22, 2012
    Publication date: August 22, 2013
    Applicant: SILICON MOTION, INC.
    Inventor: Tsung-Chieh Yang
  • Publication number: 20130185606
    Abstract: System and methods for proactively refreshing portions of a nonvolatile memory are disclosed. A memory system may proactively refresh a portion of nonvolatile memory based on data associated with the portion. The data may include the time elapsed since the portion was last refreshed, the number of times the portion has been cycled, and the average operating temperature of the nonvolatile memory. A portion of nonvolatile memory meeting certain criteria determined from that data may be proactively refreshed during a downtime when the nonvolatile memory is not otherwise being accessed.
    Type: Application
    Filed: January 18, 2012
    Publication date: July 18, 2013
    Applicant: APPLE INC.
    Inventor: Anthony Fai
  • Publication number: 20130179727
    Abstract: A redundant controller engine (RCE) of a system includes a first, second and at least a third redundant processing unit (RPU). The RCE includes an arbitrator in communication with the first, second and third RPUs which sends a message for a corresponding time requiring a decision to the first, second and third RPUs, and receives the decisions made by the first, second and third RPUs. The arbitrator accepts a first two matching decisions for the corresponding time received from the first, second and third RPUs, and sending the matching decision for the corresponding time to the system. The arbitrator has a first message processing unit (MPU) and a second MPU. The first MPU sends the message for the corresponding time to and receives the decisions for the corresponding time from the first, second and third RPUs. A method for processing data from a system. An apparatus for conferencing.
    Type: Application
    Filed: January 7, 2012
    Publication date: July 11, 2013
    Inventors: Anthony Grieco, Ken Price, John L. Driscoll, Stephen Schweizer
  • Publication number: 20130166947
    Abstract: The present disclosure discloses a power system with hot-swap with a buck converter. The power system comprises a front stage, a hot-swap stage and a load stage; wherein the hot-swap stage comprises: a buck converter having a switch operate at ON/OFF state to provide a desired output voltage to the load stage with low power loss and optimized thermal design.
    Type: Application
    Filed: December 22, 2011
    Publication date: June 27, 2013
    Inventors: Eric Yang, ZhengXing Li, Yuancheng Ren
  • Publication number: 20130151890
    Abstract: In accordance with embodiments of the present disclosure, a method may comprise identifying one or more portions of the memory having defects. The method may also include storing one or more addresses in the memory defect list, each of the one or more addresses associated with a portion of the one or more identified portions. The method may further include indicating to components of an information handling system that the one or more identified portions are unusable such that the other components are prevented from allocating and using the one or more identified portions.
    Type: Application
    Filed: December 7, 2011
    Publication date: June 13, 2013
    Applicant: DELL PRODUCTS L.P.
    Inventors: Stephen Ray Cooper, Bryan James Thornley
  • Publication number: 20130132764
    Abstract: A method may include receiving an order associated with processing a media file and forwarding the order to a resource management system. The method may also include identifying, by the resource management system, tasks associated with fulfilling the order, storing the plurality of tasks and identifying an execution system to execute the tasks. The method may further include forwarding, by the resource management system, the tasks to the execution system.
    Type: Application
    Filed: November 21, 2011
    Publication date: May 23, 2013
    Applicant: Verizon Patent and Licensing Inc.
    Inventor: Mohammad Reza Shafiee
  • Publication number: 20130117635
    Abstract: Disclosed is a method of controlling a nonvolatile memory device which includes programming data in a user data area of the nonvolatile memory device and state information on logical states of the data in a meta area of the nonvolatile memory device; and adjusting levels of a plurality of read voltages using the state information to read the data from the user data area using the plurality of read voltages having the adjusted levels.
    Type: Application
    Filed: July 17, 2012
    Publication date: May 9, 2013
    Inventors: Dong Ju Ok, Kyoung Lae Cho, Dongsub Kim
  • Publication number: 20130086427
    Abstract: A portable device for diagnosing a diagnosis device, a method for providing a diagnosis service, and a diagnosis system thereof are provided. The portable device includes a setting information collecting unit which collects setting information relating to the diagnosis device which is output from the diagnosis device, a diagnosis device information generating unit which generates diagnosis device information based on the setting information, a communication unit which transmits the diagnosis device information to a server, and a diagnosis result output unit which, if diagnosis result information is received from the server via the communication unit, outputs the received diagnosis result information. Accordingly, an electronic apparatus without a network function may provide a diagnosis service remotely by using a portable device.
    Type: Application
    Filed: September 14, 2012
    Publication date: April 4, 2013
    Applicant: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Myung-suk BAE, Jong-ho RHEE
  • Publication number: 20130080858
    Abstract: Methods of performing a read retry, including reading a non-volatile memory with new read parameters, and devices for performing such methods are disclosed. The read retry operation and/or subsequent read retry operation may be initiated and/or completed before it is determined that such read retry operation is warranted. For example, a page of a NAND flash memory may be read in a read retry operation with new read voltage levels applied to a word line of the page. For example, a read retry operation may be performed on a target page prior to determining errors of a previous read page of data of the target page are uncorrectable via an ECC operation.
    Type: Application
    Filed: March 24, 2012
    Publication date: March 28, 2013
    Inventors: Sang Hoon Lee, Sung-Hwan Bae, Jong-Nam Baek, Hyun Seok Kim, Sung Bin Kim
  • Publication number: 20130067271
    Abstract: The method includes receiving a command at a first storage system of a block storage cluster. The command is transmitted by the initiator system to the first storage system via a network and includes a request for data. The method further includes transferring the stored data from the first storage system to the initiator system via the network when data requested in the data request is stored by the first storage system. The method further includes transmitting a referral response from the first storage system to the initiator system when a portion of the data requested in the data request is not stored by the first storage system, but is stored by a second storage. system of the block storage cluster.
    Type: Application
    Filed: November 5, 2012
    Publication date: March 14, 2013
    Applicant: NETAPP, INC.
    Inventor: NETAPP, INC.
  • Publication number: 20130061100
    Abstract: With increasing capacity, testing of three-dimensional mask-programmed read-only memory (3D-MPROM) becomes too time-consuming and expensive. Accordingly, the present invention discloses a field-repair system. Most of the 3D-MPROM data are not checked in the factory, but checked and repaired in the field. The field-repair system comprises a playback device with a communicating means. The playback device checks the 3D-MPROM data as they are read out. When bad data are detected, the good data to replace the bad data are fetched from a remote server with the communicating means. The remote server stores at least a copy of the content being read.
    Type: Application
    Filed: August 28, 2012
    Publication date: March 7, 2013
    Applicant: ChengDu HaiCun IP Technology LLC
    Inventor: Guobiao ZHANG
  • Publication number: 20130061108
    Abstract: The present invention discloses a self-repair system for three-dimensional mask-programmed read-only memory (3D-MPROM). Most of the 3D-MPROM data are not checked in the factory, but checked and repaired in the field. This self-repair system comprises a playback device with a re-writable memory (RWM). The RWM temporarily stores new contents. After a user receives a 3D-MPROM card storing the same contents, the playback device checks the 3D-MPROM data. When bad data are detected, the good data to replace the bad data are fetched from the RWM.
    Type: Application
    Filed: August 28, 2012
    Publication date: March 7, 2013
    Applicant: CHENGDU HAICUN IP TECHNOLOGY LLC
    Inventor: Guobiao ZHANG
  • Publication number: 20130055036
    Abstract: An image forming apparatus including an acquisition unit configured to acquire log data recording operation of the image forming apparatus, a first storage unit configured to store the acquired log data in a volatile memory, a calculation unit configured to calculate a total size of the log data stored in the volatile memory, a determination unit configured to determine whether the calculated total size of the log data has reached a threshold value, a second storage unit configured to store the log data from the first storage unit when the total size of the log data in the first storage unit has reached the threshold value, and a changing unit configured to change the threshold value according to an operation state of the image forming apparatus.
    Type: Application
    Filed: October 30, 2012
    Publication date: February 28, 2013
    Applicant: CANON KABUSHIKI KAISHA
    Inventor: CANON KABUSHIKI KAISHA
  • Publication number: 20130042164
    Abstract: A non-volatile semiconductor memory device includes: a memory unit including a plurality of memory cells, each of the plurality of memory cells to perform a multi-level storage operation by assigning a value including a plurality of bits to at least four data states defined according to a threshold level; and a controller to control the memory unit, wherein the controller sets at least one of the plurality of bits to an error correction bit that indicates one of a first state and a second state; assigns the first state to the error correction bits that correspond to the data states having a minimum threshold level and a maximum threshold level and the second state to the error correction bits that correspond to the data state having other threshold level; and resets the error correction bit to the first state when the error correction bit indicates the second state.
    Type: Application
    Filed: June 29, 2012
    Publication date: February 14, 2013
    Applicant: FUJITSU LIMITED
    Inventors: Toshihiko Suzuki, Hidenori Takahashi, Terumasa Haneda, Atsushi Uchida
  • Publication number: 20130031432
    Abstract: A memory circuit including a logic circuit, content addressable memory, and a multiplexer. The logic circuit is configured to output a first address. The content addressable memory is configured to i) receive the first address and ii) output a substitute address and a match signal if the first address matches a second address stored in the content addressable memory. The multiplexer is configured to i) receive the first address and the substitute address and ii) selectively output one of the first address and the substitute address based on the match signal.
    Type: Application
    Filed: October 1, 2012
    Publication date: January 31, 2013
    Applicant: Marvell World Trade Ltd.
    Inventor: Marvell World Trade Ltd.
  • Publication number: 20130031443
    Abstract: A method of operating a memory controller includes reading data from a first block of a memory device; detecting degraded pages from a plurality of pages of the first block and counting a number of the degraded pages in the first block; and recharging or reclaiming the first block, which includes the degraded pages, based on the counted number of the degraded pages.
    Type: Application
    Filed: July 16, 2012
    Publication date: January 31, 2013
    Applicant: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Eun-Chu Oh, Jae-Hong Kim, Yong-June Kim, Jun-Jin Kong
  • Publication number: 20130024719
    Abstract: In a system and method for processing network data of a server, the server includes a timer, a switch and a storage system. The server determines whether the storage system includes overtime information of the timer when server is powered on. If the storage system includes the overtime information, the overtime information is deleted. If an operating system is started, a predetermined initial value is written into the timer to start timing, and a first network port and a second network port are disconnected through the switch. If the server works normally, a predetermined reset command is sent to the timer to reset the timer at regular intervals. If the server does not work normally, the first network port and the second network port are connected through the switch. If the timer times out, the overtime information is written into the storage system.
    Type: Application
    Filed: October 25, 2011
    Publication date: January 24, 2013
    Applicants: HON HAI PRECISION INDUSTRY CO., LTD., HONG FU JIN PRECISION INDUSTRY (ShenZhen) CO., LTD.
    Inventor: YU-GANG ZHANG
  • Publication number: 20130013958
    Abstract: A method begins by a dispersed storage (DS) processing module generating a set of encoded data slices based on a data segment of data and dispersed storage network (DSN) addressing information regarding metadata of the data. The method continues with the DS processing module generating a set of encoded metadata slices based on the metadata and DSN addressing information regarding the data. The method continues with the DS processing module generating a set of metadata write commands regarding storing the set of encoded metadata in a first set of DS units of DSN memory. The method continues with the DS processing module generating a set of data segment write commands regarding storing the set of encoded data slices in a second set of DS units of the DSN memory.
    Type: Application
    Filed: June 20, 2012
    Publication date: January 10, 2013
    Applicant: CLEVERSAFE, INC.
    Inventor: Wesley Leggette
  • Publication number: 20130007503
    Abstract: Continuous workload availability between sites at unlimited distances, which includes receiving a unit of work data. Once the unit of work data has been received the workload that the unit of work data is directed to is determined, and a primary site of a plurality of sites to process the unit of work is chosen. If the processing of the unit of work data is successful, then one of one or more processing systems of the primary site are selected to process the unit of work data, and the unit of work data is replicated to at least one other site. The primary site is separated from each of the plurality of sites by a distance greater than a metropolitan area network (MAN) and operations occur within a customer acceptability window.
    Type: Application
    Filed: June 30, 2011
    Publication date: January 3, 2013
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Jaime F. Anaya, Paul M. Cadarette, Michael G. Fitzpatrick, David B. Petersen
  • Publication number: 20130007509
    Abstract: A method of utilizing storage in a storage system comprises prioritizing a plurality of storage areas in the storage system for data recovery with different priorities; and performing data recovery of the storage system at an occurrence of a failure involving one or more of the storage areas in the storage system based on the priorities. Data recovery for one storage area having a higher priority is to occur before data recovery for another storage area having a lower priority in the storage system. In various embodiments, the prioritization is achieved by monitoring the access characteristics, or the priority is specified by the host or management computer based on the usage and/or importance of data stored in the storage system, or the priority is determined by the storage system based on the area assignment/release (i.e., usage) of thin provisioned volumes.
    Type: Application
    Filed: September 14, 2012
    Publication date: January 3, 2013
    Applicant: HITACHI, LTD.
    Inventors: Hiroshi ARAKAWA, Akira YAMAMOTO
  • Publication number: 20130007542
    Abstract: In some example embodiments, a method includes performing a memory scrub of a memory across a scrub cycle of multiple scrub cycles. The method includes identifying correctable errors of symbols in the memory that are a result of accesses from a section of the memory in response to the memory scrub. The method also includes performing an analysis across the multiple scrub cycles, wherein the performing of the analysis comprises determining whether at least two symbols across the multiple scrub cycles have at least one correctable error. The method includes responsive to determining that at least two symbols across the multiple scrub cycles have at least one correctable error, executing at least one repair of the memory that includes the section of memory.
    Type: Application
    Filed: August 21, 2012
    Publication date: January 3, 2013
    Applicant: International Business Machines Corporation
    Inventors: Jay W. Carman, Marc A. Gollub, Anshuman Khandual, Jyotindra Patel
  • Publication number: 20120324313
    Abstract: A method for encoding a data word for writing an encoded data word in N cells of a solid state memory. Each of the N cells can be programmed in one of q nominal levels. The method includes encoding the data word as a codeword of a first codeword type having q symbol values or as a codeword of a second codeword type having (q-d) symbol values, d ? [1, . . . , q-1], depending on a state of the N cells.
    Type: Application
    Filed: August 28, 2012
    Publication date: December 20, 2012
    Applicant: International Business Machines Corporation
    Inventors: Thomas Mittelholzer, Nikolaos Papandreou, Charalampos Pozidis
  • Publication number: 20120311395
    Abstract: A method begins by a dispersed storage (DS) processing module generating preliminary dispersed storage network (DSN) storage information for data to be stored in a DSN. The method continues with the DS processing module accessing DSN storage information regarding other data stored in the DSN and comparing the preliminary DSN storage information for the data with the DSN storage information regarding the other data. When at least a portion of the data has compatible preliminary DSN storage information with DSN storage information of at least a portion of the other data, the method continues with the DS processing module generating DSN storage information for remaining portions of the data to produce remaining portions DSN storage information and generating DSN storage information for the data based on the DSN storage information of the at least the portion of the other data and the remaining portions DSN storage information.
    Type: Application
    Filed: May 4, 2012
    Publication date: December 6, 2012
    Applicant: CLEVERSAFE, INC.
    Inventors: Wesley Leggette, Jason K. Resch
  • Publication number: 20120311376
    Abstract: A secondary location of a network acts as a recovery network for a primary location of the service. The secondary location is maintained in a warm state that is configured to replace the primary location in a case of a failover. During normal operation, the primary location actively services user load and performs backups that include full backups, incremental backups and transaction logs that are automatically replicated to the secondary location. Information is stored (e.g. time, retry count) that may be used to assist in determining when the backups are restored correctly at the secondary location. The backups are restored and the transaction logs are replayed at the secondary location to reflect changes (content and administrative) that are made to the primary location. After failover to the secondary location, the secondary location becomes the primary location and begins to actively service the user load.
    Type: Application
    Filed: June 6, 2011
    Publication date: December 6, 2012
    Applicant: MICROSOFT CORPORATION
    Inventors: Viktoriya Taranov, Alexander Hopmann, Antonio Marcos Da Silva, JR., Nikita Voronkov, Kai Yiu Luk, Ramanathan Somasundaram, Artsiom Kokhan, Siddharth Rajendra Shah, Daniel Blood, Bhavesh Doshi
  • Publication number: 20120311378
    Abstract: Techniques are described for increasing a lifetime of blocks of memory. In operation, respective life expectancy scores for each of the blocks are calculated based at least in part on a respective number of times each of the blocks is respectively erased, and further based at least in part on at least one other factor that affects the lifetime of the blocks. An order to write and recycle the blocks is determined, based at least in part on at least some of the respective lifetime expectancy scores. A total amount of the blocks that are erased and written is minimized while lifetime expectancy score variation between the blocks is equalized.
    Type: Application
    Filed: August 10, 2012
    Publication date: December 6, 2012
    Applicant: LSI CORPORATION
    Inventor: Radoslav Danilak
  • Publication number: 20120311381
    Abstract: The present disclosure includes apparatus (e.g., computing systems, memory systems, controllers, etc.) and methods for providing data integrity. One or more methods can include, for example: receiving a number of sectors of data to be written to a number of memory devices; appending first metadata corresponding to the number of sectors and including first integrity data to the number of sectors, the first metadata has a particular format; generating second integrity data to be provided in second metadata, the second integrity data corresponding to at least one of the number of sectors (wherein the second metadata has a second format); and generating third integrity data to be provided in the second metadata, the third integrity data including error data corresponding to the second integrity data and the at least one of the number of sectors.
    Type: Application
    Filed: May 31, 2011
    Publication date: December 6, 2012
    Applicant: Micron Technology, Inc.
    Inventor: Kent A. Porterfield
  • Publication number: 20120304040
    Abstract: A checksum calculation, prediction and validation system includes a host system, a network interface, a reception pipeline disposed between the host system and network interface and configured to calculate an expected full checksum related to packets received in the host system and a transmission pipeline disposed between the host system and network interface and configured calculate factors related to packets for transmission on the network interface.
    Type: Application
    Filed: May 27, 2011
    Publication date: November 29, 2012
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Carl A. Bender, Michael J. Cadigan, JR., Nihad Hadzic, Howard M. Haynie, Jeffrey M. Turner, Raymond Wong
  • Publication number: 20120297237
    Abstract: An improved data access layer (DAL) architecture enables database connection pooling or multiplexing across machine boundaries. Drivers installed at web servers communicate with servers in a DAL. The DAL servers present a virtual database to the web servers, and the DAL servers in turn open connections to a set of physical databases. DAL servers are able to recycle connections that are no longer needed, or to move available connections from one DAL server to another, so as to provide improved efficiency in connection management, burst management, and peak load management. Scalability is thereby improved, and more efficient use of system resources is facilitated.
    Type: Application
    Filed: July 30, 2012
    Publication date: November 22, 2012
    Applicant: Wal-Mart Stores, Inc.
    Inventors: Amlan Chatterjee, Chirag R. Shah, Mohan Kishore, Jack P. Hsu
  • Publication number: 20120297238
    Abstract: A cloud migration system is described herein that provides capacity management and disaster recovery by detecting peak load conditions and automatically moving computing to another computing resource (and back) and by providing computing across two or more clouds and moving completely to one in the case of a disaster at one site. The system monitors loads within a datacenter and detects a threshold that indicates that the current load is nearing the datacenter's capacity. Upon detecting that the threshold will be reached, the system facilitates an orderly move of at least some datacenter load to another datacenter or cloud-based resources. The system can also be used as a disaster recovery architecture at a datacenter/network level to manage fast workload transition in case of disaster. Thus, the system allows enterprises to build smaller and more efficient datacenters that leverage other resources for rare extra loads.
    Type: Application
    Filed: May 20, 2011
    Publication date: November 22, 2012
    Applicant: Microsoft Corporation
    Inventors: Eric B. Watson, Alireza Farhangi, Kannan C. Iyer
  • Publication number: 20120272093
    Abstract: A method for providing fault-tolerant network communications between a plurality of nodes for an application, including providing a plurality of initial communications pathways over a plurality of networks coupled between the plurality of nodes, receiving a data packet on a sending node from the application, the sending node being one of the plurality of nodes, the data packet being addressed by the application to an address on one of the plurality of nodes, and selecting a first selected pathway for the data packet from among the plurality of initial communications pathways where the first selected pathway is a preferred pathway.
    Type: Application
    Filed: July 2, 2012
    Publication date: October 25, 2012
    Applicant: Microsoft Corporation
    Inventors: Michael T. Massa, Rudolf Opavsky, David A. Dion
  • Publication number: 20120266046
    Abstract: An apparatus, system, and method are disclosed for storing information in a storage device that includes multi-level memory cells. The method involves storing data that is written to the storage device in the LSBs of the multi-level memory cells, and storing audit data in the MSBs of the multi-level memory cells. The audit data can be read separately from the data and used to determine whether or not there has been any unintended drift between states in the multi-level cells. The audit data may be used to correct data when the errors in the data are too numerous to be corrected using error correction code (ECC). The audit data may also be used to monitor the general health of the storage device. The monitoring process may run as a background process on the storage device. The storage device may transition the multi-level memory cells to operate as single-level memory cells.
    Type: Application
    Filed: June 22, 2012
    Publication date: October 18, 2012
    Applicant: FUSION-IO
    Inventors: Jonathan Thatcher, David Flynn, Ethan Barnes, John Strasser, Robert Wood, Michael Zappe
  • Publication number: 20120260150
    Abstract: Methods and apparatus are provided for controlling data management operations including storage of data in solid state storage of a solid state storage system. Input data is stored in successive groups of data write locations in the solid state storage. Each group comprises a set of write locations in each of a plurality of logical subdivisions of the solid state storage. The input data to be stored in each group is encoded in accordance with first and second linear error correction codes. The encoding is performed by constructing from the input data to be stored in each group a logical array of rows and columns of data symbols. The rows and columns are respectively encoded in accordance with the first and second linear error correction codes to produce an encoded array in which all rows correspond to respective first codewords and columns correspond to respective second codewords.
    Type: Application
    Filed: December 16, 2010
    Publication date: October 11, 2012
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Roy D. Cideciyan, Evangelos S. Eleftheriou, Robert Haas, Xiao-Yu Hu, Ilias Iliadas, Thomas Mittelholzer
  • Publication number: 20120239993
    Abstract: The present invention provides various circuits for injecting faults into a larger circuit, sometimes called circuit under test, or CUT. One type of fault injection circuit is a clock controlled fault injection circuit. This type of circuit uses internal scan chains as a way by which a fault injection operation is performed while a system clock is in the off state. Another type of fault injection circuit is a concurrent fault injection circuit. This type of fault injection circuit uses dedicated fault injection scan chains in parallel with or without internal scan chains. Yet another type of fault injection circuit is a hybrid fault injection circuit that uses both clock controlled and concurrent fault injection circuits. Other embodiments are disclosed and still other embodiments would be obvious to those of ordinary skill in the art upon understanding the full scope of the present disclosure.
    Type: Application
    Filed: March 17, 2011
    Publication date: September 20, 2012
    Applicant: EIGENIX
    Inventor: Sung Soo Chung
  • Publication number: 20120240006
    Abstract: A method and system for storing data in a multi-level cell (MLC) flash memory device are described. The method includes receiving data for storage in the flash memory device, the flash memory device comprising an array of MLC flash memory cells, and encoding the received data into non-binary symbols according to a trellis-coded modulation scheme. The method further includes writing each of the non-binary symbols to a respective flash memory cell set, wherein each flash memory cell set comprises a plurality of MLC flash memory cells.
    Type: Application
    Filed: May 27, 2011
    Publication date: September 20, 2012
    Applicant: STEC, Inc.
    Inventors: Xinde Hu, Anthony D. Weathers, Richard D. Barndt
  • Publication number: 20120233496
    Abstract: Embodiments are directed to establishing a fault tolerant parallel database system and to detecting the health of parallel database services. In an embodiment, a computer system establishes a control node cluster that includes at least one active control node and at least one spare control node. Each node of the control node cluster includes specific functions assumable only by other control nodes. The computer system also establishes a compute node cluster that includes at least one active computing node, at least one spare computing node, at least one active storage node and at least one spare storage node. Each of the computing and storage nodes includes specific functions assumable only by other computing and storage nodes. The computer system detects a failure of an active node and instantiates a corresponding spare node that is configured to perform the functions of the failed active node.
    Type: Application
    Filed: March 11, 2011
    Publication date: September 13, 2012
    Applicant: MICROSOFT CORPORATION
    Inventors: German A. Gil, Yunsheng He, Dale S. Grinnell, Paul Herman Dyke, Subhankar Aich, Ruwen Henning Hess
  • Publication number: 20120226963
    Abstract: Bad block management for flash memory including a method for storing data. The method includes receiving a write request that includes write data. A block of memory is identified for storing the write data. The block of memory includes a plurality of pages. A bit error rate (BER) of the block of memory is determined and expanded write data is created from the write data in response to the BER exceeding a BER threshold. The expanded write data is characterized by an expected BER that is lower than the BER threshold. The expanded write data is encoded using an error correction code (ECC). The encoded expanded write data is written to the block of memory.
    Type: Application
    Filed: March 4, 2011
    Publication date: September 6, 2012
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: John A. Bivens, Michele M. Franceschini, Ashish Jagmohan
  • Patent number: 8249728
    Abstract: Methods for operating a management system that manages a large number of first function modules and second function modules. An inhibitor module I sets first control statuses to designating blocking when associated events are detected by an event detecting device, and then the management system no longer makes associated first function modules available for execution. The inhibitor module I sets second control statuses to designating executable when associated events are detected by an event detecting device, and then the management system makes associated second function modules available for execution.
    Type: Grant
    Filed: September 13, 2005
    Date of Patent: August 21, 2012
    Assignee: Robert Bosch GmbH
    Inventors: Bernd Kesch, Hans Hillner, Matthias Knirsch, Alexander Hinz