Abstract: A parallel processing system includes at least three parallel processors, state monitoring circuitry, and state reload circuitry. The state monitoring circuitry couples to the at least three parallel processors and is configured to monitor runtime states of the at least three parallel processors and identify a first processor of the at least three parallel processors having at least one runtime state error. The state reload circuitry couples to the at least three parallel processors and is configured to select a second processor of the at least three parallel processors for state reload, access a runtime state of the second processor, and load the runtime state of the second processor into the first processor. Monitoring and reload may be performed only on sub-systems of the at least three parallel processors. During reload, clocks and supply voltages of the processors may be altered. The state reload may relate to sub-systems.

Abstract: A storage device includes a main system; a power loss protection integrated circuit (PLP IC) configured to provide output power to the main system based on external or internal power; and an auxiliary power supply configured to provide the internal power to the PLP IC. The main system may operate in a dump mode where data is backed up in response to at least one of a first condition or a second condition being satisfied. The PLP IC may provide the output power based on the internal power in response to a sudden power off (SPO) occurring. The first condition is satisfied when the SPO occurs and an SPO time is longer than a maximum filtering time. The second condition is satisfied when the SPO occurs and a voltage level of the internal power provided by the auxiliary power supply is lower than a voltage level of a threshold voltage.

Abstract: A method and a device are provided. The device includes a first memory, a second memory having a storage characteristic different from that of the first memory, and a processor operatively connected to at least one of the first memory and the second memory. The processor is configured to generate a logical storage area in a data area of the first memory, store designated data in the generated logical storage area, and enter a recovery mode to store the data stored in the logical storage area in the second memory, format the first memory, and move the data stored in the second memory to the data area of the first memory.

Abstract: A control apparatus for a NAND flash memory device according to an embodiment includes a NAND flash memory; a controller configured to generate a command signal to program, read, and erase data in the NAND flash memory; and an auxiliary power circuit configured to maintain power for operating the memory and the controller during a first time from a first time point when a voltage of a supply power is less than a preset voltage, wherein the controller is configured to block the command signal during the first time, and wherein power supplied to the memory is blocked for at least a second time from a second time point after the first time.

Abstract: Systems, methods, and computer readable media for auto-recovery of an augmented reality (AR) wearable device are disclosed. A pass-through application is invoked as a background process and an application is invoked as a foreground process. The pass-through application includes an on-resume procedure that is called if the operating system or interpreter determines that the foreground process is unresponsive. The on-resume procedure restarts the application as the foreground process and may first reboot the AR wearable device. The pass-through application remains transparent to the user by not displaying output on the display of the AR wearable device. Additionally, an uncaught exception handler is registered with the operating system to be called in the event that an exception occurs that does not have a handler. The exception handler restarts the application as the foreground process and may first reboot the AR wearable device.

Abstract: The present disclosure relates to systems and methods for power outage protection. The system may obtain a read/write signal of each of a plurality of storage devices. For each of the plurality of storage devices, the system may identify a state of the storage device based on the read/write signal of the storage device. The state of the storage device may include a read/write state or an idle state of the storage device. In response to an interruption of power supply to the plurality of storage devices, the system may selectively provide electric power to the plurality of storage devices using a power source based at least partially on the states of the plurality of storage devices.

Abstract: Various embodiments include a parallel processing computer system that detects memory errors as a memory client loads data from memory and disables the memory client from storing data to memory, thereby reducing the likelihood that the memory error propagates to other memory clients. The memory client initiates a stall sequence, while other memory clients continue to execute instructions and the memory continues to service memory load and store operations. When a memory error is detected, a specific bit pattern is stored in conjunction with the data associated with the memory error. When the data is copied from one memory to another memory, the specific bit pattern is also copied, in order to identify the data as having a memory error.

Abstract: A kexec-based system update process wherein user-specific data is transferred on reboot of the second kernel. Upon initializing kexec load, buffer memory is assigned to the second kernel and the system loads control pages of fixed size for the second kernel boot, and also loads user-specific data onto extended control pages of variable size. Upon boot of the second kernel, the user-specific data is extracted from the extended control pages and transferred to the corresponding applications.

Abstract: A signal receiving circuit receives a reset configuration signal from an exceptional timing sequence device in a functional module and outputs a trigger signal. A first signal generation circuit generates an idle signal based at least in part on the trigger signal. The idle signal is used to configure a shutdown signal which in turn is used to shut down a first clock signal of the exceptional timing sequence device and a second clock signal in a same clock domain as the first clock signal. A second signal generation circuit generates a reset enable signal based at least in part on the trigger signal. An operational circuit performs an operation based at least in part on the reset enable signal and generates a module-based reset signal based at least in part on an operation result. The module-based reset signal is used to reset the exceptional timing sequence device in the functional module.

Abstract: Nonvolatile data storage systems, methods, and devices are disclosed. In one example, a nonvolatile storage device includes a volatile memory, a controller electrically coupled to the volatile memory, a nonvolatile memory electrically coupled to the controller, and a backup power source electrically coupled to the controller, the volatile memory, and the nonvolatile memory. The controller is configured to read and write primary data from a primary host and mirrored data from a secondary host in the volatile memory. The backup power source is configured to store sufficient energy to power the nonvolatile storage device during a backup operation. The controller is configured to, in response to a backup signal, copy the primary data and the mirrored data stored in the volatile memory to the nonvolatile memory.

Abstract: Memory regions may be protected based on occurrence of an event in a computing device. Subsystems of the computing device may store information in a memory controller identifying memory regions to be erased upon occurrence of an event, such as a system or subsystem crash. The memory controller may control erasing the memory regions in response to an indication associated with the event. A memory dump may be performed after the memory regions have been erased.

Abstract: A Data Storage Device (DSD) includes at least one Non-Volatile Memory (NVM) configured to store data and a Non-Volatile Cache (NVC). Write data is stored in a volatile memory in preparation for writing the write data in the at least one NVM. In response to a power loss of the DSD, at least a portion of the data stored in the volatile memory is transferred from the volatile memory to the NVC and one or more parameters are determined for deriving a margin representing an additional amount of data for transfer from the volatile memory to the NVC using a remaining power following a power loss. A size of the NVC is adjusted based at least in part on the derived margin.

Abstract: A vehicle system having: a hardware level, a first operating system, and a virtual machine integrated on the hardware level having a second operating system. A hypervisor operates the virtual machine such that the first and the second operating systems) are operated in parallel on the hardware. A first application is executed on the first operating system and a second application is executed on the second operating system. The first application has a higher safety standard than the second application. The second operating system is configured to be operated in suspend-to-RAM mode while the first operating system is switched off.

Abstract: A computer-based system and method for providing a distributed write buffer in a storage system, including: obtaining a write request at a primary storage server to store data associated with the write request in a non-volatile storage of the primary storage server; and storing the data associated with the write request in a persistent memory of the primary storage server or in a persistent memory of an auxiliary storage server based on presence of persistent memory space in the primary storage server. The write request may be acknowledged by the primary storage server after storing the data associated with the write request in the persistent memory of the primary storage server or in the persistent memory of the auxiliary storage server.

Abstract: A method for determining the integrity of navigation data of a control unit of an automotive vehicle, including the steps involving setting two counters to a value strictly above the maximum of the two counters, and, in a waking phase, calculating the fingerprints of the data written to the reset safe area, comparing the counters and determining the integrity of the data when the counters are the same.

Abstract: A block family associated with a memory device is initialized. An initial value of a power cycle count associated with the memory device is stored. Responsive to programming a block residing in the memory device, the block is associated with the block family. Responsive to determining that a current value of the power cycle count exceeds the initial value of the power cycle count, the block family is closed. Responsive to determining that a time period that has elapsed since initializing the block family exceeds a threshold period, the block family is closed.

Abstract: A data storage device may include a nonvolatile memory device, and a controller configured to increase an assert count, when a malfunction occurs while an operation for a command received from a host device is executed, the assert count representing the number of times the malfunction has occurred, and execute a flash translation layer (FTL) resetting operation in a read-dedicated mode in response to an initialization request from the host device when the assert count is greater than or equal to a reference value.

Abstract: A performance enhancing solution can be executed on a computing device to detect changes in the foreground application. When the foreground application changes, the performance enhancing solution can adjust the allocation of system resources to running applications to thereby enhance the performance of the foreground application.

Abstract: An electronic device includes an application processor; and a first storage device that is, connected to the application processor and directly communicates with the application processor, and connected to a second storage device such that the second storage device communicates with the application processor through the first storage device, wherein the first storage device includes a reset converter configured to generate a software reset signal in response to a hardware reset signal received from the application processor, and wherein the software reset signal resets the second storage device.

Abstract: A control device for controlling equipment or a machine includes: one or more processors, a general-purpose OS and a real-time OS executed in parallel on the one or more processors, and an input interface that receives a cutoff event from outside, wherein the real-time OS provides an execution environment of a user program for realizing control over the equipment or machine. The real-time OS has a function of executing a shutdown preparation process required for shutdown of the real-time OS in response to the cutoff event; a function of instructing the general-purpose OS to shut down after executing the shutdown preparation process; and a function of completing the shutdown of the real-time OS and cutting off power supply of the control device when a predetermined condition is satisfied, wherein the predetermined condition includes receipt of a notification of shutdown completion from the general-purpose OS.

Abstract: A method, computer readable medium, and system independently managing network applications within a network traffic management device communicating with networked clients and servers include monitoring with a network device a plurality of applications communicating over a plurality of direct memory access (DMA) channels established across a bus. The network device receives a request from a first application communicating over a first DMA channel in the plurality of DMA channels to restart the first DMA channel. In response to the request, the first DMA channel is disabled with the network device while allowing other executing applications in the plurality of applications to continue to communicate over other DMA channels in the plurality of DMA channels. A state of the first DMA channel is cleared independently from other DMA channels in the plurality of DMA channels, and communications for the first application over the first DMA channel are resumed with the network device.

Abstract: Various embodiments are described herein with regards to performing a selective fault recovery for an electronic device having a plurality of subsystems in which one of the subsystems has a fault. The selective fault recovery techniques described herein allow a user to use non-faulty subsystem of the electronic device while selective fault recovery is being conducted on the subsystem having the fault.

Abstract: A data processing apparatus executes instructions in a sequence of pipelined execution stages. An error detection unit twice samples a signal associated with execution of an instruction and generates an error signal if the samples differ. An exception storage unit maintains an age-ordered list of entries corresponding to instructions issued to the execution pipeline and can mark an entry to show if the error signal has been generated in association with that instruction. A timer unit is responsive to generation of the error signal to initiate timing of a predetermined time period. An error recovery unit initiates a soft pipeline flush procedure if an oldest pending entry in the list has said error marker stored in association therewith and initiates a hard pipeline flush procedure if said predetermined time period elapses, said hard flush procedure comprising resetting said pipeline to a predetermined state.

Abstract: In a storage system for performing data backup using a battery during blackout, when the blackout continues for a long time, problems such as the loss of volatile memory data due to the consumption of battery capacity and the difference in recovery time between controller units after power recovery occur during restarting of the system. The present invention solves the problems by selecting (a1) battery backup or (a2) saving of data in a nonvolatile device based on the battery capacity or setting of modes, and selecting (b1) inhibiting restart of the system or (b2) storing of data in the volatile memory to a nonvolatile memory means and performing access via write-through based on the remaining capacity of the battery when restarting the system after power recovery. Further, the system enables to increase and decrease the volatile memory capacity of the write area and mutually confirms synchronization of controller units and contents of volatile memories.

Abstract: Storage system arrangement wherein: when a transmission destination determines that a source-side serial number included in a received packet is the same as a current destination-side serial number in the transmission destination, the transmission destination processes a content of the received packet in accordance with a command included in the received packet; and when the transmission destination determines that the source-side serial number is not the same as the current destination-side serial number, the transmission destination does not process a content of the received packet.

Abstract: A method for the generation of a set of conflicts for model-based system diagnostics is described, with which system a plurality of sensors is associated for the observation of variables indicative of operation conditions. The method starts from generating a complete set of Analytical Redundancy Relations (ARRs) in implicit form and, for each diagnosis instance: it performs a system simulation, computing the expected values for a first subset of Analytical Redundancy Relations (D-ARRs) including the relations involving only one system observation variable; it compares the expected and observed values of the system observation variables to identify the inconsistent variables, i.e.

Abstract: A system and a method for handling a system failure are disclosed. The method is adapted for an information handling system having a basic input and output system and a micro-controller. The method includes the following steps: sending, via the micro-controller, a signal; checking, via the micro-controller, whether an acknowledgement is received from the basic input and output system responsive to the signal; and scanning, via the micro-controller, a type of a system failure in response to the acknowledgement being not received.

Abstract: A computer system including a first processor, an error detecting circuit and a south bridge chip is provided. The first processor outputs a first catastrophic error signal. The error detecting circuit is coupled to the first processor to receive the first catastrophic error signal. When the first catastrophic error signal changes to a first level and is maintained for a period exceeding a first predetermined time, the error detecting circuit outputs an internal error reset signal. When the first catastrophic error signal changes to a first level and passes a second predetermined time, the error detecting circuit outputs a machine error reset signal. Here, the second predetermined time is greater than the first predetermined time. The south bridge chip is coupled to the error detecting circuit and reboots the computer system according the internal error reset signal or the machine error reset signal.

Abstract: A method for managing operating system deployment failure includes, with an operating system deployment server, running an operating system deployment process that comprises running a progressive hardware discovery process of a target machine to which an operating system is deployed, the discovery process to capture inventory information related to the target machine, monitoring the operating system deployment to detect failure in a pre-operating system environment running on the target machine for a predefined period of time, and executing a remediation action in response to generation of a failure code during the period of time, the remediation action related to a Basic Input Output System (BIOS) of the target machine.

Abstract: Various embodiments include a software provisioning system and method for a vehicle infotainment computer. Software provisioning of the vehicle infotainment computer may occur during vehicle assembly. A software provisioning request may be received for custom installing software to the vehicle infotainment computer. The custom install may be based on a customization schedule which may include a location identifier (such as uniform resource identifiers or file paths) for locating the software. In response to the request, the software may be located on a provisioning server or a portable memory device based on the customization schedule. The software may be transmitted to memory of the vehicle infotainment computer and custom installed on the vehicle infotainment computer.

Abstract: Provided is a RAID controlled storage device of a PCI-Express (PCI-e) type, which provides data storage/reading services through a PCI-Express interface. The RAID controller typically includes a disk mount coupled to a set of PCI-Express SSD memory disk units, the set of PCI-Express SSD memory disk units comprising a set of volatile semiconductor memories; a disk monitoring unit coupled to the disk mount for monitoring the set of PCI-Express memory disk units; a disk plug and play controller coupled to the disk monitoring unit and the disk mount for controlling the disk mount; a high speed host interface coupled to the disk monitoring unit and the disk mount for providing high-speed host interface capabilities; a disk controller coupled to the high speed host interface and the disk monitoring unit; and a host interface coupled to the disk controller.

Abstract: Described herein are a method, system, and computer readable medium for resetting a subsystem of a communication device. The method involves utilizing a subsystem error handler to generate a reset request signal indicating the subsystem has experienced an exception; distributing to a software component, residing externally to the subsystem, a status message indicative of a current state of the subsystem; performing a reset of the subsystem in response to the reset request signal; and rebooting the subsystem. When the subsystem can be reset without performing a system wide reset of the communication device, communication device downtime is reduced, which facilitates a positive user experience.

Abstract: A failover control method for a virtual computer system including a plurality of virtual computers including: monitoring a second virtual computer via a first line by a first virtual computer among the plurality of virtual computers; detecting a malfunction of the second virtual computer by the first virtual computer; receiving from the other virtual computers a notification including a monitoring result for the second virtual computer in the other virtual computers among the plurality of virtual computers by the first virtual computer; relating the monitoring result to the detected malfunction of the second virtual computer to correspond to each other; judging whether or not the correspondence between the monitoring result and the detected malfunction of the second virtual computer satisfies a predetermined condition; and giving the second computer a reset instruction via a second line, when the predetermined condition is satisfied.

Abstract: The disclosed embodiments provide a system that configures a battery for a computer system. During operation, the system disconnects the battery by simulating a fault condition using a safety circuit of the battery. The fault condition may be simulated to facilitate safe assembly of a computer system containing the battery. After assembly is complete, the system enables use of the battery in the computer system by applying external power to the computer system, which resets the safety circuit and reconnects the battery.

Abstract: An I/O processor determines whether or not the amount of dirty data on a cache memory exceeds a threshold value and, if the determination is that this threshold value has been exceeded, writes a portion of the dirty data of the cache memory to a storage device. If a power source monitoring and control unit detects a voltage abnormality of the supplied power, the power monitoring and control unit maintains supply of power using power from a battery, so that a processor receives supply of power from the battery and saves the dirty data stored on the cache memory to a non-volatile memory.

Abstract: A computer system including a plurality of PCIe paths is configured such that a failed PCIe path only is disabled, thereby preventing the computer system from system resetting. The computer comprises a root port for detecting a failure on a PCIe path, and then for issuing a SMI (System Maintenance Interrupt) to a CPU; and the CPU for, on the receipt of the SMI, executing BIOS to issue, through the root port, a PCIe reset to the PCIe path on which the failure has occurred.

Abstract: An information processing apparatus having a resume function which can maintain the security even when a plurality of users commonly use the apparatus. A work state at a power-off time of the apparatus is preserved together with a work state name including a user's ID in a different area in a plurality of preservation areas for resume function on a main memory for each user. When a power source is again turned on, data in the preservation area corresponding to the user's ID is used to reproduce the work state of the user at the power-off time. The work preservation areas can be provided on a file server apparatus in a network not needing battery back-up. When the information processing apparatus is used, a work state at a power-off time can be independently preserved and reproduced for each user.

Abstract: A reset signal generation circuit for generating a reset signal synchronously or asynchronously to a clock signal in accordance with an operation state. An operation detection circuit detects operation of a CPU and generates an operation detection signal. A signal control circuit generates a first reset signal synchronously or asynchronously to an internal clock signal based on the operation detection signal and a system reset signal. The first reset signal is provided to synchronous circuits including the CPU.

Abstract: A control device and a control method for increasing stability of micro controller system are described. The control device comprises a system error detection unit a memory unit, a data error detection unit, an error signal processing unit and a system resetting unit. When the system is error or the data transferred from the memory unit has error, the system error detection unit or the data error detection unit outputs an error signal to the error signal processing unit, and then the error signal processing unit corrects the error data or commands the system resetting unit to reset the system by the error signal for increasing the system stability.