Abstract: A multiplexer device that is operable to generate from one or more input channels a multiplexed output signal. When generating the multiplexed output signal the multiplexing circuit is configured to encode the measurement values for the plurality of input channels from which input signals were provided to the multiplexer device into the multiplexed output signal in such a manner that respective measurement values from different ones of the plurality of input channels can be identified directly from the multiplexed output signal.

Abstract: A system for detecting errors and correcting errors in a multi-thread processor is disclosed. The multi-thread processor includes a first processor and a second processor. First processor executes a first thread and a second thread. Second processor executes a third thread and fourth thread. An instruction execution is initiated in all four threads. Output of the instruction execution from all four threads are compared for a match by a data compare engine to detect an error in execution of the instruction. When output of the instruction execution from one of the four threads does not match, an error in execution is detected and the output is replaced by one of the other three threads whose output does match. When output of the instruction execution by two or more threads does not match, error is detected, but not corrected.

Abstract: An integrated circuit 114 includes processing pipeline circuitry 40 comprising a plurality of pipeline stages 44, 46, 48 separated by respective signal value storage circuitry 48, 50, 52. Timing detection circuitry 54, 56, 58 coupled to the processing pipeline circuitry serves to detect as timing violations any signal transitions arrive at the signal value storage circuits outside respective nominal timing windows. Error detection circuitry 66 triggers an error correcting response if the timing detection circuitry indicates a predetermined pattern comprising a plurality of timing violations spread over a plurality of clock cycles of a clock signal CK controlling the processing pipeline circuitry. The predetermined pattern may be two consecutive timing violations.

Abstract: This invention concerns the transmitting and receiving of digital media packets, such as audio and video channels and lighting instructions. In particular, the invention concerns the transmitting and receiving of redundant media packet streams. Samples are extracted (556) from a first (904) and second (906) media packet stream. The extracted samples are written to a buffer (910) based on the output time of each sample (556). Extracted samples having the same output time are written to the same location in the buffer. Both media packet streams are simply processed all the way to the buffer without any particular knowledge that one of the packet streams is actually redundant. This simplifies the management of the redundant packet streams, such as eliminating the need for a “fail-over” switch and the concept of an “active stream”, The location is the storage space allocated to store one sample.

Abstract: For an error rate QBER, threshold values are preset, including a threshold value Qbit for frame synchronization processing, a threshold value Qphase for phase correction processing, and a threshold value QEve for eavesdropping detection. Upon the distribution of a quantum key from a sender to a receiver, when the measurement value of QBER is deteriorated more than Qbit, frame synchronization processing is performed. When the measurement value of QBER is deteriorated more than Qphase, phase correction processing and frame synchronization processing are performed. When QBER does not become better than QEve even after these recovery-processing steps are repeated N times, it is determined that there is a possibility of eavesdropping, and the processing is stopped.

Abstract: An access control apparatus includes a memory and a command executor executing an access process on a command with the command completion time limit. An address of an inaccessible recording area is stored in the memory. Data attempted to be written on the inaccessible recording area is obtained. The data is stored in association with the address in the memory. An automated alternate processor executes the automated alternate process of the inaccessible recording area in a predefined period of time after the process executed by the command executor is completed. A memory updater deletes the address of the inaccessible recording area whose automated alternate process has succeeded and the data attempted to be written in the recording area at the address.