Abstract: One embodiment of the present invention provides a system that uses performance parameters to predict a computer system failure. The system operates by evaluating a performance-parameter rule on a target system to determine if a corresponding performance parameter is within a predetermined range. Note that the performance parameter defines a performance metric for software, including an operating system, executing on the computer system. Note that the performance parameter may also define a performance metric for hardware and networks, and can come from other sources such as vendor-internal records. The system also receives an evaluation result of the performance-parameter rule from the target system. Next, the system records the evaluation result in a historic data set. The system then determines if the target system failed within a pre-determined time period subsequent to the evaluation of the performance-parameter rule. If so, the system records the failure of the target system in the historic data set.

Abstract: A system for validating communications between a plurality of processors is disclosed. The system includes a plurality of loop back paths, and each of the loop back paths is coupled to a corresponding one of the plurality of processors. In addition, each loop back path is configured to attenuate one of a plurality of signals transmitted from each of the corresponding ones of the plurality of processors so as to generate a plurality of loop back signals. A plurality of signal transmission paths are configured to carry a corresponding one of the plurality of signals from one of the plurality of processors to another of the plurality of processors, and a plurality of comparators compare the plurality of loop back signals to the plurality of transmission signals so as to enable the validity of each of the plurality of signals to be assessed.

Abstract: This invention provides a semiconductor test system including a test pattern generating portion for generating a test pattern data including a test signal for testing a device under test, at a predetermined timing, a driver for inputting the test pattern data generated by the test pattern generating portion into the device under test by way of a transmission line, and an adjustment DA converter for setting a voltage value of a high level or a low level signal inputted by the driver, to a voltage value of an adjustment high level or an adjustment low level adjusted in accordance with a characteristic of the transmission line.

Abstract: A data transmission speed test system is provided. The system includes a computer. The computer is configured for reading data stored in a database and transmitting the data to a target device. The computer is further configured for testing data transmission speeds at regular time intervals and dynamically displaying the data transmission speeds, such as a maximal speed, a minimal speed and an average speed at different time on a display device, during the whole data transmission process. A related method is also provided.

Abstract: Example embodiments of the present invention include a memory device testable without using data and a dataless test method. The memory device includes a plurality of registers to store test patterns, the registers being coupled to input/output DQ pads. The test patterns are stored in the registers when a mode register of the memory device is set. The memory device transfers the test patterns to a DQ pad responsive to a write test signal, and transfers the test patterns from the DQ pad to a data input buffer responsive to a read test signal. The memory device writes the test patterns transferred to the data input buffer to memory cells. The memory device reads data stored in the memory cells responsive to the write test signal and transfers the memory cell data from the DQ pad to a comparator responsive to the read test signal. The memory device compares the test patterns to the memory cell data transferred to the comparator and generates an indicator signal to indicate the comparison result.

Abstract: Error detection circuitry is provided on a programmable logic resource. Programmable logic resource configuration data is loaded into a cyclic redundancy check (CRC) module where a checksum calculation may be performed. In one embodiment, the checksum may be compared to an expected value, which is a precomputed checksum on data prior to being programmed into or while data is being programmed into a programmable logic resource. In another embodiment, the expected value may be included in the checksum calculation. An output indicating whether an error is detected may be generated depending on the relationship between the checksum and the expected value, or on the value of the checksum. This output may be sent to an output pin that is accessible by user logic.

Abstract: A memory card has a plurality of non-volatile memories and a main controller for controlling the operation of the non-volatile memories. The main controller performs an access control to the non-volatile memories in response to an external access instruction, and an alternate control for alternating an access error-related storage area of the non-volatile memory with other storage area. In the access control, the speeding up of the data transfer between flash memories is achieved by causing the plurality of non-volatile memories to parallel access operate. In the alternation control, the storage areas is made alternative for each non-volatile memory in which an access error occurs.

Abstract: Each memory chip of a memory module tests a total of N data bits from X memory blocks for efficient testing and outputs N/X data bits from one of the memory blocks. A memory module includes a plurality of memory chips and a plurality of comparison units. Each comparison unit is disposed within a respective memory chip for testing a plurality of data bits from a plurality of memory blocks. In addition, each comparison unit outputs data bits from one of the memory blocks within the respective memory chip.