Logging Of Test Results (epo) Patents (Class 714/E11.147)
  • Publication number: 20140068325
    Abstract: A computer-implemented method for test case result processing includes receiving, by a test case result processing logic in a processor of a computer, a test result from a test case that executes on the computer; determining, by the test case result processing logic based on a result description file, whether a result description corresponding to the received result exists in the result description file; based on the result description corresponding to the received result existing in the result description file, determining an action description associated with the result description based on an action definition file; and executing an action corresponding to the determined action description.
    Type: Application
    Filed: August 30, 2012
    Publication date: March 6, 2014
    Inventors: Joel L. Masser, David C. Reed, Max D. Smith
  • Publication number: 20130179732
    Abstract: An approach is provided in which a network hardware adapter stores offload information in a shared memory area that is located on a host system. The offload information includes connection information that was offloaded to the network hardware adapter by an application executing on the host system. An operating system (e.g., a network device driver) detects a network adapter error corresponding to the network hardware adapter and, in turn, retrieves the offload information stored in the shared memory area. As such, an analysis application utilizes the retrieved offload information to debug the network adapter error.
    Type: Application
    Filed: January 5, 2012
    Publication date: July 11, 2013
    Applicant: International Business Machines Corporation
    Inventors: Francisco Jesus Alanis, Omar Cardona, Jeffrey Paul Messing
  • Publication number: 20130103982
    Abstract: A compression system identifies one or more fields in a log file based on at least one field rule from among multiple field rules specified in a log file framework. The compression system extracts contents of the log file associated with the one or more fields. The compression system passes the contents associated with the one or more fields to corresponding compression engines from among a multiple compression engines each specified for performing a separate type of compression from among multiple types of compression for each of the one or more fields, wherein each of the one or more fields corresponds to one or more compression engines from among the multiple compression engines.
    Type: Application
    Filed: October 25, 2011
    Publication date: April 25, 2013
  • Publication number: 20120254667
    Abstract: Core dump is performed over a network without relying on network device drivers. Instead of network device drivers, firmware of network devices that is typically used during boot is preserved in memory post-boot, and one or more application program interfaces of the firmware are invoked to perform the network core dump. For ease of implementation, a network bootstrap program that has standard application program interfaces for calling into the firmware of network devices may be invoked when performing core dump over the network.
    Type: Application
    Filed: April 1, 2011
    Publication date: October 4, 2012
    Applicant: VMWARE, INC.
    Inventors: Ronghua ZHANG, Saleem ABDULRASOOL, Mallik MAHALINGAM, Boon Seong ANG
  • Publication number: 20120151263
    Abstract: Embodiments include methods for performing various operations in a computing system that includes an electronic module and a debug circuit. The method includes programming the debug circuit to monitor for pre-selected triggers produced by the computing system, and to perform actions in response to detecting the pre-select triggers. For example, in response to various pre-selected triggers, the debug circuit may, among other things: perform state transitions and log information indicating whether or not the state transitions were performed; monitor various signals when the debug circuit has determined that a test escape has occurred; and/or perform one or more actions that initiate stopping one or more clocks in response to certain pre-selected triggers.
    Type: Application
    Filed: April 27, 2011
    Publication date: June 14, 2012
    Inventors: Eric M. RENTSCHLER, Steven J. KOMMRUSCH, Scott NIXON
  • Publication number: 20120144253
    Abstract: A technique for managing hard failures in a memory system employing a locking is disclosed. An error count is maintained for units of memory within the memory system. When the error count indicates a hard failure, the unit of memory is locked out from further use. An arbitrary set of error counters are assigned to record errors resulting from access to the units of memory. Embodiments of the present invention advantageously enable a system to continue reliable operation even after one or more internal hard memory failures. Other embodiments advantageously enable manufacturers to salvage partially failed devices and deploy the devices as having a lower-performance specification rather than discarding the devices, as would otherwise be indicated by conventional practice.
    Type: Application
    Filed: December 7, 2010
    Publication date: June 7, 2012
    Inventors: Miguel Comparan, Mark G. Kupferschmidt, Robert A. Shearer
  • Publication number: 20120036404
    Abstract: A control apparatus controlling testing of a memory under test that includes one or more row repair memory blocks and column repair memory blocks. The control apparatus comprises a counting section that sequentially receives test results respectively indicating pass/fail of a plurality of test blocks of the memory under test, and sequentially counts, for each first-type memory block, which is a row-oriented memory block or a column-oriented memory block, a fail memory block number among second-type memory blocks; a selecting section that selects memory blocks first-type memory blocks for which the fail memory block number exceeds a reference value, such that the number of selected memory blocks is no greater than the number of first-type repair memory blocks of the memory under test; and a test control section that masks test blocks among the memory blocks selected by the selecting section and causes further testing of the memory under test.
    Type: Application
    Filed: August 18, 2011
    Publication date: February 9, 2012
    Inventor: Makoto TABATA
  • Publication number: 20110320892
    Abstract: A system and computer implemented method for isolating errors in a computer system is provided. The method includes receiving a direct memory access (DMA) command to access a computer memory, a read response, or an interrupt; associating the DMA command to access the computer memory, the read response, or the interrupt with a stream identified by a stream identification (ID); detecting a memory error caused by the DMA command in the stream, the memory error resulting in stale data in the computer memory; and isolating the memory error in the stream associated with the stream ID from other streams associated with other stream IDs upon detecting the memory error.
    Type: Application
    Filed: June 23, 2010
    Publication date: December 29, 2011
    Inventors: Mark A. Check, David F. Craddock, Thomas A. Gregg, Pak-kin Mak, Gary E. Strait
  • Publication number: 20110289364
    Abstract: An apparatus, and an associated method, reports when incidence of email or other data-message communication of a wireless network system. An analyzer analyzes logged information and determines the incidence, such as by calculating a ratio, of delayed versus timely message communications. If the ratio, or other indication, is beyond a threshold, a reporter generates a report to alert the high incidence of delayed communications.
    Type: Application
    Filed: May 21, 2010
    Publication date: November 24, 2011
  • Publication number: 20110264956
    Abstract: A management server includes a meta rule for identifying an event to be a root cause and a failure recovery method that corresponds to the meta rule for an event capable of occurring in a plurality of node apparatuses, and also displays a cause event to be a root cause of an event detected by the management server, and a method for recovering from this cause event.
    Type: Application
    Filed: July 16, 2009
    Publication date: October 27, 2011
    Inventors: Atsushi Ito, Nobuo Beniyama, Yuji Mizote, Takaki Kuroda
  • Publication number: 20110246842
    Abstract: Methods and apparatus are provided for approximating a probability density function or distribution for a received value in communication or storage systems. A target distribution is approximated for a received value in one or more of a communication system and a memory device, by substantially minimizing a squared error between the target distribution of the received values and a second distribution obtained by mapping a predefined distribution, such as a Gaussian distribution, through a mapping function, wherein the second distribution has an associated set of parameters. The mapping function can be, for example, a piecewise linear function. The second distribution has a plurality of segments and each of the segments has an associated set of parameters. The associated set of parameters can be used to compute probability values, soft data values or log likelihood ratios.
    Type: Application
    Filed: March 31, 2010
    Publication date: October 6, 2011
    Inventors: Erich F. Haratsch, Nenad Miladinovic, Andrei Vityaev
  • Publication number: 20110246826
    Abstract: Systems and methods of collecting and aggregating log data with fault tolerance are disclosed. One embodiment includes, one or more devices that generate log data, the one or more machines each associated with an agent node to collect the log data, wherein, the agent node generates a batch comprising multiple messages from the log data and assigns a tag to the batch. In one embodiment, the agent node further computes a checksum for the batch of multiple messages. The system may further include a collector device, the collector device being associated with a collector tier having a collector node to which the agent sends the log data; wherein, the collector determines the checksum for the batch of multiple messages received from the agent node.
    Type: Application
    Filed: September 8, 2010
    Publication date: October 6, 2011
    Applicant: Cloudera, Inc.
    Inventors: Jonathan Ming-Cyn Hsieh, Henry Noel Robinson
  • Publication number: 20110167308
    Abstract: A method and apparatus for multi-site testing of computer memory devices. An embodiment of a method of testing computer memory devices includes coupling multiple memory devices, each memory device having a serializer output and a deserializer input, wherein the serializer output of a first memory device is coupled with a deserializer input of one or more of the memory devices of the plurality of memory devices. The method further includes producing test signal patterns using a test generator of each memory device, serializing the test signal pattern at each memory device, and transmitting the serialized test pattern for testing of the memory devices, wherein testing of the memory devices includes a first test mode and a second test mode.
    Type: Application
    Filed: January 6, 2010
    Publication date: July 7, 2011
    Inventor: Chinsong Sul
  • Publication number: 20110083050
    Abstract: Embodiments of the present disclosure provide methods, devices, and systems for performing a programming operation on an array of non-volatile memory cells. One method includes programming a number of cells to a number of final data states. The method includes performing, prior to completion of, e.g., finishing, the programming operation, an erase state check on a subset of the number of cells, which were to be programmed to an erased state.
    Type: Application
    Filed: December 3, 2010
    Publication date: April 7, 2011
    Inventor: Seiichi Aritome
  • Publication number: 20100287427
    Abstract: Disclosed are a flash memory device and flash memory programming method that equalizes a wear-level. The flash memory device includes a memory cell array, an inversion determining unit to generate a programming page through inverting or not inverting a data page based on a number of ‘1’s and ‘0’s in the data page, a programming unit to store the generated programming page in the memory cell array; and a data verifying unit to read the programming page stored in the memory cell array, to restore the data page from the programming page according to whether an error exists in the read programming page, and to output the restored data page, and thereby can equalize a wear-level of a memory cell.
    Type: Application
    Filed: August 25, 2008
    Publication date: November 11, 2010
    Inventors: Bumsoo Kim, Hyunmo Chung, Hanmook Park
  • Publication number: 20100192029
    Abstract: In accordance with certain embodiments of the present disclosure, an information handling system is provided. The information handling system may include a plurality of processors, each processor comprising multiple cores, a memory system coupled to the plurality of processors, and a controller coupled to the plurality of processors. The controller may be configured to: receive a local system management interrupt (SMI) signal regarding an error associated with at least one of the multiple cores, determine that the received local SMI signal triggers a global SMI based on a global SMI trigger rule, cause the plurality of processors to enter a global system management mode (SMM), and log the error in a shared resource shared by the plurality of processors during the global SMM.
    Type: Application
    Filed: January 29, 2009
    Publication date: July 29, 2010
    Applicant: DELL PRODUCTS L.P.
    Inventors: Bi-Chong Wang, Vijay Nijhawan, Madhusudhan Rangarajan
  • Publication number: 20090259896
    Abstract: A bad block identifying method for a flash memory, a storage system, and a controller thereof are provided. The bad block identifying method includes determining whether a programming error occurs in a block of the flash memory after the block is programmed and marking the block as a bad block when the programming error successively occurs in the block. Since the block is determined to be a bad block only when the programming error repeatedly occurs in the block, misjudgment of bad block in the flash memory can be avoided and accordingly the lifespan of the flash memory storage system can be prolonged.
    Type: Application
    Filed: June 16, 2008
    Publication date: October 15, 2009
    Inventors: Chih-Jen Hsu, Yi-Hsiang Huang
  • Publication number: 20090249140
    Abstract: A method for managing defect blocks in a non-volatile memory essentially comprises the steps of detecting defect blocks in the non-volatile memory, storing addresses of the defect blocks in a table block of the non-volatile memory, and setting the non-volatile memory to be read-only if the quantity of defect blocks in the non-volatile memory exceeds a threshold and no free blocks remain in the non-volatile memory. In a preferred embodiment, the free pages in the defect block continue to be programmed before setting the non-volatile memory to be read-only.
    Type: Application
    Filed: March 27, 2008
    Publication date: October 1, 2009
    Inventors: Szu I. Yeh, Hsin Jen Huang, Chien Cheng Lin, Chia Hao Lee, Chih Nan Yen, Fuja Shone
  • Publication number: 20090235133
    Abstract: A system that generates test patterns for detecting transition faults in an integrated circuit (IC). During operation, the system receives slack times for each net in the IC. Note that a slack time for a net is the minimum amount of delay that the given net can tolerate before violating a timing constraint. For each possible transition fault in the IC, the system uses the slack times for nets in the IC to generate a test pattern which exposes the transition fault by producing a transition that propagates along the longest path to the transition fault.
    Type: Application
    Filed: May 21, 2009
    Publication date: September 17, 2009
    Applicant: SYNOPSYS, INC.
    Inventors: Rohit Kapur, Tom W. Williams, Cyrus Hay
  • Publication number: 20090063900
    Abstract: A log collecting system includes a computer apparatus and at least one peripheral apparatus connected to the computer apparatus, the computer apparatus collecting a log that records operation of the at least one peripheral apparatus. The peripheral apparatus includes, a first log memory controlling section that stores a first log relating to all operation of the at least one peripheral apparatus in a first log memory region, and a second log memory controlling section that stores, in a second log memory region, a second log indicative of any influence on the operation of the at least one peripheral apparatus among the first logs.
    Type: Application
    Filed: September 2, 2008
    Publication date: March 5, 2009
    Inventor: Akidi YOSHIDA
  • Publication number: 20090013218
    Abstract: Methods, systems and modules for datalog management. In one embodiment, the logging of data is allowed to at least occasionally occur while the handling equipment is preparing device(s) for testing. Additionally or alternatively, in one embodiment with a plurality of test site controllers, after testing has been completed at all test site(s) associated with a particular test site controller the logging of data relating to that test site controller is allowed to at least occasionally occur while testing is continuing at test site(s) associated with other test site controller(s).
    Type: Application
    Filed: July 2, 2007
    Publication date: January 8, 2009
    Applicant: Optimal Test Ltd.
    Inventors: Eran ROUSSEAU, Igal GURVITS, Reed LINDE, Gil BALOG
  • Publication number: 20080320336
    Abstract: A process executing on a computing system may encounter an exception. Pointers or other references created by the exception may identify portions of the computing system's memory containing the binary code that was executing at the time of the exception. The exception-causing code from the system memory may be compared to an original version of the code from a non-volatile source. If the comparison identifies a hardware corruption pattern, the computing system may communicate information about the process and the exception to an error analysis server. Using historical exception data, the error analysis server may determine if the identified corruption pattern is most likely the result of corrupt hardware at the computing system. If corrupt hardware was the most likely result of the exception, then the server may communicate with the computing system to recommend or initiate a hardware diagnostic routine at the computing system to identify the faulty hardware.
    Type: Application
    Filed: June 22, 2007
    Publication date: December 25, 2008
    Inventors: Haseeb Abdul Qadir, Kinshumann Kinshumann
  • Publication number: 20080320347
    Abstract: A method and apparatus for testing of integrated circuits using a Direct Memory Load Execute Dump (DMLED) test module. The method includes loading a test case into a memory using the DMLED test module, loading initialization signatures of fixed pattern into the memory using the DMLED test module, and executing the test case at an operating clock rate of a processor. The method further includes writing result signatures into the memory, and dumping the results signatures from the memory to a tester using the DMLED test module.
    Type: Application
    Filed: June 9, 2008
    Publication date: December 25, 2008
    Applicant: Texas Instruments Incorporated
    Inventors: Pascal Cussonneau, Eric Bernillon
  • Publication number: 20080263417
    Abstract: Memory array built in self testing utilizing including a simple data history table. The table is used to track failing locations observed during any level of assembly test of processor or logic semiconductor chips where the chips contain SRAM macros with redundant elements for failure relief.
    Type: Application
    Filed: June 30, 2008
    Publication date: October 23, 2008
    Inventors: Tom Y. Chang, William V. Huott, Thomas J. Knips, Donald W. Plass
  • Publication number: 20080244340
    Abstract: There is provided a test apparatus for testing a memory under test that includes therein a plurality of blocks and one or more repairing columns.
    Type: Application
    Filed: September 14, 2007
    Publication date: October 2, 2008
    Inventor: MASARU DOI
  • Publication number: 20080222453
    Abstract: A method for emulating and debugging a microcontroller. In one embodiment, an event thread is executed on an emulator that operates in lock-step with the microcontroller. Event information is sampled at selected points. Trace information is also recorded at the selected points. As such, the event information and trace information are effectively pre-filtered. Accordingly, it is not incumbent on a designer to read and understand the event and trace information and sort out the information that is of interest. Instead, this task is essentially done automatically, helping the designer and reducing the probability of error. Furthermore, because only selected event and trace information is recorded, the resources of the in-circuit emulator system are not taxed.
    Type: Application
    Filed: May 22, 2008
    Publication date: September 11, 2008
    Inventors: Manfred Bartz, Craig Nemecek, Matt Pleis