Abstract: A central processing unit measurement facility is virtualized in order to support concurrent use of the facility by multiple guests executing within a virtual environment. Each guest of the environment has independent control over disablement/enablement of the facility for that guest.

Abstract: The disclosure provides an approach for obscuring the organization of data within a storage system by embedding virtual machines within blocks of the storage system. A storage system may receive a command comprising an address. The address may correspond to a location of an embedded virtual machine within the storage system. The virtual machine instantiates and executes an opaque algorithm, the algorithm returning a new address. The new address corresponds to the real location of data on with the command is executed. The logic of the algorithm is obscured within the virtual machine, making the algorithm less predictable and thus, more secure.

Abstract: A method, computer program product, and computer system for editing code, by a computing device, via an integrated development environment. The code is determined to be syntactically valid. While editing the code, a subset of automated tests associated with the code is executed in response to determining that the code is syntactically valid. It is determined whether at least one automated test error is detected. The at least one automated test error is reported.

Abstract: A memory apparatus includes a host device and a slave device. The host device stores verification data. The slave device includes a memory unit, a control unit, and a logic unit. The control unit drives the memory unit to provide storage data in a data transmission sub-period, and further provides a control signal, indicating the first verification data, in a dummy sub-period. The logic unit provides first preamble data, indicating substantially a same data value as the verification data, in the dummy sub-period in response to the first control signal. The preamble data and the storage data are transmitted according to an internal clock signal. The host device samples the first preamble data according to an external clock signal, and determines whether the external and the internal clock signals are synchronized by comparing the first preamble data and the first verification data.

Abstract: A system, method, and computer program product are provided for redirecting internet relay chat (IRC) traffic identified utilizing a port-independent algorithm and controlling IRC based malware. In use, IRC traffic communicated via a network is identified utilizing a port-independent algorithm. Furthermore, the IRC traffic is redirected to a honeypot.

Abstract: An improved USB host controller and method supports concurrent host and device debug operations with only one usable USB port. The described embodiments save silicon cost and avoid additional connectors, which are undesirable in ever-smaller devices.

Abstract: A system and method for efficiently storing traces of multiple components in an embedded system. A system-on-a-chip (SOC) includes a trace unit for collecting and storing trace history, bus event statistics, or both. The SOC may transfer cache coherent messages across multiple buses between a shared memory and a cache coherent controller. The trace unit includes a trace buffer with multiple physical partitions assigned to subsets of the multiple buses. The number of partitions is less than the number of multiple buses. One or more trace instructions may cause a trace history, trace bus event statistics, local time stamps and a global time-base value to be stored in a physical partition within the trace buffer.

Abstract: In some examples, a computer system includes a first component associated with a first power domain and a second component associated with a second power domain. The computer system also includes a debug port with a debug port pin shared by a debug operation pin of the first component and a corresponding debug operation pin of the second component. The computer system also includes a switch associated with the debug port pin to selectively isolate the debug operation pin of the first component from leakage current of the corresponding debug operation pin of the second component.

Abstract: Systems and methods for detecting faults in a system. The method comprising maintaining diagnostic history for one or more system components; receiving system information about operational state and relational interaction among system components; determining if one or more system components are to be examined, in response to performing an analysis of the diagnostic history, wherein the analysis is performed to determine if the diagnostic history includes any information that may indicate that certain system components or combinations of components are suspected of causing a problem detected in the system, wherein the diagnostic history is maintained based on an at least one examination performed on said one or more components when said one or more components were installed in a system other than the system in which the problem is detected.

Abstract: A mechanism is provided for protecting storage fabrics from an errant device causing a single point of failure. The mechanism identities a source of the out-of-context traffic, isolates the TAG to prevent further catastrophe, and ensures that device isolation control operations are processed timely allowing device isolation and removing the source of the issue. Should device isolation not solve the issue, the mechanism allows the host to use a binary search method to isolate the device that may be hiding its true identity and sourcing possibly malicious traffic.

Abstract: A semiconductor memory device includes: a plurality of RAM macros; and a test control circuit configured to correlate the plurality of RAM macros with a plurality of memory test execution periods. The test control circuit outputs control signals to the plurality of RAM macros such that one RAM macro of the plurality of RAM macros is tested during one memory test execution period of the plurality of memory test execution periods, the one RAM macro being correlated with the one memory test execution period.

Abstract: A memory system has a first memory having an array of memory cells that includes a redundant column. The redundant column substitutes for a first column in the array. The first column includes a test memory cell. The array receives a power supply voltage. The test memory cell becomes non-functional at a higher power supply voltage than the memory cells of the array. A memory controller is coupled to the first memory and is for determining if the test memory cell is functional at a first value for the power supply voltage. This is useful in making decisions concerning the value of the power supply voltage applied to the array.

Abstract: Representative locations of a non-volatile, solid-state memory of an apparatus store characterization data. An event during which elapsed time is not measured by the apparatus is determined. In response to the event, temporal degradation of the non-volatile, solid-state memory during the event is estimated based on electrical characteristics of the representative locations.

Abstract: It is provided a storage system for storing write data requested by a host computer, comprising: a data storage device, first and second cache memories, first and second non-volatile memories and at least one power storage device, wherein the storage system stores the requested write data in the data storage device, without storing the requested write data in neither the first cache memory nor the second cache memory in a case where the amount of charge of the at least one power storage device is smaller than the predetermined amount of power, and stores the requested write data in at least one of the first and second cache memories, and then store the requested write data in the data storage device in a case where the amount of charge of the at least one power storage device is equal to or larger than the predetermined amount of power.

Abstract: An abstraction for storage class memory is provided that hides the details of the implementation of storage class memory from a program, and provides a standard channel programming interface for performing certain actions, such as controlling movement of data between main storage and storage class memory or managing storage class memory.

Abstract: Mechanisms are provided in which firmware verifies he entire system's memory scrub coverage through some additional memory controller (MC) registers/attentions and builds up a processor runtime diagnostic (PRD) scrub coverage table during every scrub cycle. Firmware may go through the scrub coverage table rank-by-rank on a periodic basis to determine whether any ranks had not been covered by hardware scrubbing. Firmware may initiate a targeted scrub and diagnostic for all of the ranks that did not have adequate scrub coverage. If for some reason the system still has some memory ranks that have not been covered by the initial hardware scrub and the targeted scrub, then the firmware may perform some course of action for fault isolation.

Abstract: The present disclosure provides a method for operating a storage drive. The method includes receiving a storage command from an initiator and generating an error in response to the storage command. The method also includes adding a check condition data parameter to a check condition log stored to a storage media of the storage drive. The check condition data parameter comprises a physical memory address corresponding to a physical location of a storage element corresponding to the error.

Abstract: In a method for testing a high-definition multimedia interface (HDMI) of a computing device, tests are individually selected and applied to the HDMI. A source code file of the selected test is obtained from a storage system of the computing device. The parameters of the selected test and display resolutions of a display device of the computing device are set. The obtained source code file are executed to apply the selected test to the HDMI according to the set parameters and the display resolutions. After the source code has been executed, the test results are stored.

Abstract: A trace unit, diagnostic apparatus and data processing apparatus are provided for tracing of conditional instructions. The data processing apparatus generates instruction observed indicators indicating execution of conditional instructions and result output indicators indicating output by the data processing apparatus of results of executing respective conditional instructions. The instruction observed indicators and result output indicators are received by a trace unit that is configured to output conditional instruction trace data items and independently output conditional result trace data items enabling separate trace analysis of conditional instructions and corresponding conditional results by a diagnostic apparatus. The instruction observed indicator is received at the trace unit in a first processing cycle of the data processing apparatus whilst result output indicator is received at in a second different processing cycle.

Abstract: Provided are an apparatus and method for detecting a memory access error in a computer system. The apparatus and method may intercept a sub-system that processes a request for access to a memory, and may be applied to various computer systems without causing any performance deterioration. The apparatus includes a sub-system configured to process a request for access to a memory, and an interception module configured to detect a memory access address by intercepting the sub-system.

Abstract: A storage apparatus includes a drive unit device including a plurality of storage drives, a drive interface unit and a power supply unit, the storage drives being configured to provide a physical storage area for creating a logical storage area to be used by an external apparatus, the drive interface unit being configured to input and output data to and from the storage drives, the power supply unit being configured to supply operation power to the storage drives and the drive interface unit, a storage controller including a plurality of processing units and a drive control interface unit, the processing units being configured to perform a data input/output process via the drive interface unit, the data input/output process including a process of writing data from the external apparatus into the storage drives and a process of reading data out of the storage drives, the drive control interface unit being configured to issue a command to the drive interface unit in response to a request from each of the proces

Abstract: A system and method for mitigating memory errors in a computer system. Faulty memory is identified and tested by a memory manager of an operating system. The memory manager may perform diagnostic tests while the operating system is executing on the computer system. Regions of memory that are being used by software components of the computer system may also be tested. The memory manager maintains a stored information about faulty memory regions. Regions are added to the stored information when they are determined to be faulty by a diagnostic test tool. Memory regions are allocated to software components by the memory manager after checking the stored information about faulty memory regions. This ensures a faulty memory region is never allocated to a software component of the computer system.

Abstract: A device for repair analysis includes a selection unit and an analysis unit. The selection unit is configured to select a part of the row addresses of a plurality of spare pivot fault cells and a part of the column addresses of the spare pivot fault cells in response to a control code. The analysis unit is configured to generate an analysis signal indicating whether row addresses of a plurality of non-spare pivot fault cells are included in selected row addresses and column addresses of the non-spare pivot fault cells are included in selected column addresses.

Abstract: A method detects a memory error of a computing device using a baseboard management controller (BMC) of the computing device. The BMC includes a microprocessor and a storage system. The method reads data of a state register of a processor of the computing device when the microprocessor receives an interrupt signal generated by the processor due to an internal error of the processor. Then the method determines whether the internal error is a multiple-bit error of a memory of the computing device according to the read data. Upon the condition that the internal error is the multiple-bit error, the method records error information of the multiple-bit error in the storage system.

Abstract: Various embodiments of a memory system are disclosed. In one exemplary embodiment, the memory system may include a semiconductor memory apparatus configured to generate error check signals in a column direction and a row direction of data groups to be transmitted through a plurality of data input/output terminals in a read operation and output the error check signals together with the data groups, and a memory controller configured to control data read/write operations of the semiconductor memory apparatus, generate error check signals by performing error check in a column direction and a row direction of data groups to be transmitted in a write operation, and provide the error check signals to the semiconductor memory apparatus together with the data groups.

Abstract: A semiconductor memory apparatus includes: a first data counting unit configured to count respective programming levels of a plurality of input data and output a plurality of first data counting codes having a code value corresponding to the number of respective programming levels; a data read unit configured to sense data stored in a memory block having the plurality of input data programmed therein, based on a voltage level of a plurality of read bias signals, and output the sensed result as a plurality of output data; a second data counting unit configured to count respective programming levels of the plurality of output data and output a plurality of second data counting codes having a code value corresponding to the number of respective programming levels; a read bias control unit configured to compare the plurality of first data counting codes with the plurality of second data counting codes and output a bias control code having a code value corresponding to the comparison result; and a read bias genera

Abstract: A memory system according to the embodiment comprises a cell array including cell units having p or more physical quantity levels (p is a prime of 3 or more); a code generator unit operative to convert binary-represented input data to a write code represented by elements in Zp that is a residue field modulo p; and a code write unit operative to write the write code in the cell unit in accordance with the association of the elements in Zp to different physical quantity levels, wherein the input data is recorded in (p?1) cell units, the (p?1) cell units including no cell unit that applies the same physical quantity level for write in the case where the input data is 0 and for write in the case where only 1 bit is 1.

Abstract: An integrated circuit is described that has a substrate with a memory array with dedicated support hardware formed on the substrate. An access wrapper circuit is coupled to address and data lines of the memory array and to control lines of the dedicated support hardware. The wrapper circuit is configured to provide an access port to the memory array. A test controller is formed on the substrate and coupled in parallel with the access wrapper circuit to the address and data lines of the memory array and to the control lines of the dedicated support hardware, wherein the test controller is operable to perform a test of the memory array by manipulating control signals to the support hardware in addition to those required to write data patterns into the memory array and to read the contents of the memory array.

Abstract: One embodiment provides an error detection method wherein single-bit errors in a memory module are detected and identified as being a random error or a repeat error. Each identified random error and each identified repeat error occurring in a time interval is counted. An alert is generated in response to a number of identified random errors reaching a random-error threshold or a number of identified repeat errors reaching a repeat-error threshold during the predefined interval. The repeat-error threshold is set lower than the random-error threshold. A hashing process may be applied to the memory address of each detected error to map the location of the error in the memory system to a corresponding location in an electronic table.

Abstract: A method and a system for testing memory blocks using a built-in-self-test (BIST) block using a regeneration mechanism. The method includes generation of a test pattern by executing a pre-defined algorithm to test a memory address of a memory block. The test pattern is stored at the memory address, and then the stored data is read from the memory address. The read data is send to a comparator for comparison with a background data. The background data corresponds to the test pattern and is regenerated by a regeneration block corresponding to clock cycles taken for storing the test pattern in the memory address. The stored data is read from the memory address. The comparator generates a validity signal based on the comparison of the background data with the read data.

Abstract: A system and method for enabling portable diagnostics in a configurable device. Physical layer device technology can be implemented into a configurable device (e.g., handheld device) to perform diagnostics. The configurable device can be enabled for diagnostics through an authentication module that performs an authentication and/or licensing function. Diagnostic information (e.g., channel characteristics, data analysis, traffic analysis, packet analysis, bit analysis, etc.) can be displayed on a display of the configurable device to assist field personnel.

Abstract: Systems and methods for intelligently reducing the number of log-likelihood ratios (LLRs) stored in memory of a wireless communication device are described herein. In one aspect, the systems and methods described herein relate to selecting LLRs for storage based on a quality metric. In another aspect, the systems and methods described herein relate to improving communication quality in response to available memory capacity.

Abstract: A storage device according to some aspects of the invention includes a communication unit configured to perform processing for communication with a host apparatus; a storage unit configured to have a first memory area and a second memory area that store therein received data from the host apparatus, and memory area selection information; a memory control unit configured to select one of the first memory area and the second memory area as a memory area for reading, select the other one thereof as a memory area for writing, and perform control of reading and writing; and an increment determination unit configured to compare a value of data having been read out from the memory area for reading by the memory control unit and a value of the received data to determine a magnitude relation therebetween.

Abstract: Embodiments of a system and method for testing an integrated circuit device are described herein. Testing is complemented by a determination of characteristics of a data valid window that identifies components of a response data signal from a device under test where the data signal can always be expected to be stable.

Abstract: The disclosed invention provides a structure and method for detecting address line (e.g., wordline, bitline) memory failures. In one embodiment, the method and structure comprise generating an address signature, by re-encoding an internally generated address signal from activated elements (e.g., wordlines) inside a memory array. The regenerated address signature may be compared with a requested memory address location. If the regenerated address signature and memory location are equal than there is no error in the memory array, but if the regenerated address signature and memory location are equal than an error is present in the memory array. Accordingly, re-encoding an address signature provides a closed loop check that a wordline and/or bitline, that was actually activated in a memory array, was the correct requested wordline and/or bitline, that no other wordlines or bitlines were also triggered, and that the wordline and/or bitline is continuous.

Abstract: A memory error detecting apparatus for detecting an error of a subject memory, the memory error detecting apparatus includes a memory bus connected to the subject memory, a mirror memory connected to the memory bus so as to receive the same data as data to be written into and read from the subject memory, the received data being written into the mirror memory, an address acquiring portion configured to acquire an address related to the data written into the subject memory, a mirror memory controller configured to control data writing or reading to or from the mirror memory on the basis of the acquired address, a comparator configured to compare data read from the subject memory and data read from the mirror memory, and an error detector configured to detect a data error on the basis of a result of the comparison.

Abstract: An array built-in self test (ABIST) system includes a first latch having a first data input, a first scan input and first output and a second latch having a second data input, a second scan input and a second output. The system also includes a first ABIST logic block coupled to the first output that compares a first expected value with a first data value received at the first data input and provided to the first ABIST logic block after a first clock is applied to the first latch. The system also includes a second ABIST logic block coupled to the second output that compares a second expected value with a second data value received at the second data input and provided to the second ABIST logic block after a second clock is applied to the second latch.

Abstract: According to one embodiment, a nonvolatile semiconductor memory device comprises a memory cell array, a write control circuit, a latch circuit, an address control circuit, a scan control circuit, and an address latch circuit. The write control circuit executes write and verify for each page of the memory cell array. The latch circuit holds data of the verify result. The address control circuit divides the page into zones and sequentially selects the address of each of the zones. The scan control circuit executes scan so as to count the number of fail bits in zone selected by the address control circuit and determine whether the number of fail bits is not more than the number of allowable bits. The address latch circuit holds the address of a no fail zone, out of the plurality of zones, in which the number of fail bits is 0.

Abstract: One or more embodiments of the invention enable a memory device to load its memory array with desired background data, such as to reduce total test time and costs associated with testing. A background data loading circuit according to one embodiment of the invention includes a buffer, a data loading circuit, and a pattern generating logic. The buffer is coupled to the array of memory cells. The data loading circuit is coupled to load data into the buffer to be transferred to a respective row of the memory cells. The pattern generating logic is coupled to the data loading circuit. The pattern generating logic applies a pattern generating algorithm corresponding to a test mode when the memory devices is in the test mode and generates patterns of data each for a respective row of the memory cells according to the pattern generating algorithm.

Abstract: A system and method for testing a control module includes a microprocessor, where the microprocessor has a programming environment. The programming environment has a test data structure, a configuration data structure, and a monitor data structure each containing data. At least one test data instance is associated with the test data structure and at least one configuration data instance is associated with the configuration data structure. The configuration data instance is a diagnostic test that monitors a parameter of the microprocessor, and the monitor data structure creates the test data instance such that each test data instance corresponds to one of the configuration data instances. The program includes a first control logic for associating the test data structure, the configuration data structure and the monitor data structure as part of a core infrastructure portion of the programming environment, where the core infrastructure portion of the program is static.

Abstract: A memory system is provided with a processor, a main memory, and a flash memory. Performance of the memory system is improved through achievement of speed-up and high data reliability. The memory system includes a nonvolatile memory device and a controller configured to drive a control program to control the nonvolatile memory device. The control program executes a second access operation for the nonvolatile memory device even before a first access operation to the nonvolatile memory device is completed.

Abstract: An object of the present invention is to provide a semiconductor device capable of recognizing circuit malfunction in an actual operation and of specifying a point of the circuit malfunction, and the semiconductor device, which does not induce the malfunction in the circuit of a subsequent stage when restoring the malfunction. The present invention is the semiconductor device provided with a plurality of logic circuits and a plurality of judging circuits for judging malfunction based on data from the logic circuits, wherein each of the judging circuits is provided with a first register, delay unit, a second register, a comparator and scanning unit, which makes the second register a shift register to allow to transmit an error signal held in the second register to the subsequent stage, while allowing the comparator to hold a comparison result.

Abstract: A method for verifying memory device integrity includes identifying at least one memory block corresponding to at least one memory location within a memory device. The memory block is associated with a prior checksum. It is determined whether the first memory block is designated read-only. A current checksum is calculated based at least in part on data within the memory block. When the first memory block is designated read-only, and the prior checksum represents expected data within the first memory block, it is determined whether the current checksum is equal to the prior checksum. When the current checksum is not equal to the prior checksum, a verification failure for the first memory block is indicated via a notification interface. A system for verifying memory device integrity is also disclosed.

Abstract: An apparatus having a memory module and an initialization module is disclosed. The initialization module may be configured to (i) mark a particular location in the memory module as an uninitialized location by writing a predetermined word into the particular location in response to an occurrence of an event, (ii) read a read word from an address in the memory module in response to a read cycle and (iii) generate an interrupt signal by analyzing the read word, the interrupt signal being asserted where the read word indicates that the address is the uninitialized location in the memory module.

Abstract: A test circuit of a semiconductor memory apparatus includes: a first fail detection unit configured to detect a fail of a memory cell group of a first memory block by combining a plurality of first test data signals outputted from the memory cell group of the first memory block; a second fail detection unit configured to detect a fail of a memory cell group of a second memory block by combining a plurality of second test data signals outputted from the memory cell group of the second memory block; a common fail detection unit configured to detect a fail of the memory cell groups of the first and second memory blocks by combining the plurality of first test data signals and the plurality of second test data signals; and a fail determination unit configured to output detection results of the first and second fail detection units or a detection result of the common is fail detection unit according to the detection results of the first and second fail detection units.

Abstract: A plurality of stacked memory device die and a logic circuit are connected to each other through a plurality of conductors. The stacked memory device die are arranged in a plurality of vaults. The logic circuit die serves as a memory interface device to a memory access device, such as a processor. The logic circuit die includes a plurality of link interfaces and downstream targets for transmitting received data to the vaults. The logic circuit die includes a packet builder and broadcaster configured to receive command, address and data signals over separate interfaces from a conventional tester, format the signals into a packet and broadcast the signals to a plurality of vaults.

Abstract: A semiconductor integrated circuit device related to an embodiment of the present invention includes an address register which includes an internal selection circuit connected with a control circuit, a signal generation instruction circuit which instructs the control circuit so that a predetermined internal control signal is generated, a latch circuit, a plurality of which are arranged corresponding to a number of bits of test parameter data, the latch circuit latching test result data which is provided from the data program/read circuit and outputting the test result data to the selection circuit and externally, the control circuit generating an internal control signal which activates the selection circuit at a timing at which a fixed value data of the test parameter data is changed, and the selection circuit controlling a test so that a fixed value data of the test parameter data is changed.

Abstract: Apparatus and methods, such as those that read data from non-volatile integrated circuit memory devices, such as NAND flash. For example, disclosed techniques can be embodied in a device driver of an operating system. Errors are tracked during read operations. If sufficient errors are observed during read operations, the block is then retired when it is requested to be erased or a page of the block is to be written. One embodiment is a technique to recover data from uncorrectable errors. For example, a read mode can be changed to a more reliable read mode to attempt to recover data. One embodiment further returns data from the memory device regardless of whether the data was correctable by decoding of error correction code data or not.

Abstract: Systems and methods are disclosed for performing run-time tests on a non-volatile memory (“NVM”), such as flash memory. The run-time tests may be tests that are performed on the NVM while the NVM can be operated by an end user (as opposed to during a manufacturing phase). In some embodiments, a controller for the NVM may detect an error event that may be indicative of a systemic failure of a die of the NVM. The controller may then select one or more blocks in the die to test, which may be dies that are currently not being used to store user data. The controller may post process the results of the test to determine whether there is a systemic failure, such as a column failure, and may treat the systemic failure if there is one.

Abstract: A semiconductor device includes a decoder, a first register unit, and a second register unit. The decoder generates first and second register control signals in response to an external test code signal. The first register unit is coupled to the decoder. The first register unit receives the first register control signal from the decoder. The first register unit outputs in series a plurality of test signals in response to the first register control signal. The second register unit is coupled to the first register unit. The second register unit receives the first and second register control signals from the decoder. The second register unit receives in series the plurality of test signals from the first register unit in response to the first register control signal. The second register unit outputs in parallel the plurality of test signals in response to the second register control signal.