Abstract: A hard disk status testing apparatus, including: a voltage reading module, a controller, an analogue switch, and multiple hard disk slot units. Each hard disk slot unit includes: a hard disk status testing module and a hard disk status indication module. The hard disk status testing modules and the hard disk status indication modules among different hard disk slot units are time-multiplexed, achieving independent control of the hard disk status testing modules of different hard disk slot units and independent control of the hard disk status indication modules of different hard disk slot units. A hard disk status testing method that effectively solves the problem of an increase in the number of pins needed for hard disk status testing and status indication, thus effectively decreasing hardware costs and increasing the utilization rate of pin resources.

Abstract: An apparatus and method for efficiently updating power supply voltages due to degradation from aging. A computing system includes one or more functional units and a runtime voltage calibrator (or calibrator). The calibrator is capable of performing power supply calibration for the one or more supply voltage power rail used by the one or more functional units. The calibrator identifies a particular ground reference power rail that is received by the one or more functional units. The calibrator also identifies a first supply voltage power rail that is received by at least a first functional unit of the one or more functional units. If the runtime voltage calibrator determines that all circuitry that uses the particular ground reference power rail is idle, the calibrator performs power supply calibration for the first supply voltage power rail. The calibrator does not wait for a bootup operation and avoids interference from ground bounce.

Abstract: A fan management system includes a fan and a server. The fan includes a driving circuit, and the driving circuit is configured for driving the fan. The fan operates in an operation mode. The server is connected to the fan and is configured for controlling the operation of the fan. The driving circuit outputs a digital label signal when the fan operates abnormally, and the server obtains a production history, an operation information and a warning message of the fan through the digital label signal. The server adjusts the operation mode of the fan according to the warning message simultaneously.

Abstract: User configurable hardware settings for overclocking is described. In accordance with the described techniques, user input to adjust hardware settings for operating a processing unit in an overclocking mode is received. The user input, for example, adjusts at least one of a voltage droop threshold or a frequency adjustment of the clock rate. A voltage droop is detected while operating the processing unit in the overclocking mode. Responsive to detecting the voltage droop, a clock rate of the processing unit is adjusted based at least in part on the adjusted hardware settings.

Abstract: A dummy dual in-line memory module (DIMM) testing system based on boundary scan interconnect and a method thereof. A dummy dual in-line memory module functioning normally is used as a test fixture, a dummy dual in-line memory module under test is served as an unit under test (UUT), and the test fixture and the unit under test are inserted into a test device to electrically connect to each other, so that the test access port (TAP) device can perform boundary scan to control the test fixture to test the unit under test through signal pins, and check a test result based on a data signal collected from at least one boundary scan register. Therefore, the effect of improving testing convenience of the dummy DIMM can be achieved.

Abstract: Embodiments of this present disclosure may include a system with a first power converter and a control system. The first power converter may supply a first current to a first backplane while a second power converter is concurrently supplying a second current to a second backplane. The first backplane and the second backplane may electrically couple to one or more load components and the control system. The control system may cause the first power converter to adjust the first current such that the first current and the second current are imbalanced with respect to each other in response to receiving a request to verify that the second power converter is capable of supplying the one or more load components with a target current value while the first current and the second current are imbalanced.

Abstract: A control module is adapted to control technical equipment by processing batch-run data from the technical equipment. The control module operates according to parameters that are obtained by a parameter module. The module receives a reference plurality of multi-variate reference time series with data values from sources that are related to the equipment. There are time series with measurement values and time series with data that describes particular manufacturing operations during a batch-run time interval. The module splits the time interval into phases by determining transitions between the particular manufacturing operations, and divides the time series into particular phase-specific partial series. For each phase separately, and for the phase-specific partial series in combination, the module differentiates phase-specific time series into relevant partial time series or non-relevant partial time series and set the parameters accordingly.

Abstract: A burn-in board includes: a board; sockets mounted on the board; a connector mounted on the board; and wiring systems disposed in the board and connecting the sockets and the connector. The wiring systems comprise: a first wiring system that transmits a first signal; and a second wiring system that transmits a second signal different from the first signal, and a type of a first connection form of the first wiring system is different from a type of a second connection form of the second wiring system.

Abstract: A semiconductor device and a method of testing the same are provided. A semiconductor device includes a Design Under Test (DUT), a processing core configured to execute test software to determine an optimum operating voltage of the DUT, and a protection circuit configured to block the transmission of undefined signals generated by the DUT while the processing core executes the test software.

Abstract: The present invention provides a smart overclocking method for a computer device with a multi-core CPU and abasic input/output system (BIOS) where an overclocking database is stored therein, which comprises: booting the computer device, logging in the BIOS and performing an overclocking function; acquiring overclocking parameters from the overclocking database; conducting adjustment/settlement of the clock rate and the voltage of the multi-core CPU based on the overclocking parameters; conducting a Heavy Load Testing (HLT) on the multi-core CPU; reading out working results data of the multi-core CPU and determining whether any of them have exceeded limits. Hence, overclocking can be completed within 10 min. or less, without causing shut down of the computer device, and without causing working temperature or working voltage of multi-core CPU to be higher than 90° C. or 1500 mV during Heavy Load Testing (HLT).

Abstract: Techniques for environmental contaminant monitoring are disclosed. In some embodiments, a contaminant detection system electronically instigates a test circuit that shares an environment with another circuit to induce an electrical anomaly in the test circuit when environmental contamination is present. While electronically instigating the first circuit, the contaminant detection system monitors for an electrical anomaly indicative of the environmental contamination. Responsive to detecting an electrical anomaly in the test circuit that is indicative of environmental contamination, the contaminant detection system generates an alert that indicates that the second circuit has likely been exposed to the environmental contamination. The contaminant detection system may provide early warning of potentially caustic environments before creep corrosion or similar phenomena manifest in expensive hardware resources. Thus, hardware outages may be mitigated or avoided.

Abstract: A stand-alone bridging test method is provided, which is applied to a stand-alone bridging device. The stand-alone bridging device is coupled to a storage device. The stand-alone bridging device includes a bridging controller. The storage device includes a device controller and a device memory. The stand-alone bridging test method includes the bridging controller generates a handshaking test signal and transmits the handshaking test signal to the device controller. The device controller generates a confirmation test signal according to the handshaking test signal and transmits the confirmation test signal to the bridging controller. The bridging controller generates a test data according to the confirmation test signal and transmits a write command to the device controller to write the test data into the device memory. The bridging controller transmits a read command to the device controller to read a stored data of the device memory.

Abstract: A system including a baseboard management controller (BMC) and a socket is described. The BMC is configured to provide a management interface to a network device. The socket is configured to accept an edge connector of a removable storage card. The BMC is configured to access via the socket at least a portion of the firmware of the BMC stored on the removable storage card.

Abstract: A system and method for providing status information during a power-on self-test routine. The system includes a basic input output system operable to execute the power-on self-test routine and output the status of the power-on self-test routine. The system includes an externally visible indicator such as a server chassis identify LED. A controller is coupled to the basic input output system and the externally visible indicator. The controller is operable to receive the status from the basic input output system, and to control the externally visible indicator in response to the status received from the basic input output system.

Abstract: A system for monitoring electrostatic charge buildup and electrostatic discharge (ESD) remotely comprises a plurality of electrostatic charge measurement units and a data acquisition device. Each electrostatic charge measurement unit includes a primary charge plate, a static sensor device, a secondary charge plate, and a shielded cable. The primary charge plate is positioned proximal to an object. The static sensor device includes an input sensor at which an electric voltage is measured and outputs an electronic signal whose level varies according to the measured electric voltage. The secondary charge plate is positioned in proximity to the input sensor of the static sensor device. The shielded cable includes an inner conductor electrically connected to the primary charge plate and the secondary charge plate and an outer conductor electrically connected to electrical ground. The data acquisition device receives the electronic signal from the static sensor device of each electrostatic charge measurement unit.

Abstract: Systems, apparatuses and methods may provide for technology that detects a successful boot of a first firmware component in a computing system, receives a signal from a second firmware component in the computing system, and detects an incompatibility of the first firmware component with respect to the second firmware component based on the signal. In one example, only the first firmware component is repaired in response to the incompatibility.

Abstract: A method for resource allocation, a terminal, and a computer-readable storage medium are provided. The method includes the following. A target application sends scene information to an operating system through a data channel established with the operating system, where the scene information is indicative of a running scene of the target application. The operating system acquires a target optimization configuration file corresponding to the scene information, where the target optimization configuration file contains optimization configuration information corresponding to different running time periods in the running scene, and the optimization configuration information is indicative of a manner for system resource allocation. The operating system acquires target optimization configuration information corresponding to a current running time period from the target optimization configuration file.

Abstract: The present disclosure provides a method for providing a fatal error of a system-on-chip product and a method for identifying a fatal error of a system-on-chip product. The system-on-chip product includes a processor. The method for providing a fatal error of a system-on-chip product includes: when a fatal error occurs, setting a port value of a preset port of the processor as a preset value corresponding to the fatal error; converting the preset value into register data accessible to an external server, such that the external server can identify the fatal error that occurs in the system-on-chip product according to the preset value when acquiring the register data. Through the present disclosure, even if the system-on-chip product does not support a baseboard management controller, the user of the baseboard can still obtain the reason for the error of the product through an out-of-band method.

Abstract: A chip with a built-in self-test (BIST) component capable of testing the linearity of an ADC is described herein. The BIST component uses hardware registers to facilitate a sliding histogram technique to save space on the chip. A subset of detected digital codes are analyzed, and DNL and INL calculations are performed by a controller to determine whether any of the digital codes in the subset exceed maximum or minimum DNL and INL thresholds. New digital codes being detected by the ADC are added to the subset as lower-value digital codes are pushed out of the subset, maintaining the same number of digital codes being analyzed as the subset moves from lower codes detected during lower voltages to higher codes detected at higher voltages. A synchronizer and pointer ensure that the subset moves through the digital codes at the same rate as the analog input ramp source.

Abstract: An apparatus, system, and method are disclosed for a baseboard management controller (BMC) which includes an FPGA with a monitor module for monitoring the operations parameters of a host computer device. In addition, the BMC has a host connector that connects the BMC to the system bus of the host computing device, allowing the BMC access to the computing elements on the host. The host connector has reconfigurable pins with connection configuration controlled by the FPGA. In addition, the BMC has a server with a processor and associated non-volatile memory on board. The operating system provides services to the host computing device and its constituent components, as well as allowing advanced networking and interconnectivity with other BMCs in a management network.